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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2023 Intel Corporation4 */5 6#ifndef _XE_REG_DEFS_H_7#define _XE_REG_DEFS_H_8 9#include <linux/build_bug.h>10 11#include "compat-i915-headers/i915_reg_defs.h"12 13/**14 * struct xe_reg - Register definition15 *16 * Register defintion to be used by the individual register. Although the same17 * definition is used for xe_reg and xe_reg_mcr, they use different internal18 * APIs for accesses.19 */20struct xe_reg {21 union {22 struct {23 /** @addr: address */24 u32 addr:28;25 /**26 * @masked: register is "masked", with upper 16bits used27 * to identify the bits that are updated on the lower28 * bits29 */30 u32 masked:1;31 /**32 * @mcr: register is multicast/replicated in the33 * hardware and needs special handling. Any register34 * with this set should also use a type of xe_reg_mcr_t.35 * It's only here so the few places that deal with MCR36 * registers specially (xe_sr.c) and tests using the raw37 * value can inspect it.38 */39 u32 mcr:1;40 /**41 * @vf: register is accessible from the Virtual Function.42 */43 u32 vf:1;44 /**45 * @ext: access MMIO extension space for current register.46 */47 u32 ext:1;48 };49 /** @raw: Raw value with both address and options */50 u32 raw;51 };52};53static_assert(sizeof(struct xe_reg) == sizeof(u32));54 55/**56 * struct xe_reg_mcr - MCR register definition57 *58 * MCR register is the same as a regular register, but uses another type since59 * the internal API used for accessing them is different: it's never correct to60 * use regular MMIO access.61 */62struct xe_reg_mcr {63 /** @__reg: The register */64 struct xe_reg __reg;65};66 67 68/**69 * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the70 * written bits on the lower 16 bits.71 *72 * It only applies to registers explicitly marked in bspec with73 * "Access: Masked". Registers with this option can have write operations to74 * specific lower bits by setting the corresponding upper bits. Other bits will75 * not be affected. This allows register writes without needing a RMW cycle and76 * without caching in software the register value.77 *78 * Example: a write with value 0x00010001 will set bit 0 and all other bits79 * retain their previous values.80 *81 * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER()82 */83#define XE_REG_OPTION_MASKED .masked = 184 85/**86 * XE_REG_OPTION_VF - Register is "VF" accessible.87 *88 * To be used with XE_REG() and XE_REG_INITIALIZER().89 */90#define XE_REG_OPTION_VF .vf = 191 92/**93 * XE_REG_INITIALIZER - Initializer for xe_reg_t.94 * @r_: Register offset95 * @...: Additional options like access mode. See struct xe_reg for available96 * options.97 *98 * Register field is mandatory, and additional options may be passed as99 * arguments. Usually ``XE_REG()`` should be preferred since it creates an100 * object of the right type. However when initializing static const storage,101 * where a compound statement is not allowed, this can be used instead.102 */103#define XE_REG_INITIALIZER(r_, ...) { .addr = r_, __VA_ARGS__ }104 105 106/**107 * XE_REG - Create a struct xe_reg from offset and additional flags108 * @r_: Register offset109 * @...: Additional options like access mode. See struct xe_reg for available110 * options.111 */112#define XE_REG(r_, ...) ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__))113 114/**115 * XE_REG_EXT - Create a struct xe_reg from extension offset and additional116 * flags117 * @r_: Register extension offset118 * @...: Additional options like access mode. See struct xe_reg for available119 * options.120 */121#define XE_REG_EXT(r_, ...) \122 ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .ext = 1))123 124/**125 * XE_REG_MCR - Create a struct xe_reg_mcr from offset and additional flags126 * @r_: Register offset127 * @...: Additional options like access mode. See struct xe_reg for available128 * options.129 */130#define XE_REG_MCR(r_, ...) ((const struct xe_reg_mcr){ \131 .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \132 })133 134static inline bool xe_reg_is_valid(struct xe_reg r)135{136 return r.addr;137}138 139#endif140