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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2022 Intel Corporation4 */5 6#ifndef _XE_GT_TOPOLOGY_H_7#define _XE_GT_TOPOLOGY_H_8 9#include "xe_gt_types.h"10 11/*12 * Loop over each DSS with the bit is 1 in geometry or compute mask13 * @dss: iterated DSS bit from the DSS mask14 * @gt: GT structure15 */16#define for_each_dss(dss, gt) \17 for_each_or_bit((dss), \18 (gt)->fuse_topo.g_dss_mask, \19 (gt)->fuse_topo.c_dss_mask, \20 XE_MAX_DSS_FUSE_BITS)21 22struct drm_printer;23 24void xe_gt_topology_init(struct xe_gt *gt);25 26void xe_gt_topology_dump(struct xe_gt *gt, struct drm_printer *p);27 28unsigned int29xe_dss_mask_group_ffs(const xe_dss_mask_t mask, int groupsize, int groupnum);30 31bool xe_dss_mask_empty(const xe_dss_mask_t mask);32 33bool34xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad);35 36bool xe_gt_has_geometry_dss(struct xe_gt *gt, unsigned int dss);37bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss);38 39#endif /* _XE_GT_TOPOLOGY_H_ */40