368 lines · c
1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2022 Intel Corporation4 */5 6#ifndef _XE_GUC_FWIF_H7#define _XE_GUC_FWIF_H8 9#include <linux/bits.h>10 11#include "abi/guc_klvs_abi.h"12 13#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 414#define G2H_LEN_DW_DEREGISTER_CONTEXT 315#define G2H_LEN_DW_TLB_INVALIDATE 316 17#define GUC_ID_MAX 6553518 19#define GUC_CONTEXT_DISABLE 020#define GUC_CONTEXT_ENABLE 121 22#define GUC_CLIENT_PRIORITY_KMD_HIGH 023#define GUC_CLIENT_PRIORITY_HIGH 124#define GUC_CLIENT_PRIORITY_KMD_NORMAL 225#define GUC_CLIENT_PRIORITY_NORMAL 326#define GUC_CLIENT_PRIORITY_NUM 427 28#define GUC_RENDER_ENGINE 029#define GUC_VIDEO_ENGINE 130#define GUC_BLITTER_ENGINE 231#define GUC_VIDEOENHANCE_ENGINE 332#define GUC_VIDEO_ENGINE2 433#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)34 35#define GUC_RENDER_CLASS 036#define GUC_VIDEO_CLASS 137#define GUC_VIDEOENHANCE_CLASS 238#define GUC_BLITTER_CLASS 339#define GUC_COMPUTE_CLASS 440#define GUC_GSC_OTHER_CLASS 541#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS42#define GUC_MAX_ENGINE_CLASSES 1643#define GUC_MAX_INSTANCES_PER_CLASS 3244 45/* Helper for context registration H2G */46struct guc_ctxt_registration_info {47 u32 flags;48 u32 context_idx;49 u32 engine_class;50 u32 engine_submit_mask;51 u32 wq_desc_lo;52 u32 wq_desc_hi;53 u32 wq_base_lo;54 u32 wq_base_hi;55 u32 wq_size;56 u32 hwlrca_lo;57 u32 hwlrca_hi;58};59#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)60 61/* 32-bit KLV structure as used by policy updates and others */62struct guc_klv_generic_dw_t {63 u32 kl;64 u32 value;65} __packed;66 67/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */68struct guc_update_exec_queue_policy_header {69 u32 action;70 u32 guc_id;71} __packed;72 73struct guc_update_exec_queue_policy {74 struct guc_update_exec_queue_policy_header header;75 struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];76} __packed;77 78/* GUC_CTL_* - Parameters for loading the GuC */79#define GUC_CTL_LOG_PARAMS 080#define GUC_LOG_VALID BIT(0)81#define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1)82#define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2)83#define GUC_LOG_LOG_ALLOC_UNITS BIT(3)84#define GUC_LOG_CRASH_SHIFT 485#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)86#define GUC_LOG_DEBUG_SHIFT 687#define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT)88#define GUC_LOG_CAPTURE_SHIFT 1089#define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT)90#define GUC_LOG_BUF_ADDR_SHIFT 1291 92#define GUC_CTL_WA 193#define GUC_WA_GAM_CREDITS BIT(10)94#define GUC_WA_DUAL_QUEUE BIT(11)95#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)96#define GUC_WA_CONTEXT_ISOLATION BIT(15)97#define GUC_WA_PRE_PARSER BIT(14)98#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)99#define GUC_WA_POLLCS BIT(18)100#define GUC_WA_RENDER_RST_RC6_EXIT BIT(19)101#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)102#define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22)103 104#define GUC_CTL_FEATURE 2105#define GUC_CTL_ENABLE_SLPC BIT(2)106#define GUC_CTL_DISABLE_SCHEDULER BIT(14)107 108#define GUC_CTL_DEBUG 3109#define GUC_LOG_VERBOSITY_SHIFT 0110#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)111#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)112#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)113#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)114#define GUC_LOG_VERBOSITY_MIN 0115#define GUC_LOG_VERBOSITY_MAX 3116#define GUC_LOG_VERBOSITY_MASK 0x0000000f117#define GUC_LOG_DESTINATION_MASK (3 << 4)118#define GUC_LOG_DISABLED (1 << 6)119#define GUC_PROFILE_ENABLED (1 << 7)120 121#define GUC_CTL_ADS 4122#define GUC_ADS_ADDR_SHIFT 1123#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)124 125#define GUC_CTL_DEVID 5126 127#define GUC_CTL_MAX_DWORDS 14128 129/* Scheduling policy settings */130 131#define GLOBAL_POLICY_MAX_NUM_WI 15132 133/* Don't reset an engine upon preemption failure */134#define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)135 136#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000137 138struct guc_policies {139 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];140 /*141 * In micro seconds. How much time to allow before DPC processing is142 * called back via interrupt (to prevent DPC queue drain starving).143 * Typically 1000s of micro seconds (example only, not granularity).144 */145 u32 dpc_promote_time;146 147 /* Must be set to take these new values. */148 u32 is_valid;149 150 /*151 * Max number of WIs to process per call. A large value may keep CS152 * idle.153 */154 u32 max_num_work_items;155 156 u32 global_flags;157 u32 reserved[4];158} __packed;159 160/* GuC MMIO reg state struct */161struct guc_mmio_reg {162 u32 offset;163 u32 value;164 u32 flags;165 u32 mask;166#define GUC_REGSET_MASKED BIT(0)167#define GUC_REGSET_MASKED_WITH_VALUE BIT(2)168#define GUC_REGSET_RESTORE_ONLY BIT(3)169} __packed;170 171/* GuC register sets */172struct guc_mmio_reg_set {173 u32 address;174 u16 count;175 u16 reserved;176} __packed;177 178/* Generic GT SysInfo data types */179#define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0180#define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1181#define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2182#define GUC_GENERIC_GT_SYSINFO_MAX 16183 184/* HW info */185struct guc_gt_system_info {186 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];187 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];188 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];189} __packed;190 191enum {192 GUC_CAPTURE_LIST_INDEX_PF = 0,193 GUC_CAPTURE_LIST_INDEX_VF = 1,194 GUC_CAPTURE_LIST_INDEX_MAX = 2,195};196 197/* GuC Additional Data Struct */198struct guc_ads {199 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];200 u32 reserved0;201 u32 scheduler_policies;202 u32 gt_system_info;203 u32 reserved1;204 u32 control_data;205 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];206 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];207 u32 private_data;208 u32 um_init_data;209 u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];210 u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];211 u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];212 u32 wa_klv_addr_lo;213 u32 wa_klv_addr_hi;214 u32 wa_klv_size;215 u32 reserved[11];216} __packed;217 218/* Engine usage stats */219struct guc_engine_usage_record {220 u32 current_context_index;221 u32 last_switch_in_stamp;222 u32 reserved0;223 u32 total_runtime;224 u32 reserved1[4];225} __packed;226 227struct guc_engine_usage {228 struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];229} __packed;230 231/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */232enum xe_guc_recv_message {233 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),234 XE_GUC_RECV_MSG_EXCEPTION = BIT(30),235};236 237/* Page fault structures */238struct access_counter_desc {239 u32 dw0;240#define ACCESS_COUNTER_TYPE BIT(0)241#define ACCESS_COUNTER_SUBG_LO GENMASK(31, 1)242 243 u32 dw1;244#define ACCESS_COUNTER_SUBG_HI BIT(0)245#define ACCESS_COUNTER_RSVD0 GENMASK(2, 1)246#define ACCESS_COUNTER_ENG_INSTANCE GENMASK(8, 3)247#define ACCESS_COUNTER_ENG_CLASS GENMASK(11, 9)248#define ACCESS_COUNTER_ASID GENMASK(31, 12)249 250 u32 dw2;251#define ACCESS_COUNTER_VFID GENMASK(5, 0)252#define ACCESS_COUNTER_RSVD1 GENMASK(7, 6)253#define ACCESS_COUNTER_GRANULARITY GENMASK(10, 8)254#define ACCESS_COUNTER_RSVD2 GENMASK(16, 11)255#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)256 257 u32 dw3;258#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)259} __packed;260 261enum guc_um_queue_type {262 GUC_UM_HW_QUEUE_PAGE_FAULT = 0,263 GUC_UM_HW_QUEUE_PAGE_FAULT_RESPONSE,264 GUC_UM_HW_QUEUE_ACCESS_COUNTER,265 GUC_UM_HW_QUEUE_MAX266};267 268struct guc_um_queue_params {269 u64 base_dpa;270 u32 base_ggtt_address;271 u32 size_in_bytes;272 u32 rsvd[4];273} __packed;274 275struct guc_um_init_params {276 u64 page_response_timeout_in_us;277 u32 rsvd[6];278 struct guc_um_queue_params queue_params[GUC_UM_HW_QUEUE_MAX];279} __packed;280 281enum xe_guc_fault_reply_type {282 PFR_ACCESS = 0,283 PFR_ENGINE,284 PFR_VFID,285 PFR_ALL,286 PFR_INVALID287};288 289enum xe_guc_response_desc_type {290 TLB_INVALIDATION_DESC = 0,291 FAULT_RESPONSE_DESC292};293 294struct xe_guc_pagefault_desc {295 u32 dw0;296#define PFD_FAULT_LEVEL GENMASK(2, 0)297#define PFD_SRC_ID GENMASK(10, 3)298#define PFD_RSVD_0 GENMASK(17, 11)299#define XE2_PFD_TRVA_FAULT BIT(18)300#define PFD_ENG_INSTANCE GENMASK(24, 19)301#define PFD_ENG_CLASS GENMASK(27, 25)302#define PFD_PDATA_LO GENMASK(31, 28)303 304 u32 dw1;305#define PFD_PDATA_HI GENMASK(11, 0)306#define PFD_PDATA_HI_SHIFT 4307#define PFD_ASID GENMASK(31, 12)308 309 u32 dw2;310#define PFD_ACCESS_TYPE GENMASK(1, 0)311#define PFD_FAULT_TYPE GENMASK(3, 2)312#define PFD_VFID GENMASK(9, 4)313#define PFD_RSVD_1 GENMASK(11, 10)314#define PFD_VIRTUAL_ADDR_LO GENMASK(31, 12)315#define PFD_VIRTUAL_ADDR_LO_SHIFT 12316 317 u32 dw3;318#define PFD_VIRTUAL_ADDR_HI GENMASK(31, 0)319#define PFD_VIRTUAL_ADDR_HI_SHIFT 32320} __packed;321 322struct xe_guc_pagefault_reply {323 u32 dw0;324#define PFR_VALID BIT(0)325#define PFR_SUCCESS BIT(1)326#define PFR_REPLY GENMASK(4, 2)327#define PFR_RSVD_0 GENMASK(9, 5)328#define PFR_DESC_TYPE GENMASK(11, 10)329#define PFR_ASID GENMASK(31, 12)330 331 u32 dw1;332#define PFR_VFID GENMASK(5, 0)333#define PFR_RSVD_1 BIT(6)334#define PFR_ENG_INSTANCE GENMASK(12, 7)335#define PFR_ENG_CLASS GENMASK(15, 13)336#define PFR_PDATA GENMASK(31, 16)337 338 u32 dw2;339#define PFR_RSVD_2 GENMASK(31, 0)340} __packed;341 342struct xe_guc_acc_desc {343 u32 dw0;344#define ACC_TYPE BIT(0)345#define ACC_TRIGGER 0346#define ACC_NOTIFY 1347#define ACC_SUBG_LO GENMASK(31, 1)348 349 u32 dw1;350#define ACC_SUBG_HI BIT(0)351#define ACC_RSVD0 GENMASK(2, 1)352#define ACC_ENG_INSTANCE GENMASK(8, 3)353#define ACC_ENG_CLASS GENMASK(11, 9)354#define ACC_ASID GENMASK(31, 12)355 356 u32 dw2;357#define ACC_VFID GENMASK(5, 0)358#define ACC_RSVD1 GENMASK(7, 6)359#define ACC_GRANULARITY GENMASK(10, 8)360#define ACC_RSVD2 GENMASK(16, 11)361#define ACC_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)362 363 u32 dw3;364#define ACC_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)365} __packed;366 367#endif368