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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2022 Intel Corporation4 */5 6/* Internal to xe_pcode */7 8#include "regs/xe_reg_defs.h"9 10#define PCODE_MAILBOX XE_REG(0x138124)11#define PCODE_READY REG_BIT(31)12#define PCODE_MB_PARAM2 REG_GENMASK(23, 16)13#define PCODE_MB_PARAM1 REG_GENMASK(15, 8)14#define PCODE_MB_COMMAND REG_GENMASK(7, 0)15#define PCODE_ERROR_MASK 0xFF16#define PCODE_SUCCESS 0x017#define PCODE_ILLEGAL_CMD 0x118#define PCODE_TIMEOUT 0x219#define PCODE_ILLEGAL_DATA 0x320#define PCODE_ILLEGAL_SUBCOMMAND 0x421#define PCODE_LOCKED 0x622#define PCODE_GT_RATIO_OUT_OF_RANGE 0x1023#define PCODE_REJECTED 0x1124 25#define PCODE_DATA0 XE_REG(0x138128)26#define PCODE_DATA1 XE_REG(0x13812C)27 28/* Min Freq QOS Table */29#define PCODE_WRITE_MIN_FREQ_TABLE 0x830#define PCODE_READ_MIN_FREQ_TABLE 0x931#define PCODE_FREQ_RING_RATIO_SHIFT 1632 33/* PCODE Init */34#define DGFX_PCODE_STATUS 0x7E35#define DGFX_GET_INIT_STATUS 0x036#define DGFX_INIT_STATUS_COMPLETE 0x137 38#define PCODE_POWER_SETUP 0x7C39#define POWER_SETUP_SUBCOMMAND_READ_I1 0x440#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x541#define POWER_SETUP_I1_WATTS REG_BIT(31)42#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */43#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)44 45#define PCODE_FREQUENCY_CONFIG 0x6e46/* Frequency Config Sub Commands (param1) */47#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x048#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x149/* Domain IDs (param2) */50#define PCODE_MBOX_DOMAIN_HBM 0x251 52struct pcode_err_decode {53 int errno;54 const char *str;55};56 57