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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * ZynqMP Display Driver4 *5 * Copyright (C) 2017 - 2020 Xilinx, Inc.6 *7 * Authors:8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>10 */11 12#ifndef _ZYNQMP_DISP_H_13#define _ZYNQMP_DISP_H_14 15#include <linux/types.h>16 17/*18 * 3840x2160 is advertised as the maximum resolution, but almost any19 * resolutions under a 300Mhz pixel rate would work. Pick 4096x4096.20 */21#define ZYNQMP_DISP_MAX_WIDTH 409622#define ZYNQMP_DISP_MAX_HEIGHT 409623 24/* The DPDMA is limited to 44 bit addressing. */25#define ZYNQMP_DISP_MAX_DMA_BIT 4426 27struct device;28struct drm_format_info;29struct drm_plane_state;30struct platform_device;31struct zynqmp_disp;32struct zynqmp_disp_layer;33struct zynqmp_dpsub;34 35/**36 * enum zynqmp_dpsub_layer_id - Layer identifier37 * @ZYNQMP_DPSUB_LAYER_VID: Video layer38 * @ZYNQMP_DPSUB_LAYER_GFX: Graphics layer39 */40enum zynqmp_dpsub_layer_id {41 ZYNQMP_DPSUB_LAYER_VID,42 ZYNQMP_DPSUB_LAYER_GFX,43};44 45void zynqmp_disp_enable(struct zynqmp_disp *disp);46void zynqmp_disp_disable(struct zynqmp_disp *disp);47int zynqmp_disp_setup_clock(struct zynqmp_disp *disp,48 unsigned long mode_clock);49 50void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp,51 bool enable, u32 alpha);52 53u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,54 unsigned int *num_formats);55u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer,56 unsigned int *num_formats);57void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer);58void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer);59void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,60 const struct drm_format_info *info);61void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer,62 u32 media_bus_format);63int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,64 struct drm_plane_state *state);65 66int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub);67void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub);68 69#endif /* _ZYNQMP_DISP_H_ */70