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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * ZynqMP Display Controller Driver - Register Definitions4 *5 * Copyright (C) 2017 - 2020 Xilinx, Inc.6 *7 * Authors:8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>10 */11 12#ifndef _ZYNQMP_DISP_REGS_H_13#define _ZYNQMP_DISP_REGS_H_14 15#include <linux/bits.h>16 17/* Blender registers */18#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x019#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x420#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x821#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff22#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc23#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(n) ((n) << 1)24#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN BIT(0)25#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x1426#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x027#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444 0x128#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 0x229#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x330#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x431#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE BIT(4)32#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(n) (0x18 + ((n) * 4))33#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US BIT(0)34#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1)35#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8)36#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 937#define ZYNQMP_DISP_V_BLEND_NUM_OFFSET 338#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(n) (0x20 + ((n) * 4))39#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(n) (0x44 + ((n) * 4))40#define ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(n) (0x68 + ((n) * 4))41#define ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(n) (0x74 + ((n) * 4))42#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(n) (0x80 + ((n) * 4))43#define ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(n) (0xa4 + ((n) * 4))44#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_ENABLE 0x1d045#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP1 0x1d446#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP2 0x1d847#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP3 0x1dc48 49/* AV buffer manager registers */50#define ZYNQMP_DISP_AV_BUF_FMT 0x051#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_SHIFT 052#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK (0x1f << 0)53#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_UYVY (0 << 0)54#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY (1 << 0)55#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YVYU (2 << 0)56#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV (3 << 0)57#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16 (4 << 0)58#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24 (5 << 0)59#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI (6 << 0)60#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO (7 << 0)61#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2 (8 << 0)62#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444 (9 << 0)63#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888 (10 << 0)64#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880 (11 << 0)65#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10 (12 << 0)66#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444_10 (13 << 0)67#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_10 (14 << 0)68#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10 (15 << 0)69#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_10 (16 << 0)70#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10 (17 << 0)71#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10 (18 << 0)72#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420 (19 << 0)73#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420 (20 << 0)74#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420 (21 << 0)75#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420_10 (22 << 0)76#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10 (23 << 0)77#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420_10 (24 << 0)78#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_SHIFT 879#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK (0xf << 8)80#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888 (0 << 8)81#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888 (1 << 8)82#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888 (2 << 8)83#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888 (3 << 8)84#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551 (4 << 8)85#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444 (5 << 8)86#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565 (6 << 8)87#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_8BPP (7 << 8)88#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_4BPP (8 << 8)89#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_2BPP (9 << 8)90#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_1BPP (10 << 8)91#define ZYNQMP_DISP_AV_BUF_NON_LIVE_LATENCY 0x892#define ZYNQMP_DISP_AV_BUF_CHBUF(n) (0x10 + ((n) * 4))93#define ZYNQMP_DISP_AV_BUF_CHBUF_EN BIT(0)94#define ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH BIT(1)95#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT 296#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MASK (0xf << 2)97#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX 0xf98#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX 0x399#define ZYNQMP_DISP_AV_BUF_STATUS 0x28100#define ZYNQMP_DISP_AV_BUF_STC_CTRL 0x2c101#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EN BIT(0)102#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_SHIFT 1103#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VSYNC 0104#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VID 1105#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_AUD 2106#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_INT_VSYNC 3107#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE0 0x30108#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE1 0x34109#define ZYNQMP_DISP_AV_BUF_STC_ADJ 0x38110#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS0 0x3c111#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS1 0x40112#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS0 0x44113#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS1 0x48114#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS0 0x4c115#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS1 0x50116#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS0 0x54117#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS1 0x58118#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT0 0x60119#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT1 0x64120#define ZYNQMP_DISP_AV_BUF_OUTPUT 0x70121#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_SHIFT 0122#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK (0x3 << 0)123#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE (0 << 0)124#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM (1 << 0)125#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN (2 << 0)126#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE (3 << 0)127#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_SHIFT 2128#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK (0x3 << 2)129#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE (0 << 2)130#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM (1 << 2)131#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE (2 << 2)132#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_NONE (3 << 2)133#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_SHIFT 4134#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK (0x3 << 4)135#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PL (0 << 4)136#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM (1 << 4)137#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PATTERN (2 << 4)138#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE (3 << 4)139#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN BIT(6)140#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT0 0x74141#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT1 0x78142#define ZYNQMP_DISP_AV_BUF_PATTERN_GEN_SELECT 0x100143#define ZYNQMP_DISP_AV_BUF_CLK_SRC 0x120144#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS BIT(0)145#define ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS BIT(1)146#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING BIT(2)147#define ZYNQMP_DISP_AV_BUF_SRST_REG 0x124148#define ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST BIT(1)149#define ZYNQMP_DISP_AV_BUF_AUDIO_CH_CONFIG 0x12c150#define ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(n) (0x200 + ((n) * 4))151#define ZYNQMP_DISP_AV_BUF_VID_COMP_SF(n) (0x20c + ((n) * 4))152#define ZYNQMP_DISP_AV_BUF_LIVD_VID_COMP_SF(n) (0x218 + ((n) * 4))153#define ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG 0x224154#define ZYNQMP_DISP_AV_BUF_LIVD_GFX_COMP_SF(n) (0x228 + ((n) * 4))155#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG 0x234156#define ZYNQMP_DISP_AV_BUF_4BIT_SF 0x11111157#define ZYNQMP_DISP_AV_BUF_5BIT_SF 0x10842158#define ZYNQMP_DISP_AV_BUF_6BIT_SF 0x10410159#define ZYNQMP_DISP_AV_BUF_8BIT_SF 0x10101160#define ZYNQMP_DISP_AV_BUF_10BIT_SF 0x10040161#define ZYNQMP_DISP_AV_BUF_NULL_SF 0162#define ZYNQMP_DISP_AV_BUF_NUM_SF 3163#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 0x0164#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 0x1165#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 0x2166#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12 0x3167#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK GENMASK(2, 0)168#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB (0x0 << 4)169#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 (0x1 << 4)170#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 (0x2 << 4)171#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY (0x3 << 4)172#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK GENMASK(5, 4)173#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_CB_FIRST BIT(8)174#define ZYNQMP_DISP_AV_BUF_PALETTE_MEMORY 0x400175 176/* Audio registers */177#define ZYNQMP_DISP_AUD_MIXER_VOLUME 0x0178#define ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE 0x20002000179#define ZYNQMP_DISP_AUD_MIXER_META_DATA 0x4180#define ZYNQMP_DISP_AUD_CH_STATUS0 0x8181#define ZYNQMP_DISP_AUD_CH_STATUS1 0xc182#define ZYNQMP_DISP_AUD_CH_STATUS2 0x10183#define ZYNQMP_DISP_AUD_CH_STATUS3 0x14184#define ZYNQMP_DISP_AUD_CH_STATUS4 0x18185#define ZYNQMP_DISP_AUD_CH_STATUS5 0x1c186#define ZYNQMP_DISP_AUD_CH_A_DATA0 0x20187#define ZYNQMP_DISP_AUD_CH_A_DATA1 0x24188#define ZYNQMP_DISP_AUD_CH_A_DATA2 0x28189#define ZYNQMP_DISP_AUD_CH_A_DATA3 0x2c190#define ZYNQMP_DISP_AUD_CH_A_DATA4 0x30191#define ZYNQMP_DISP_AUD_CH_A_DATA5 0x34192#define ZYNQMP_DISP_AUD_CH_B_DATA0 0x38193#define ZYNQMP_DISP_AUD_CH_B_DATA1 0x3c194#define ZYNQMP_DISP_AUD_CH_B_DATA2 0x40195#define ZYNQMP_DISP_AUD_CH_B_DATA3 0x44196#define ZYNQMP_DISP_AUD_CH_B_DATA4 0x48197#define ZYNQMP_DISP_AUD_CH_B_DATA5 0x4c198#define ZYNQMP_DISP_AUD_SOFT_RESET 0xc00199#define ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST BIT(0)200 201#endif /* _ZYNQMP_DISP_REGS_H_ */202