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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * ZynqMP DPSUB Subsystem Driver4 *5 * Copyright (C) 2017 - 2020 Xilinx, Inc.6 *7 * Authors:8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>10 */11 12#ifndef _ZYNQMP_DPSUB_H_13#define _ZYNQMP_DPSUB_H_14 15struct clk;16struct device;17struct drm_bridge;18struct zynqmp_disp;19struct zynqmp_disp_layer;20struct zynqmp_dp;21struct zynqmp_dpsub_drm;22 23#define ZYNQMP_DPSUB_NUM_LAYERS 224 25enum zynqmp_dpsub_port {26 ZYNQMP_DPSUB_PORT_LIVE_VIDEO,27 ZYNQMP_DPSUB_PORT_LIVE_GFX,28 ZYNQMP_DPSUB_PORT_LIVE_AUDIO,29 ZYNQMP_DPSUB_PORT_OUT_VIDEO,30 ZYNQMP_DPSUB_PORT_OUT_AUDIO,31 ZYNQMP_DPSUB_PORT_OUT_DP,32 ZYNQMP_DPSUB_NUM_PORTS,33};34 35enum zynqmp_dpsub_format {36 ZYNQMP_DPSUB_FORMAT_RGB,37 ZYNQMP_DPSUB_FORMAT_YCRCB444,38 ZYNQMP_DPSUB_FORMAT_YCRCB422,39 ZYNQMP_DPSUB_FORMAT_YONLY,40};41 42/**43 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem44 * @dev: The physical device45 * @apb_clk: The APB clock46 * @vid_clk: Video clock47 * @vid_clk_from_ps: True of the video clock comes from PS, false from PL48 * @aud_clk: Audio clock49 * @aud_clk_from_ps: True of the audio clock comes from PS, false from PL50 * @connected_ports: Bitmask of connected ports in the device tree51 * @dma_enabled: True if the DMA interface is enabled, false if the DPSUB is52 * driven by the live input53 * @drm: The DRM/KMS device data54 * @bridge: The DP encoder bridge55 * @disp: The display controller56 * @layers: Video and graphics layers57 * @dp: The DisplayPort controller58 * @dma_align: DMA alignment constraint (must be a power of 2)59 */60struct zynqmp_dpsub {61 struct device *dev;62 63 struct clk *apb_clk;64 struct clk *vid_clk;65 bool vid_clk_from_ps;66 struct clk *aud_clk;67 bool aud_clk_from_ps;68 69 unsigned int connected_ports;70 bool dma_enabled;71 72 struct zynqmp_dpsub_drm *drm;73 struct drm_bridge *bridge;74 75 struct zynqmp_disp *disp;76 struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS];77 struct zynqmp_dp *dp;78 79 unsigned int dma_align;80};81 82bool zynqmp_dpsub_audio_enabled(struct zynqmp_dpsub *dpsub);83unsigned int zynqmp_dpsub_get_audio_clk_rate(struct zynqmp_dpsub *dpsub);84 85void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub);86 87#endif /* _ZYNQMP_DPSUB_H_ */88