151 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Tegra host1x opcodes4 *5 * Copyright (c) 2022 NVIDIA Corporation.6 */7 8#ifndef __HOST1X_OPCODES_H9#define __HOST1X_OPCODES_H10 11#include <linux/types.h>12 13static inline u32 host1x_class_host_wait_syncpt(14 unsigned indx, unsigned threshold)15{16 return host1x_uclass_wait_syncpt_indx_f(indx)17 | host1x_uclass_wait_syncpt_thresh_f(threshold);18}19 20static inline u32 host1x_class_host_load_syncpt_base(21 unsigned indx, unsigned threshold)22{23 return host1x_uclass_load_syncpt_base_base_indx_f(indx)24 | host1x_uclass_load_syncpt_base_value_f(threshold);25}26 27static inline u32 host1x_class_host_wait_syncpt_base(28 unsigned indx, unsigned base_indx, unsigned offset)29{30 return host1x_uclass_wait_syncpt_base_indx_f(indx)31 | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)32 | host1x_uclass_wait_syncpt_base_offset_f(offset);33}34 35static inline u32 host1x_class_host_incr_syncpt_base(36 unsigned base_indx, unsigned offset)37{38 return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)39 | host1x_uclass_incr_syncpt_base_offset_f(offset);40}41 42static inline u32 host1x_class_host_incr_syncpt(43 unsigned cond, unsigned indx)44{45 return host1x_uclass_incr_syncpt_cond_f(cond)46 | host1x_uclass_incr_syncpt_indx_f(indx);47}48 49static inline u32 host1x_class_host_indoff_reg_write(50 unsigned mod_id, unsigned offset, bool auto_inc)51{52 u32 v = host1x_uclass_indoff_indbe_f(0xf)53 | host1x_uclass_indoff_indmodid_f(mod_id)54 | host1x_uclass_indoff_indroffset_f(offset);55 if (auto_inc)56 v |= host1x_uclass_indoff_autoinc_f(1);57 return v;58}59 60static inline u32 host1x_class_host_indoff_reg_read(61 unsigned mod_id, unsigned offset, bool auto_inc)62{63 u32 v = host1x_uclass_indoff_indmodid_f(mod_id)64 | host1x_uclass_indoff_indroffset_f(offset)65 | host1x_uclass_indoff_rwn_read_v();66 if (auto_inc)67 v |= host1x_uclass_indoff_autoinc_f(1);68 return v;69}70 71static inline u32 host1x_opcode_setclass(72 unsigned class_id, unsigned offset, unsigned mask)73{74 return (0 << 28) | (offset << 16) | (class_id << 6) | mask;75}76 77static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)78{79 return (1 << 28) | (offset << 16) | count;80}81 82static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)83{84 return (2 << 28) | (offset << 16) | count;85}86 87static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)88{89 return (3 << 28) | (offset << 16) | mask;90}91 92static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)93{94 return (4 << 28) | (offset << 16) | value;95}96 97static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)98{99 return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),100 host1x_class_host_incr_syncpt(cond, indx));101}102 103static inline u32 host1x_opcode_restart(unsigned address)104{105 return (5 << 28) | (address >> 4);106}107 108static inline u32 host1x_opcode_gather(unsigned count)109{110 return (6 << 28) | count;111}112 113static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)114{115 return (6 << 28) | (offset << 16) | BIT(15) | count;116}117 118static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)119{120 return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;121}122 123static inline u32 host1x_opcode_setstreamid(unsigned streamid)124{125 return (7 << 28) | streamid;126}127 128static inline u32 host1x_opcode_setpayload(unsigned payload)129{130 return (9 << 28) | payload;131}132 133static inline u32 host1x_opcode_gather_wide(unsigned count)134{135 return (12 << 28) | count;136}137 138static inline u32 host1x_opcode_acquire_mlock(unsigned mlock)139{140 return (14 << 28) | (0 << 24) | mlock;141}142 143static inline u32 host1x_opcode_release_mlock(unsigned mlock)144{145 return (14 << 28) | (1 << 24) | mlock;146}147 148#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)149 150#endif151