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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * AMD MP2 PCIe communication driver4 * Copyright 2020-2021 Advanced Micro Devices, Inc.5 * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>6 * Sandeep Singh <Sandeep.singh@amd.com>7 * Basavaraj Natikar <Basavaraj.Natikar@amd.com>8 */9 10#ifndef PCIE_MP2_AMD_H11#define PCIE_MP2_AMD_H12 13#include "amd_sfh_common.h"14 15/* MP2 C2P Message Registers */16#define AMD_C2P_MSG0 0x1050017#define AMD_C2P_MSG1 0x1050418#define AMD_C2P_MSG2 0x1050819 20/* MP2 P2C Message Registers */21#define AMD_P2C_MSG3 0x1068C /* Supported Sensors info */22 23#define V2_STATUS 0x224 25#define HPD_IDX 1626#define ACS_IDX 2227 28#define SENSOR_DISCOVERY_STATUS_MASK GENMASK(5, 3)29#define SENSOR_DISCOVERY_STATUS_SHIFT 330 31/* SFH Command register */32union sfh_cmd_base {33 u32 ul;34 struct {35 u32 cmd_id : 8;36 u32 sensor_id : 8;37 u32 period : 16;38 } s;39 struct {40 u32 cmd_id : 4;41 u32 intr_disable : 1;42 u32 rsvd1 : 3;43 u32 length : 7;44 u32 mem_type : 1;45 u32 sensor_id : 8;46 u32 period : 8;47 } cmd_v2;48};49 50union cmd_response {51 u32 resp;52 struct {53 u32 status : 2;54 u32 out_in_c2p : 1;55 u32 rsvd1 : 1;56 u32 response : 4;57 u32 sub_cmd : 8;58 u32 sensor_id : 6;59 u32 rsvd2 : 10;60 } response_v2;61};62 63union sfh_cmd_param {64 u32 ul;65 struct {66 u32 buf_layout : 2;67 u32 buf_length : 6;68 u32 rsvd : 24;69 } s;70};71 72struct sfh_cmd_reg {73 union sfh_cmd_base cmd_base;74 union sfh_cmd_param cmd_param;75 phys_addr_t phys_addr;76};77 78enum sensor_idx {79 accel_idx = 0,80 gyro_idx = 1,81 mag_idx = 2,82 als_idx = 1983};84 85enum mem_use_type {86 USE_DRAM,87 USE_C2P_REG,88};89 90struct hpd_status {91 union {92 struct {93 u32 object_distance : 16;94 u32 probablity : 8;95 u32 human_presence_actual : 4;96 u32 human_presence_report : 4;97 } shpd;98 u32 val;99 };100};101 102int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id);103int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata);104int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata);105void amd_sfh_set_desc_ops(struct amd_mp2_ops *mp2_ops);106 107#endif108