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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * H/W layer of ISHTP provider device (ISH)4 *5 * Copyright (c) 2014-2016, Intel Corporation.6 */7 8#ifndef _ISHTP_HW_ISH_H_9#define _ISHTP_HW_ISH_H_10 11#include <linux/pci.h>12#include <linux/interrupt.h>13#include "hw-ish-regs.h"14#include "ishtp-dev.h"15 16#define PCI_DEVICE_ID_INTEL_ISH_CHV 0x22D817#define PCI_DEVICE_ID_INTEL_ISH_BXT_Ax 0x0AA218#define PCI_DEVICE_ID_INTEL_ISH_BXT_Bx 0x1AA219#define PCI_DEVICE_ID_INTEL_ISH_APL_Ax 0x5AA220#define PCI_DEVICE_ID_INTEL_ISH_SPT_Ax 0x9D3521#define PCI_DEVICE_ID_INTEL_ISH_CNL_Ax 0x9DFC22#define PCI_DEVICE_ID_INTEL_ISH_GLK_Ax 0x31A223#define PCI_DEVICE_ID_INTEL_ISH_CNL_H 0xA37C24#define PCI_DEVICE_ID_INTEL_ISH_ICL_MOBILE 0x34FC25#define PCI_DEVICE_ID_INTEL_ISH_SPT_H 0xA13526#define PCI_DEVICE_ID_INTEL_ISH_CML_LP 0x02FC27#define PCI_DEVICE_ID_INTEL_ISH_CMP_H 0x06FC28#define PCI_DEVICE_ID_INTEL_ISH_EHL_Ax 0x4BB329#define PCI_DEVICE_ID_INTEL_ISH_TGL_LP 0xA0FC30#define PCI_DEVICE_ID_INTEL_ISH_TGL_H 0x43FC31#define PCI_DEVICE_ID_INTEL_ISH_ADL_S 0x7AF832#define PCI_DEVICE_ID_INTEL_ISH_ADL_P 0x51FC33#define PCI_DEVICE_ID_INTEL_ISH_ADL_N 0x54FC34#define PCI_DEVICE_ID_INTEL_ISH_RPL_S 0x7A7835#define PCI_DEVICE_ID_INTEL_ISH_MTL_P 0x7E4536#define PCI_DEVICE_ID_INTEL_ISH_ARL_H 0x774537#define PCI_DEVICE_ID_INTEL_ISH_ARL_S 0x7F7838#define PCI_DEVICE_ID_INTEL_ISH_LNL_M 0xA84539 40#define REVISION_ID_CHT_A0 0x641#define REVISION_ID_CHT_Ax_SI 0x042#define REVISION_ID_CHT_Bx_SI 0x1043#define REVISION_ID_CHT_Kx_SI 0x2044#define REVISION_ID_CHT_Dx_SI 0x3045#define REVISION_ID_CHT_B0 0xB046#define REVISION_ID_SI_MASK 0x7047 48struct ipc_rst_payload_type {49 uint16_t reset_id;50 uint16_t reserved;51};52 53struct time_sync_format {54 uint8_t ts1_source;55 uint8_t ts2_source;56 uint16_t reserved;57} __packed;58 59struct ipc_time_update_msg {60 uint64_t primary_host_time;61 struct time_sync_format sync_info;62 uint64_t secondary_host_time;63} __packed;64 65enum {66 HOST_UTC_TIME_USEC = 0,67 HOST_SYSTEM_TIME_USEC = 168};69 70struct ish_hw {71 void __iomem *mem_addr;72};73 74/*75 * ISH FW status type76 */77enum {78 FWSTS_AFTER_RESET = 0,79 FWSTS_WAIT_FOR_HOST = 4,80 FWSTS_START_KERNEL_DMA = 5,81 FWSTS_FW_IS_RUNNING = 7,82 FWSTS_SENSOR_APP_LOADED = 8,83 FWSTS_SENSOR_APP_RUNNING = 1584};85 86#define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)87 88irqreturn_t ish_irq_handler(int irq, void *dev_id);89struct ishtp_device *ish_dev_init(struct pci_dev *pdev);90int ish_hw_start(struct ishtp_device *dev);91void ish_device_disable(struct ishtp_device *dev);92int ish_disable_dma(struct ishtp_device *dev);93void ish_set_host_ready(struct ishtp_device *dev);94 95#endif /* _ISHTP_HW_ISH_H_ */96