798 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Intel MAX 10 BMC HWMON Driver4 *5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.6 *7 */8#include <linux/device.h>9#include <linux/hwmon.h>10#include <linux/mfd/intel-m10-bmc.h>11#include <linux/module.h>12#include <linux/mod_devicetable.h>13#include <linux/platform_device.h>14 15struct m10bmc_sdata {16 unsigned int reg_input;17 unsigned int reg_max;18 unsigned int reg_crit;19 unsigned int reg_hyst;20 unsigned int reg_min;21 unsigned int multiplier;22 const char *label;23};24 25struct m10bmc_hwmon_board_data {26 const struct m10bmc_sdata *tables[hwmon_max];27 const struct hwmon_channel_info * const *hinfo;28};29 30struct m10bmc_hwmon {31 struct device *dev;32 struct hwmon_chip_info chip;33 char *hw_name;34 struct intel_m10bmc *m10bmc;35 const struct m10bmc_hwmon_board_data *bdata;36};37 38static const struct m10bmc_sdata n3000bmc_temp_tbl[] = {39 { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Temperature" },40 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Die Temperature" },41 { 0x11c, 0x124, 0x120, 0x0, 0x0, 500, "QSFP0 Temperature" },42 { 0x12c, 0x134, 0x130, 0x0, 0x0, 500, "QSFP1 Temperature" },43 { 0x168, 0x0, 0x0, 0x0, 0x0, 500, "Retimer A Temperature" },44 { 0x16c, 0x0, 0x0, 0x0, 0x0, 500, "Retimer A SerDes Temperature" },45 { 0x170, 0x0, 0x0, 0x0, 0x0, 500, "Retimer B Temperature" },46 { 0x174, 0x0, 0x0, 0x0, 0x0, 500, "Retimer B SerDes Temperature" },47};48 49static const struct m10bmc_sdata n3000bmc_in_tbl[] = {50 { 0x128, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },51 { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },52 { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },53 { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "12V Backplane Voltage" },54 { 0x14c, 0x0, 0x0, 0x0, 0x0, 1, "1.2V Voltage" },55 { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "12V AUX Voltage" },56 { 0x158, 0x0, 0x0, 0x0, 0x0, 1, "1.8V Voltage" },57 { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "3.3V Voltage" },58};59 60static const struct m10bmc_sdata n3000bmc_curr_tbl[] = {61 { 0x140, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },62 { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "12V Backplane Current" },63 { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "12V AUX Current" },64};65 66static const struct m10bmc_sdata n3000bmc_power_tbl[] = {67 { 0x160, 0x0, 0x0, 0x0, 0x0, 1000, "Board Power" },68};69 70static const struct hwmon_channel_info * const n3000bmc_hinfo[] = {71 HWMON_CHANNEL_INFO(temp,72 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |73 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,74 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |75 HWMON_T_LABEL,76 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |77 HWMON_T_LABEL,78 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |79 HWMON_T_LABEL,80 HWMON_T_INPUT | HWMON_T_LABEL,81 HWMON_T_INPUT | HWMON_T_LABEL,82 HWMON_T_INPUT | HWMON_T_LABEL,83 HWMON_T_INPUT | HWMON_T_LABEL),84 HWMON_CHANNEL_INFO(in,85 HWMON_I_INPUT | HWMON_I_LABEL,86 HWMON_I_INPUT | HWMON_I_LABEL,87 HWMON_I_INPUT | HWMON_I_LABEL,88 HWMON_I_INPUT | HWMON_I_LABEL,89 HWMON_I_INPUT | HWMON_I_LABEL,90 HWMON_I_INPUT | HWMON_I_LABEL,91 HWMON_I_INPUT | HWMON_I_LABEL,92 HWMON_I_INPUT | HWMON_I_LABEL),93 HWMON_CHANNEL_INFO(curr,94 HWMON_C_INPUT | HWMON_C_LABEL,95 HWMON_C_INPUT | HWMON_C_LABEL,96 HWMON_C_INPUT | HWMON_C_LABEL),97 HWMON_CHANNEL_INFO(power,98 HWMON_P_INPUT | HWMON_P_LABEL),99 NULL100};101 102static const struct m10bmc_sdata d5005bmc_temp_tbl[] = {103 { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Inlet Air Temperature" },104 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Core Temperature" },105 { 0x11c, 0x120, 0x124, 0x128, 0x0, 500, "Board Exhaust Air Temperature" },106 { 0x12c, 0x130, 0x134, 0x0, 0x0, 500, "FPGA Transceiver Temperature" },107 { 0x138, 0x13c, 0x140, 0x144, 0x0, 500, "RDIMM0 Temperature" },108 { 0x148, 0x14c, 0x150, 0x154, 0x0, 500, "RDIMM1 Temperature" },109 { 0x158, 0x15c, 0x160, 0x164, 0x0, 500, "RDIMM2 Temperature" },110 { 0x168, 0x16c, 0x170, 0x174, 0x0, 500, "RDIMM3 Temperature" },111 { 0x178, 0x17c, 0x180, 0x0, 0x0, 500, "QSFP0 Temperature" },112 { 0x188, 0x18c, 0x190, 0x0, 0x0, 500, "QSFP1 Temperature" },113 { 0x1a0, 0x1a4, 0x1a8, 0x0, 0x0, 500, "3.3v Temperature" },114 { 0x1bc, 0x1c0, 0x1c4, 0x0, 0x0, 500, "VCCERAM Temperature" },115 { 0x1d8, 0x1dc, 0x1e0, 0x0, 0x0, 500, "VCCR Temperature" },116 { 0x1f4, 0x1f8, 0x1fc, 0x0, 0x0, 500, "VCCT Temperature" },117 { 0x210, 0x214, 0x218, 0x0, 0x0, 500, "1.8v Temperature" },118 { 0x22c, 0x230, 0x234, 0x0, 0x0, 500, "12v Backplane Temperature" },119 { 0x248, 0x24c, 0x250, 0x0, 0x0, 500, "12v AUX Temperature" },120};121 122static const struct m10bmc_sdata d5005bmc_in_tbl[] = {123 { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QSFP0 Supply Voltage" },124 { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "QSFP1 Supply Voltage" },125 { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" },126 { 0x1ac, 0x1b0, 0x1b4, 0x0, 0x0, 1, "3.3v Voltage" },127 { 0x1c8, 0x1cc, 0x1d0, 0x0, 0x0, 1, "VCCERAM Voltage" },128 { 0x1e4, 0x1e8, 0x1ec, 0x0, 0x0, 1, "VCCR Voltage" },129 { 0x200, 0x204, 0x208, 0x0, 0x0, 1, "VCCT Voltage" },130 { 0x21c, 0x220, 0x224, 0x0, 0x0, 1, "1.8v Voltage" },131 { 0x238, 0x0, 0x0, 0x0, 0x23c, 1, "12v Backplane Voltage" },132 { 0x254, 0x0, 0x0, 0x0, 0x258, 1, "12v AUX Voltage" },133};134 135static const struct m10bmc_sdata d5005bmc_curr_tbl[] = {136 { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" },137 { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1, "3.3v Current" },138 { 0x1d4, 0x0, 0x0, 0x0, 0x0, 1, "VCCERAM Current" },139 { 0x1f0, 0x0, 0x0, 0x0, 0x0, 1, "VCCR Current" },140 { 0x20c, 0x0, 0x0, 0x0, 0x0, 1, "VCCT Current" },141 { 0x228, 0x0, 0x0, 0x0, 0x0, 1, "1.8v Current" },142 { 0x240, 0x244, 0x0, 0x0, 0x0, 1, "12v Backplane Current" },143 { 0x25c, 0x260, 0x0, 0x0, 0x0, 1, "12v AUX Current" },144};145 146static const struct m10bmc_hwmon_board_data n3000bmc_hwmon_bdata = {147 .tables = {148 [hwmon_temp] = n3000bmc_temp_tbl,149 [hwmon_in] = n3000bmc_in_tbl,150 [hwmon_curr] = n3000bmc_curr_tbl,151 [hwmon_power] = n3000bmc_power_tbl,152 },153 154 .hinfo = n3000bmc_hinfo,155};156 157static const struct hwmon_channel_info * const d5005bmc_hinfo[] = {158 HWMON_CHANNEL_INFO(temp,159 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |160 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,161 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |162 HWMON_T_LABEL,163 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |164 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,165 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |166 HWMON_T_LABEL,167 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |168 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,169 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |170 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,171 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |172 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,173 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |174 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,175 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |176 HWMON_T_LABEL,177 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |178 HWMON_T_LABEL,179 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |180 HWMON_T_LABEL,181 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |182 HWMON_T_LABEL,183 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |184 HWMON_T_LABEL,185 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |186 HWMON_T_LABEL,187 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |188 HWMON_T_LABEL,189 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |190 HWMON_T_LABEL,191 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |192 HWMON_T_LABEL),193 HWMON_CHANNEL_INFO(in,194 HWMON_I_INPUT | HWMON_I_LABEL,195 HWMON_I_INPUT | HWMON_I_LABEL,196 HWMON_I_INPUT | HWMON_I_LABEL,197 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |198 HWMON_I_LABEL,199 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |200 HWMON_I_LABEL,201 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |202 HWMON_I_LABEL,203 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |204 HWMON_I_LABEL,205 HWMON_I_INPUT | HWMON_I_MAX | HWMON_I_CRIT |206 HWMON_I_LABEL,207 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL,208 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_LABEL),209 HWMON_CHANNEL_INFO(curr,210 HWMON_C_INPUT | HWMON_C_LABEL,211 HWMON_C_INPUT | HWMON_C_LABEL,212 HWMON_C_INPUT | HWMON_C_LABEL,213 HWMON_C_INPUT | HWMON_C_LABEL,214 HWMON_C_INPUT | HWMON_C_LABEL,215 HWMON_C_INPUT | HWMON_C_LABEL,216 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL,217 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_LABEL),218 NULL219};220 221static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {222 .tables = {223 [hwmon_temp] = d5005bmc_temp_tbl,224 [hwmon_in] = d5005bmc_in_tbl,225 [hwmon_curr] = d5005bmc_curr_tbl,226 },227 228 .hinfo = d5005bmc_hinfo,229};230 231static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {232 { 0x100, 0x0, 0x104, 0x0, 0x0, 1000, "Board Local Temperature" },233 { 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" },234 { 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" },235 { 0x118, 0x0, 0x0, 0x0, 0x0, 1000, "Card Top Temperature" },236 { 0x11c, 0x0, 0x0, 0x0, 0x0, 1000, "Card Bottom Temperature" },237 { 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" },238 { 0x134, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 5V Temperature" },239 { 0x140, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.9V Temperature" },240 { 0x14c, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 0.85V Temperature" },241 { 0x158, 0x0, 0x0, 0x0, 0x0, 1000, "AUX 12V Temperature" },242 { 0x164, 0x0, 0x0, 0x0, 0x0, 1000, "Backplane 12V Temperature" },243 { 0x1a8, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-1 Temperature" },244 { 0x1ac, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-2 Temperature" },245 { 0x1b0, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-3 Temperature" },246 { 0x1b4, 0x0, 0x0, 0x0, 0x0, 1000, "QSFP28-4 Temperature" },247 { 0x1b8, 0x0, 0x0, 0x0, 0x0, 1000, "CVL1 Internal Temperature" },248 { 0x1bc, 0x0, 0x0, 0x0, 0x0, 1000, "CVL2 Internal Temperature" },249};250 251static const struct m10bmc_sdata n5010bmc_in_tbl[] = {252 { 0x120, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Voltage" },253 { 0x12c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Voltage" },254 { 0x138, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Voltage" },255 { 0x144, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Voltage" },256 { 0x150, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Voltage" },257 { 0x15c, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Voltage" },258 { 0x16c, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Voltage" },259 { 0x17c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Voltage" },260 { 0x184, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Voltage" },261 { 0x18c, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Voltage" },262 { 0x194, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Voltage" },263 { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Voltage" },264 { 0x1a4, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Voltage" },265};266 267static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {268 { 0x124, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.2V Current" },269 { 0x130, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 5V Current" },270 { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.9V Current" },271 { 0x148, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 0.85V Current" },272 { 0x154, 0x0, 0x0, 0x0, 0x0, 1, "AUX 12V Current" },273 { 0x160, 0x0, 0x0, 0x0, 0x0, 1, "Backplane 12V Current" },274 { 0x168, 0x0, 0x0, 0x0, 0x0, 1, "DDR4 1.2V Current" },275 { 0x178, 0x0, 0x0, 0x0, 0x0, 1, "FPGA 1.8V Current" },276 { 0x180, 0x0, 0x0, 0x0, 0x0, 1, "QDR 1.3V Current" },277 { 0x188, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 0.8V Current" },278 { 0x190, 0x0, 0x0, 0x0, 0x0, 1, "CVL1 1.05V Current" },279 { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 1.05V Current" },280 { 0x1a0, 0x0, 0x0, 0x0, 0x0, 1, "CVL2 0.8V Current" },281};282 283static const struct hwmon_channel_info * const n5010bmc_hinfo[] = {284 HWMON_CHANNEL_INFO(temp,285 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,286 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,287 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_LABEL,288 HWMON_T_INPUT | HWMON_T_LABEL,289 HWMON_T_INPUT | HWMON_T_LABEL,290 HWMON_T_INPUT | HWMON_T_LABEL,291 HWMON_T_INPUT | HWMON_T_LABEL,292 HWMON_T_INPUT | HWMON_T_LABEL,293 HWMON_T_INPUT | HWMON_T_LABEL,294 HWMON_T_INPUT | HWMON_T_LABEL,295 HWMON_T_INPUT | HWMON_T_LABEL,296 HWMON_T_INPUT | HWMON_T_LABEL,297 HWMON_T_INPUT | HWMON_T_LABEL,298 HWMON_T_INPUT | HWMON_T_LABEL,299 HWMON_T_INPUT | HWMON_T_LABEL,300 HWMON_T_INPUT | HWMON_T_LABEL,301 HWMON_T_INPUT | HWMON_T_LABEL),302 HWMON_CHANNEL_INFO(in,303 HWMON_I_INPUT | HWMON_I_LABEL,304 HWMON_I_INPUT | HWMON_I_LABEL,305 HWMON_I_INPUT | HWMON_I_LABEL,306 HWMON_I_INPUT | HWMON_I_LABEL,307 HWMON_I_INPUT | HWMON_I_LABEL,308 HWMON_I_INPUT | HWMON_I_LABEL,309 HWMON_I_INPUT | HWMON_I_LABEL,310 HWMON_I_INPUT | HWMON_I_LABEL,311 HWMON_I_INPUT | HWMON_I_LABEL,312 HWMON_I_INPUT | HWMON_I_LABEL,313 HWMON_I_INPUT | HWMON_I_LABEL,314 HWMON_I_INPUT | HWMON_I_LABEL,315 HWMON_I_INPUT | HWMON_I_LABEL),316 HWMON_CHANNEL_INFO(curr,317 HWMON_C_INPUT | HWMON_C_LABEL,318 HWMON_C_INPUT | HWMON_C_LABEL,319 HWMON_C_INPUT | HWMON_C_LABEL,320 HWMON_C_INPUT | HWMON_C_LABEL,321 HWMON_C_INPUT | HWMON_C_LABEL,322 HWMON_C_INPUT | HWMON_C_LABEL,323 HWMON_C_INPUT | HWMON_C_LABEL,324 HWMON_C_INPUT | HWMON_C_LABEL,325 HWMON_C_INPUT | HWMON_C_LABEL,326 HWMON_C_INPUT | HWMON_C_LABEL,327 HWMON_C_INPUT | HWMON_C_LABEL,328 HWMON_C_INPUT | HWMON_C_LABEL,329 HWMON_C_INPUT | HWMON_C_LABEL),330 NULL331};332 333static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {334 .tables = {335 [hwmon_temp] = n5010bmc_temp_tbl,336 [hwmon_in] = n5010bmc_in_tbl,337 [hwmon_curr] = n5010bmc_curr_tbl,338 },339 340 .hinfo = n5010bmc_hinfo,341};342 343static const struct m10bmc_sdata n6000bmc_temp_tbl[] = {344 { 0x444, 0x448, 0x44c, 0x0, 0x0, 500, "FPGA E-TILE Temperature #1" },345 { 0x450, 0x454, 0x458, 0x0, 0x0, 500, "FPGA E-TILE Temperature #2" },346 { 0x45c, 0x460, 0x464, 0x0, 0x0, 500, "FPGA E-TILE Temperature #3" },347 { 0x468, 0x46c, 0x470, 0x0, 0x0, 500, "FPGA E-TILE Temperature #4" },348 { 0x474, 0x478, 0x47c, 0x0, 0x0, 500, "FPGA P-TILE Temperature" },349 { 0x484, 0x488, 0x48c, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #1" },350 { 0x490, 0x494, 0x498, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #2" },351 { 0x49c, 0x4a0, 0x4a4, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #3" },352 { 0x4a8, 0x4ac, 0x4b0, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #4" },353 { 0x4b4, 0x4b8, 0x4bc, 0x0, 0x0, 500, "FPGA FABRIC Digital Temperature #5" },354 { 0x4c0, 0x4c4, 0x4c8, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #1" },355 { 0x4cc, 0x4d0, 0x4d4, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #2" },356 { 0x4d8, 0x4dc, 0x4e0, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #3" },357 { 0x4e4, 0x4e8, 0x4ec, 0x0, 0x0, 500, "FPGA FABRIC Remote Digital Temperature #4" },358 { 0x4f0, 0x4f4, 0x4f8, 0x52c, 0x0, 500, "Board Top Near FPGA Temperature" },359 { 0x4fc, 0x500, 0x504, 0x52c, 0x0, 500, "Board Bottom Near CVL Temperature" },360 { 0x508, 0x50c, 0x510, 0x52c, 0x0, 500, "Board Top East Near VRs Temperature" },361 { 0x514, 0x518, 0x51c, 0x52c, 0x0, 500, "CVL Die Temperature" },362 { 0x520, 0x524, 0x528, 0x52c, 0x0, 500, "Board Rear Side Temperature" },363 { 0x530, 0x534, 0x538, 0x52c, 0x0, 500, "Board Front Side Temperature" },364 { 0x53c, 0x540, 0x544, 0x0, 0x0, 500, "QSFP1 Case Temperature" },365 { 0x548, 0x54c, 0x550, 0x0, 0x0, 500, "QSFP2 Case Temperature" },366 { 0x554, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 0 VR Temperature" },367 { 0x560, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 1 VR Temperature" },368 { 0x56c, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage Phase 2 VR Temperature" },369 { 0x578, 0x0, 0x0, 0x0, 0x0, 500, "FPGA Core Voltage VR Controller Temperature" },370 { 0x584, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCCH VR Temperature" },371 { 0x590, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCC_1V2 VR Temperature" },372 { 0x59c, 0x0, 0x0, 0x0, 0x0, 500, "FPGA VCCH, VCC_1V2 VR Controller Temperature" },373 { 0x5a8, 0x0, 0x0, 0x0, 0x0, 500, "3V3 VR Temperature" },374 { 0x5b4, 0x0, 0x0, 0x0, 0x0, 500, "CVL Core Voltage VR Temperature" },375 { 0x5c4, 0x5c8, 0x5cc, 0x5c0, 0x0, 500, "FPGA P-Tile Temperature [Remote]" },376 { 0x5d0, 0x5d4, 0x5d8, 0x5c0, 0x0, 500, "FPGA E-Tile Temperature [Remote]" },377 { 0x5dc, 0x5e0, 0x5e4, 0x5c0, 0x0, 500, "FPGA SDM Temperature [Remote]" },378 { 0x5e8, 0x5ec, 0x5f0, 0x5c0, 0x0, 500, "FPGA Corner Temperature [Remote]" },379};380 381static const struct m10bmc_sdata n6000bmc_in_tbl[] = {382 { 0x5f4, 0x0, 0x0, 0x0, 0x0, 1, "Inlet 12V PCIe Rail Voltage" },383 { 0x60c, 0x0, 0x0, 0x0, 0x0, 1, "Inlet 12V Aux Rail Voltage" },384 { 0x624, 0x0, 0x0, 0x0, 0x0, 1, "Inlet 3V3 PCIe Rail Voltage" },385 { 0x63c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage Rail Voltage" },386 { 0x644, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH Rail Voltage" },387 { 0x64c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCC_1V2 Rail Voltage" },388 { 0x654, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH_GXER_1V1, VCCA_1V8 Voltage" },389 { 0x664, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCIO_1V2 Voltage" },390 { 0x674, 0x0, 0x0, 0x0, 0x0, 1, "CVL Non Core Rails Inlet Voltage" },391 { 0x684, 0x0, 0x0, 0x0, 0x0, 1, "MAX10 & Board CLK PWR 3V3 Inlet Voltage" },392 { 0x694, 0x0, 0x0, 0x0, 0x0, 1, "CVL Core Voltage Rail Voltage" },393 { 0x6ac, 0x0, 0x0, 0x0, 0x0, 1, "Board 3V3 VR Voltage" },394 { 0x6b4, 0x0, 0x0, 0x0, 0x0, 1, "QSFP 3V3 Rail Voltage" },395 { 0x6c4, 0x0, 0x0, 0x0, 0x0, 1, "QSFP (Primary) Supply Rail Voltage" },396 { 0x6c8, 0x0, 0x0, 0x0, 0x0, 1, "QSFP (Secondary) Supply Rail Voltage" },397 { 0x6cc, 0x0, 0x0, 0x0, 0x0, 1, "VCCCLK_GXER_2V5 Voltage" },398 { 0x6d0, 0x0, 0x0, 0x0, 0x0, 1, "AVDDH_1V1_CVL Voltage" },399 { 0x6d4, 0x0, 0x0, 0x0, 0x0, 1, "VDDH_1V8_CVL Voltage" },400 { 0x6d8, 0x0, 0x0, 0x0, 0x0, 1, "VCCA_PLL Voltage" },401 { 0x6e0, 0x0, 0x0, 0x0, 0x0, 1, "VCCRT_GXER_0V9 Voltage" },402 { 0x6e8, 0x0, 0x0, 0x0, 0x0, 1, "VCCRT_GXPL_0V9 Voltage" },403 { 0x6f0, 0x0, 0x0, 0x0, 0x0, 1, "VCCH_GXPL_1V8 Voltage" },404 { 0x6f4, 0x0, 0x0, 0x0, 0x0, 1, "VCCPT_1V8 Voltage" },405 { 0x6fc, 0x0, 0x0, 0x0, 0x0, 1, "VCC_3V3_M10 Voltage" },406 { 0x700, 0x0, 0x0, 0x0, 0x0, 1, "VCC_1V8_M10 Voltage" },407 { 0x704, 0x0, 0x0, 0x0, 0x0, 1, "VCC_1V2_EMIF1_2_3 Voltage" },408 { 0x70c, 0x0, 0x0, 0x0, 0x0, 1, "VCC_1V2_EMIF4_5 Voltage" },409 { 0x714, 0x0, 0x0, 0x0, 0x0, 1, "VCCA_1V8 Voltage" },410 { 0x718, 0x0, 0x0, 0x0, 0x0, 1, "VCCH_GXER_1V1 Voltage" },411 { 0x71c, 0x0, 0x0, 0x0, 0x0, 1, "AVDD_ETH_0V9_CVL Voltage" },412 { 0x720, 0x0, 0x0, 0x0, 0x0, 1, "AVDD_PCIE_0V9_CVL Voltage" },413};414 415static const struct m10bmc_sdata n6000bmc_curr_tbl[] = {416 { 0x600, 0x604, 0x608, 0x0, 0x0, 1, "Inlet 12V PCIe Rail Current" },417 { 0x618, 0x61c, 0x620, 0x0, 0x0, 1, "Inlet 12V Aux Rail Current" },418 { 0x630, 0x634, 0x638, 0x0, 0x0, 1, "Inlet 3V3 PCIe Rail Current" },419 { 0x640, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage Rail Current" },420 { 0x648, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCCH Rail Current" },421 { 0x650, 0x0, 0x0, 0x0, 0x0, 1, "FPGA VCC_1V2 Rail Current" },422 { 0x658, 0x65c, 0x660, 0x0, 0x0, 1, "FPGA VCCH_GXER_1V1, VCCA_1V8 Current" },423 { 0x668, 0x66c, 0x670, 0x0, 0x0, 1, "FPGA VCCIO_1V2 Current" },424 { 0x678, 0x67c, 0x680, 0x0, 0x0, 1, "CVL Non Core Rails Inlet Current" },425 { 0x688, 0x68c, 0x690, 0x0, 0x0, 1, "MAX10 & Board CLK PWR 3V3 Inlet Current" },426 { 0x698, 0x0, 0x0, 0x0, 0x0, 1, "CVL Core Voltage Rail Current" },427 { 0x6b0, 0x0, 0x0, 0x0, 0x0, 1, "Board 3V3 VR Current" },428 { 0x6b8, 0x6bc, 0x6c0, 0x0, 0x0, 1, "QSFP 3V3 Rail Current" },429};430 431static const struct m10bmc_sdata n6000bmc_power_tbl[] = {432 { 0x724, 0x0, 0x0, 0x0, 0x0, 1000, "Board Power" },433};434 435static const struct hwmon_channel_info * const n6000bmc_hinfo[] = {436 HWMON_CHANNEL_INFO(temp,437 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |438 HWMON_T_LABEL,439 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |440 HWMON_T_LABEL,441 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |442 HWMON_T_LABEL,443 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |444 HWMON_T_LABEL,445 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |446 HWMON_T_LABEL,447 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |448 HWMON_T_LABEL,449 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |450 HWMON_T_LABEL,451 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |452 HWMON_T_LABEL,453 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |454 HWMON_T_LABEL,455 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |456 HWMON_T_LABEL,457 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |458 HWMON_T_LABEL,459 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |460 HWMON_T_LABEL,461 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |462 HWMON_T_LABEL,463 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |464 HWMON_T_LABEL,465 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |466 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,467 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |468 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,469 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |470 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,471 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |472 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,473 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |474 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,475 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |476 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,477 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |478 HWMON_T_LABEL,479 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |480 HWMON_T_LABEL,481 HWMON_T_INPUT | HWMON_T_LABEL,482 HWMON_T_INPUT | HWMON_T_LABEL,483 HWMON_T_INPUT | HWMON_T_LABEL,484 HWMON_T_INPUT | HWMON_T_LABEL,485 HWMON_T_INPUT | HWMON_T_LABEL,486 HWMON_T_INPUT | HWMON_T_LABEL,487 HWMON_T_INPUT | HWMON_T_LABEL,488 HWMON_T_INPUT | HWMON_T_LABEL,489 HWMON_T_INPUT | HWMON_T_LABEL,490 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |491 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,492 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |493 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,494 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |495 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL,496 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST |497 HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_LABEL),498 HWMON_CHANNEL_INFO(in,499 HWMON_I_INPUT | HWMON_I_LABEL,500 HWMON_I_INPUT | HWMON_I_LABEL,501 HWMON_I_INPUT | HWMON_I_LABEL,502 HWMON_I_INPUT | HWMON_I_LABEL,503 HWMON_I_INPUT | HWMON_I_LABEL,504 HWMON_I_INPUT | HWMON_I_LABEL,505 HWMON_I_INPUT | HWMON_I_LABEL,506 HWMON_I_INPUT | HWMON_I_LABEL,507 HWMON_I_INPUT | HWMON_I_LABEL,508 HWMON_I_INPUT | HWMON_I_LABEL,509 HWMON_I_INPUT | HWMON_I_LABEL,510 HWMON_I_INPUT | HWMON_I_LABEL,511 HWMON_I_INPUT | HWMON_I_LABEL,512 HWMON_I_INPUT | HWMON_I_LABEL,513 HWMON_I_INPUT | HWMON_I_LABEL,514 HWMON_I_INPUT | HWMON_I_LABEL,515 HWMON_I_INPUT | HWMON_I_LABEL,516 HWMON_I_INPUT | HWMON_I_LABEL,517 HWMON_I_INPUT | HWMON_I_LABEL,518 HWMON_I_INPUT | HWMON_I_LABEL,519 HWMON_I_INPUT | HWMON_I_LABEL,520 HWMON_I_INPUT | HWMON_I_LABEL,521 HWMON_I_INPUT | HWMON_I_LABEL,522 HWMON_I_INPUT | HWMON_I_LABEL,523 HWMON_I_INPUT | HWMON_I_LABEL,524 HWMON_I_INPUT | HWMON_I_LABEL,525 HWMON_I_INPUT | HWMON_I_LABEL,526 HWMON_I_INPUT | HWMON_I_LABEL,527 HWMON_I_INPUT | HWMON_I_LABEL,528 HWMON_I_INPUT | HWMON_I_LABEL,529 HWMON_I_INPUT | HWMON_I_LABEL),530 HWMON_CHANNEL_INFO(curr,531 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |532 HWMON_C_LABEL,533 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |534 HWMON_C_LABEL,535 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |536 HWMON_C_LABEL,537 HWMON_C_INPUT | HWMON_C_LABEL,538 HWMON_C_INPUT | HWMON_C_LABEL,539 HWMON_C_INPUT | HWMON_C_LABEL,540 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |541 HWMON_C_LABEL,542 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |543 HWMON_C_LABEL,544 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |545 HWMON_C_LABEL,546 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |547 HWMON_C_LABEL,548 HWMON_C_INPUT | HWMON_C_LABEL,549 HWMON_C_INPUT | HWMON_C_LABEL,550 HWMON_C_INPUT | HWMON_C_MAX | HWMON_C_CRIT |551 HWMON_C_LABEL),552 HWMON_CHANNEL_INFO(power,553 HWMON_P_INPUT | HWMON_P_LABEL),554 NULL555};556 557static const struct m10bmc_hwmon_board_data n6000bmc_hwmon_bdata = {558 .tables = {559 [hwmon_temp] = n6000bmc_temp_tbl,560 [hwmon_in] = n6000bmc_in_tbl,561 [hwmon_curr] = n6000bmc_curr_tbl,562 [hwmon_power] = n6000bmc_power_tbl,563 },564 565 .hinfo = n6000bmc_hinfo,566};567 568static umode_t569m10bmc_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,570 u32 attr, int channel)571{572 return 0444;573}574 575static const struct m10bmc_sdata *576find_sensor_data(struct m10bmc_hwmon *hw, enum hwmon_sensor_types type,577 int channel)578{579 const struct m10bmc_sdata *tbl;580 581 tbl = hw->bdata->tables[type];582 if (!tbl)583 return ERR_PTR(-EOPNOTSUPP);584 585 return &tbl[channel];586}587 588static int do_sensor_read(struct m10bmc_hwmon *hw,589 const struct m10bmc_sdata *data,590 unsigned int regoff, long *val)591{592 unsigned int regval;593 int ret;594 595 ret = m10bmc_sys_read(hw->m10bmc, regoff, ®val);596 if (ret)597 return ret;598 599 /*600 * BMC Firmware will return 0xdeadbeef if the sensor value is invalid601 * at that time. This usually happens on sensor channels which connect602 * to external pluggable modules, e.g. QSFP temperature and voltage.603 * When the QSFP is unplugged from cage, driver will get 0xdeadbeef604 * from their registers.605 */606 if (regval == 0xdeadbeef)607 return -ENODATA;608 609 *val = regval * data->multiplier;610 611 return 0;612}613 614static int m10bmc_hwmon_read(struct device *dev, enum hwmon_sensor_types type,615 u32 attr, int channel, long *val)616{617 struct m10bmc_hwmon *hw = dev_get_drvdata(dev);618 unsigned int reg = 0, reg_hyst = 0;619 const struct m10bmc_sdata *data;620 long hyst, value;621 int ret;622 623 data = find_sensor_data(hw, type, channel);624 if (IS_ERR(data))625 return PTR_ERR(data);626 627 switch (type) {628 case hwmon_temp:629 switch (attr) {630 case hwmon_temp_input:631 reg = data->reg_input;632 break;633 case hwmon_temp_max_hyst:634 reg_hyst = data->reg_hyst;635 fallthrough;636 case hwmon_temp_max:637 reg = data->reg_max;638 break;639 case hwmon_temp_crit_hyst:640 reg_hyst = data->reg_hyst;641 fallthrough;642 case hwmon_temp_crit:643 reg = data->reg_crit;644 break;645 default:646 return -EOPNOTSUPP;647 }648 break;649 case hwmon_in:650 switch (attr) {651 case hwmon_in_input:652 reg = data->reg_input;653 break;654 case hwmon_in_max:655 reg = data->reg_max;656 break;657 case hwmon_in_crit:658 reg = data->reg_crit;659 break;660 case hwmon_in_min:661 reg = data->reg_min;662 break;663 default:664 return -EOPNOTSUPP;665 }666 break;667 case hwmon_curr:668 switch (attr) {669 case hwmon_curr_input:670 reg = data->reg_input;671 break;672 case hwmon_curr_max:673 reg = data->reg_max;674 break;675 case hwmon_curr_crit:676 reg = data->reg_crit;677 break;678 default:679 return -EOPNOTSUPP;680 }681 break;682 case hwmon_power:683 switch (attr) {684 case hwmon_power_input:685 reg = data->reg_input;686 break;687 default:688 return -EOPNOTSUPP;689 }690 break;691 default:692 return -EOPNOTSUPP;693 }694 695 if (!reg)696 return -EOPNOTSUPP;697 698 ret = do_sensor_read(hw, data, reg, &value);699 if (ret)700 return ret;701 702 if (reg_hyst) {703 ret = do_sensor_read(hw, data, reg_hyst, &hyst);704 if (ret)705 return ret;706 707 value -= hyst;708 }709 710 *val = value;711 712 return 0;713}714 715static int m10bmc_hwmon_read_string(struct device *dev,716 enum hwmon_sensor_types type,717 u32 attr, int channel, const char **str)718{719 struct m10bmc_hwmon *hw = dev_get_drvdata(dev);720 const struct m10bmc_sdata *data;721 722 data = find_sensor_data(hw, type, channel);723 if (IS_ERR(data))724 return PTR_ERR(data);725 726 *str = data->label;727 728 return 0;729}730 731static const struct hwmon_ops m10bmc_hwmon_ops = {732 .is_visible = m10bmc_hwmon_is_visible,733 .read = m10bmc_hwmon_read,734 .read_string = m10bmc_hwmon_read_string,735};736 737static int m10bmc_hwmon_probe(struct platform_device *pdev)738{739 const struct platform_device_id *id = platform_get_device_id(pdev);740 struct intel_m10bmc *m10bmc = dev_get_drvdata(pdev->dev.parent);741 struct device *hwmon_dev, *dev = &pdev->dev;742 struct m10bmc_hwmon *hw;743 744 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);745 if (!hw)746 return -ENOMEM;747 748 hw->dev = dev;749 hw->m10bmc = m10bmc;750 hw->bdata = (const struct m10bmc_hwmon_board_data *)id->driver_data;751 752 hw->chip.info = hw->bdata->hinfo;753 hw->chip.ops = &m10bmc_hwmon_ops;754 755 hw->hw_name = devm_hwmon_sanitize_name(dev, id->name);756 if (IS_ERR(hw->hw_name))757 return PTR_ERR(hw->hw_name);758 759 hwmon_dev = devm_hwmon_device_register_with_info(dev, hw->hw_name,760 hw, &hw->chip, NULL);761 return PTR_ERR_OR_ZERO(hwmon_dev);762}763 764static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {765 {766 .name = "n3000bmc-hwmon",767 .driver_data = (unsigned long)&n3000bmc_hwmon_bdata,768 },769 {770 .name = "d5005bmc-hwmon",771 .driver_data = (unsigned long)&d5005bmc_hwmon_bdata,772 },773 {774 .name = "n5010bmc-hwmon",775 .driver_data = (unsigned long)&n5010bmc_hwmon_bdata,776 },777 {778 .name = "n6000bmc-hwmon",779 .driver_data = (unsigned long)&n6000bmc_hwmon_bdata,780 },781 { }782};783 784static struct platform_driver intel_m10bmc_hwmon_driver = {785 .probe = m10bmc_hwmon_probe,786 .driver = {787 .name = "intel-m10-bmc-hwmon",788 },789 .id_table = intel_m10bmc_hwmon_ids,790};791module_platform_driver(intel_m10bmc_hwmon_driver);792 793MODULE_DEVICE_TABLE(platform, intel_m10bmc_hwmon_ids);794MODULE_AUTHOR("Intel Corporation");795MODULE_DESCRIPTION("Intel MAX 10 BMC hardware monitor");796MODULE_LICENSE("GPL");797MODULE_IMPORT_NS(INTEL_M10_BMC_CORE);798