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1// SPDX-License-Identifier: GPL-2.02// Copyright (c) 2014-2018 Nuvoton Technology corporation.3 4#include <linux/clk.h>5#include <linux/device.h>6#include <linux/hwmon.h>7#include <linux/hwmon-sysfs.h>8#include <linux/interrupt.h>9#include <linux/kernel.h>10#include <linux/module.h>11#include <linux/of_address.h>12#include <linux/of_irq.h>13#include <linux/platform_device.h>14#include <linux/spinlock.h>15#include <linux/sysfs.h>16#include <linux/thermal.h>17 18/* NPCM7XX PWM registers */19#define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L))20 21#define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00)22#define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04)23#define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08)24#define NPCM7XX_PWM_REG_CNRx(base, n, ch) \25 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))26#define NPCM7XX_PWM_REG_CMRx(base, n, ch) \27 (NPCM7XX_PWM_REG_BASE(base, n) + 0x10 + (12 * (ch)))28#define NPCM7XX_PWM_REG_PDRx(base, n, ch) \29 (NPCM7XX_PWM_REG_BASE(base, n) + 0x14 + (12 * (ch)))30#define NPCM7XX_PWM_REG_PIER(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x3C)31#define NPCM7XX_PWM_REG_PIIR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x40)32 33#define NPCM7XX_PWM_CTRL_CH0_MODE_BIT BIT(3)34#define NPCM7XX_PWM_CTRL_CH1_MODE_BIT BIT(11)35#define NPCM7XX_PWM_CTRL_CH2_MODE_BIT BIT(15)36#define NPCM7XX_PWM_CTRL_CH3_MODE_BIT BIT(19)37 38#define NPCM7XX_PWM_CTRL_CH0_INV_BIT BIT(2)39#define NPCM7XX_PWM_CTRL_CH1_INV_BIT BIT(10)40#define NPCM7XX_PWM_CTRL_CH2_INV_BIT BIT(14)41#define NPCM7XX_PWM_CTRL_CH3_INV_BIT BIT(18)42 43#define NPCM7XX_PWM_CTRL_CH0_EN_BIT BIT(0)44#define NPCM7XX_PWM_CTRL_CH1_EN_BIT BIT(8)45#define NPCM7XX_PWM_CTRL_CH2_EN_BIT BIT(12)46#define NPCM7XX_PWM_CTRL_CH3_EN_BIT BIT(16)47 48/* Define the maximum PWM channel number */49#define NPCM7XX_PWM_MAX_CHN_NUM 1250#define NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE 451#define NPCM7XX_PWM_MAX_MODULES 352 53/* Define the Counter Register, value = 100 for match 100% */54#define NPCM7XX_PWM_COUNTER_DEFAULT_NUM 25555#define NPCM7XX_PWM_CMR_DEFAULT_NUM 25556#define NPCM7XX_PWM_CMR_MAX 25557 58/* default all PWM channels PRESCALE2 = 1 */59#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 0x460#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 0x4061#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 0x40062#define NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3 0x400063 64#define PWM_OUTPUT_FREQ_25KHZ 2500065#define PWN_CNT_DEFAULT 25666#define MIN_PRESCALE1 267#define NPCM7XX_PWM_PRESCALE_SHIFT_CH01 868 69#define NPCM7XX_PWM_PRESCALE2_DEFAULT (NPCM7XX_PWM_PRESCALE2_DEFAULT_CH0 | \70 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH1 | \71 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH2 | \72 NPCM7XX_PWM_PRESCALE2_DEFAULT_CH3)73 74#define NPCM7XX_PWM_CTRL_MODE_DEFAULT (NPCM7XX_PWM_CTRL_CH0_MODE_BIT | \75 NPCM7XX_PWM_CTRL_CH1_MODE_BIT | \76 NPCM7XX_PWM_CTRL_CH2_MODE_BIT | \77 NPCM7XX_PWM_CTRL_CH3_MODE_BIT)78 79/* NPCM7XX FAN Tacho registers */80#define NPCM7XX_FAN_REG_BASE(base, n) ((base) + ((n) * 0x1000L))81 82#define NPCM7XX_FAN_REG_TCNT1(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x00)83#define NPCM7XX_FAN_REG_TCRA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x02)84#define NPCM7XX_FAN_REG_TCRB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x04)85#define NPCM7XX_FAN_REG_TCNT2(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x06)86#define NPCM7XX_FAN_REG_TPRSC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x08)87#define NPCM7XX_FAN_REG_TCKC(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0A)88#define NPCM7XX_FAN_REG_TMCTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0C)89#define NPCM7XX_FAN_REG_TICTRL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x0E)90#define NPCM7XX_FAN_REG_TICLR(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x10)91#define NPCM7XX_FAN_REG_TIEN(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x12)92#define NPCM7XX_FAN_REG_TCPA(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x14)93#define NPCM7XX_FAN_REG_TCPB(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x16)94#define NPCM7XX_FAN_REG_TCPCFG(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x18)95#define NPCM7XX_FAN_REG_TINASEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1A)96#define NPCM7XX_FAN_REG_TINBSEL(base, n) (NPCM7XX_FAN_REG_BASE(base, n) + 0x1C)97 98#define NPCM7XX_FAN_TCKC_CLKX_NONE 099#define NPCM7XX_FAN_TCKC_CLK1_APB BIT(0)100#define NPCM7XX_FAN_TCKC_CLK2_APB BIT(3)101 102#define NPCM7XX_FAN_TMCTRL_TBEN BIT(6)103#define NPCM7XX_FAN_TMCTRL_TAEN BIT(5)104#define NPCM7XX_FAN_TMCTRL_TBEDG BIT(4)105#define NPCM7XX_FAN_TMCTRL_TAEDG BIT(3)106#define NPCM7XX_FAN_TMCTRL_MODE_5 BIT(2)107 108#define NPCM7XX_FAN_TICLR_CLEAR_ALL GENMASK(5, 0)109#define NPCM7XX_FAN_TICLR_TFCLR BIT(5)110#define NPCM7XX_FAN_TICLR_TECLR BIT(4)111#define NPCM7XX_FAN_TICLR_TDCLR BIT(3)112#define NPCM7XX_FAN_TICLR_TCCLR BIT(2)113#define NPCM7XX_FAN_TICLR_TBCLR BIT(1)114#define NPCM7XX_FAN_TICLR_TACLR BIT(0)115 116#define NPCM7XX_FAN_TIEN_ENABLE_ALL GENMASK(5, 0)117#define NPCM7XX_FAN_TIEN_TFIEN BIT(5)118#define NPCM7XX_FAN_TIEN_TEIEN BIT(4)119#define NPCM7XX_FAN_TIEN_TDIEN BIT(3)120#define NPCM7XX_FAN_TIEN_TCIEN BIT(2)121#define NPCM7XX_FAN_TIEN_TBIEN BIT(1)122#define NPCM7XX_FAN_TIEN_TAIEN BIT(0)123 124#define NPCM7XX_FAN_TICTRL_TFPND BIT(5)125#define NPCM7XX_FAN_TICTRL_TEPND BIT(4)126#define NPCM7XX_FAN_TICTRL_TDPND BIT(3)127#define NPCM7XX_FAN_TICTRL_TCPND BIT(2)128#define NPCM7XX_FAN_TICTRL_TBPND BIT(1)129#define NPCM7XX_FAN_TICTRL_TAPND BIT(0)130 131#define NPCM7XX_FAN_TCPCFG_HIBEN BIT(7)132#define NPCM7XX_FAN_TCPCFG_EQBEN BIT(6)133#define NPCM7XX_FAN_TCPCFG_LOBEN BIT(5)134#define NPCM7XX_FAN_TCPCFG_CPBSEL BIT(4)135#define NPCM7XX_FAN_TCPCFG_HIAEN BIT(3)136#define NPCM7XX_FAN_TCPCFG_EQAEN BIT(2)137#define NPCM7XX_FAN_TCPCFG_LOAEN BIT(1)138#define NPCM7XX_FAN_TCPCFG_CPASEL BIT(0)139 140/* FAN General Definition */141/* Define the maximum FAN channel number */142#define NPCM7XX_FAN_MAX_MODULE 8143#define NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE 2144#define NPCM7XX_FAN_MAX_CHN_NUM 16145 146/*147 * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)148 * Timeout 94ms ~= 0x5000149 * (The minimum FAN speed could to support ~640RPM/pulse 1,150 * 320RPM/pulse 2, ...-- 10.6Hz)151 */152#define NPCM7XX_FAN_TIMEOUT 0x5000153#define NPCM7XX_FAN_TCNT 0xFFFF154#define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)155#define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)156 157#define NPCM7XX_FAN_POLL_TIMER_200MS 200158#define NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION 2159#define NPCM7XX_FAN_TINASEL_FANIN_DEFAULT 0160#define NPCM7XX_FAN_CLK_PRESCALE 255161 162#define NPCM7XX_FAN_CMPA 0163#define NPCM7XX_FAN_CMPB 1164 165/* Obtain the fan number */166#define NPCM7XX_FAN_INPUT(fan, cmp) (((fan) << 1) + (cmp))167 168/* fan sample status */169#define FAN_DISABLE 0xFF170#define FAN_INIT 0x00171#define FAN_PREPARE_TO_GET_FIRST_CAPTURE 0x01172#define FAN_ENOUGH_SAMPLE 0x02173 174struct npcm_hwmon_info {175 u32 pwm_max_channel;176};177 178struct npcm7xx_fan_dev {179 u8 fan_st_flg;180 u8 fan_pls_per_rev;181 u16 fan_cnt;182 u32 fan_cnt_tmp;183};184 185struct npcm7xx_cooling_device {186 char name[THERMAL_NAME_LENGTH];187 struct npcm7xx_pwm_fan_data *data;188 struct thermal_cooling_device *tcdev;189 int pwm_port;190 u8 *cooling_levels;191 u8 max_state;192 u8 cur_state;193};194 195struct npcm7xx_pwm_fan_data {196 void __iomem *pwm_base;197 void __iomem *fan_base;198 int pwm_modules;199 struct clk *pwm_clk;200 struct clk *fan_clk;201 struct mutex pwm_lock[NPCM7XX_PWM_MAX_MODULES];202 spinlock_t fan_lock[NPCM7XX_FAN_MAX_MODULE];203 int fan_irq[NPCM7XX_FAN_MAX_MODULE];204 bool pwm_present[NPCM7XX_PWM_MAX_CHN_NUM];205 bool fan_present[NPCM7XX_FAN_MAX_CHN_NUM];206 u32 input_clk_freq;207 struct timer_list fan_timer;208 struct npcm7xx_fan_dev fan_dev[NPCM7XX_FAN_MAX_CHN_NUM];209 struct npcm7xx_cooling_device *cdev[NPCM7XX_PWM_MAX_CHN_NUM];210 const struct npcm_hwmon_info *info;211 u8 fan_select;212};213 214static int npcm7xx_pwm_config_set(struct npcm7xx_pwm_fan_data *data,215 int channel, u16 val)216{217 u32 pwm_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);218 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);219 u32 tmp_buf, ctrl_en_bit, env_bit;220 221 /*222 * Config PWM Comparator register for setting duty cycle223 */224 mutex_lock(&data->pwm_lock[module]);225 226 /* write new CMR value */227 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch));228 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module));229 230 switch (pwm_ch) {231 case 0:232 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH0_EN_BIT;233 env_bit = NPCM7XX_PWM_CTRL_CH0_INV_BIT;234 break;235 case 1:236 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH1_EN_BIT;237 env_bit = NPCM7XX_PWM_CTRL_CH1_INV_BIT;238 break;239 case 2:240 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH2_EN_BIT;241 env_bit = NPCM7XX_PWM_CTRL_CH2_INV_BIT;242 break;243 case 3:244 ctrl_en_bit = NPCM7XX_PWM_CTRL_CH3_EN_BIT;245 env_bit = NPCM7XX_PWM_CTRL_CH3_INV_BIT;246 break;247 default:248 mutex_unlock(&data->pwm_lock[module]);249 return -ENODEV;250 }251 252 if (val == 0) {253 /* Disable PWM */254 tmp_buf &= ~ctrl_en_bit;255 tmp_buf |= env_bit;256 } else {257 /* Enable PWM */258 tmp_buf |= ctrl_en_bit;259 tmp_buf &= ~env_bit;260 }261 262 iowrite32(tmp_buf, NPCM7XX_PWM_REG_CR(data->pwm_base, module));263 mutex_unlock(&data->pwm_lock[module]);264 265 return 0;266}267 268static inline void npcm7xx_fan_start_capture(struct npcm7xx_pwm_fan_data *data,269 u8 fan, u8 cmp)270{271 u8 fan_id;272 u8 reg_mode;273 u8 reg_int;274 unsigned long flags;275 276 fan_id = NPCM7XX_FAN_INPUT(fan, cmp);277 278 /* to check whether any fan tach is enable */279 if (data->fan_dev[fan_id].fan_st_flg != FAN_DISABLE) {280 /* reset status */281 spin_lock_irqsave(&data->fan_lock[fan], flags);282 283 data->fan_dev[fan_id].fan_st_flg = FAN_INIT;284 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));285 286 /*287 * the interrupt enable bits do not need to be cleared before288 * it sets, the interrupt enable bits are cleared only on reset.289 * the clock unit control register is behaving in the same290 * manner that the interrupt enable register behave.291 */292 if (cmp == NPCM7XX_FAN_CMPA) {293 /* enable interrupt */294 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TAIEN |295 NPCM7XX_FAN_TIEN_TEIEN),296 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));297 298 reg_mode = NPCM7XX_FAN_TCKC_CLK1_APB299 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,300 fan));301 302 /* start to Capture */303 iowrite8(reg_mode, NPCM7XX_FAN_REG_TCKC(data->fan_base,304 fan));305 } else {306 /* enable interrupt */307 iowrite8(reg_int | (NPCM7XX_FAN_TIEN_TBIEN |308 NPCM7XX_FAN_TIEN_TFIEN),309 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));310 311 reg_mode =312 NPCM7XX_FAN_TCKC_CLK2_APB313 | ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base,314 fan));315 316 /* start to Capture */317 iowrite8(reg_mode,318 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));319 }320 321 spin_unlock_irqrestore(&data->fan_lock[fan], flags);322 }323}324 325/*326 * Enable a background timer to poll fan tach value, (200ms * 4)327 * to polling all fan328 */329static void npcm7xx_fan_polling(struct timer_list *t)330{331 struct npcm7xx_pwm_fan_data *data;332 int i;333 334 data = from_timer(data, t, fan_timer);335 336 /*337 * Polling two module per one round,338 * FAN01 & FAN89 / FAN23 & FAN1011 / FAN45 & FAN1213 / FAN67 & FAN1415339 */340 for (i = data->fan_select; i < NPCM7XX_FAN_MAX_MODULE;341 i = i + 4) {342 /* clear the flag and reset the counter (TCNT) */343 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,344 NPCM7XX_FAN_REG_TICLR(data->fan_base, i));345 346 if (data->fan_present[i * 2]) {347 iowrite16(NPCM7XX_FAN_TCNT,348 NPCM7XX_FAN_REG_TCNT1(data->fan_base, i));349 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPA);350 }351 if (data->fan_present[(i * 2) + 1]) {352 iowrite16(NPCM7XX_FAN_TCNT,353 NPCM7XX_FAN_REG_TCNT2(data->fan_base, i));354 npcm7xx_fan_start_capture(data, i, NPCM7XX_FAN_CMPB);355 }356 }357 358 data->fan_select++;359 data->fan_select &= 0x3;360 361 /* reset the timer interval */362 data->fan_timer.expires = jiffies +363 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);364 add_timer(&data->fan_timer);365}366 367static inline void npcm7xx_fan_compute(struct npcm7xx_pwm_fan_data *data,368 u8 fan, u8 cmp, u8 fan_id, u8 flag_int,369 u8 flag_mode, u8 flag_clear)370{371 u8 reg_int;372 u8 reg_mode;373 u16 fan_cap;374 375 if (cmp == NPCM7XX_FAN_CMPA)376 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRA(data->fan_base, fan));377 else378 fan_cap = ioread16(NPCM7XX_FAN_REG_TCRB(data->fan_base, fan));379 380 /* clear capature flag, H/W will auto reset the NPCM7XX_FAN_TCNTx */381 iowrite8(flag_clear, NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));382 383 if (data->fan_dev[fan_id].fan_st_flg == FAN_INIT) {384 /* First capture, drop it */385 data->fan_dev[fan_id].fan_st_flg =386 FAN_PREPARE_TO_GET_FIRST_CAPTURE;387 388 /* reset counter */389 data->fan_dev[fan_id].fan_cnt_tmp = 0;390 } else if (data->fan_dev[fan_id].fan_st_flg < FAN_ENOUGH_SAMPLE) {391 /*392 * collect the enough sample,393 * (ex: 2 pulse fan need to get 2 sample)394 */395 data->fan_dev[fan_id].fan_cnt_tmp +=396 (NPCM7XX_FAN_TCNT - fan_cap);397 398 data->fan_dev[fan_id].fan_st_flg++;399 } else {400 /* get enough sample or fan disable */401 if (data->fan_dev[fan_id].fan_st_flg == FAN_ENOUGH_SAMPLE) {402 data->fan_dev[fan_id].fan_cnt_tmp +=403 (NPCM7XX_FAN_TCNT - fan_cap);404 405 /* compute finial average cnt per pulse */406 data->fan_dev[fan_id].fan_cnt =407 data->fan_dev[fan_id].fan_cnt_tmp /408 FAN_ENOUGH_SAMPLE;409 410 data->fan_dev[fan_id].fan_st_flg = FAN_INIT;411 }412 413 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));414 415 /* disable interrupt */416 iowrite8((reg_int & ~flag_int),417 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));418 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));419 420 /* stop capturing */421 iowrite8((reg_mode & ~flag_mode),422 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));423 }424}425 426static inline void npcm7xx_check_cmp(struct npcm7xx_pwm_fan_data *data,427 u8 fan, u8 cmp, u8 flag)428{429 u8 reg_int;430 u8 reg_mode;431 u8 flag_timeout;432 u8 flag_cap;433 u8 flag_clear;434 u8 flag_int;435 u8 flag_mode;436 u8 fan_id;437 438 fan_id = NPCM7XX_FAN_INPUT(fan, cmp);439 440 if (cmp == NPCM7XX_FAN_CMPA) {441 flag_cap = NPCM7XX_FAN_TICTRL_TAPND;442 flag_timeout = NPCM7XX_FAN_TICTRL_TEPND;443 flag_int = NPCM7XX_FAN_TIEN_TAIEN | NPCM7XX_FAN_TIEN_TEIEN;444 flag_mode = NPCM7XX_FAN_TCKC_CLK1_APB;445 flag_clear = NPCM7XX_FAN_TICLR_TACLR | NPCM7XX_FAN_TICLR_TECLR;446 } else {447 flag_cap = NPCM7XX_FAN_TICTRL_TBPND;448 flag_timeout = NPCM7XX_FAN_TICTRL_TFPND;449 flag_int = NPCM7XX_FAN_TIEN_TBIEN | NPCM7XX_FAN_TIEN_TFIEN;450 flag_mode = NPCM7XX_FAN_TCKC_CLK2_APB;451 flag_clear = NPCM7XX_FAN_TICLR_TBCLR | NPCM7XX_FAN_TICLR_TFCLR;452 }453 454 if (flag & flag_timeout) {455 reg_int = ioread8(NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));456 457 /* disable interrupt */458 iowrite8((reg_int & ~flag_int),459 NPCM7XX_FAN_REG_TIEN(data->fan_base, fan));460 461 /* clear interrupt flag */462 iowrite8(flag_clear,463 NPCM7XX_FAN_REG_TICLR(data->fan_base, fan));464 465 reg_mode = ioread8(NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));466 467 /* stop capturing */468 iowrite8((reg_mode & ~flag_mode),469 NPCM7XX_FAN_REG_TCKC(data->fan_base, fan));470 471 /*472 * If timeout occurs (NPCM7XX_FAN_TIMEOUT), the fan doesn't473 * connect or speed is lower than 10.6Hz (320RPM/pulse2).474 * In these situation, the RPM output should be zero.475 */476 data->fan_dev[fan_id].fan_cnt = 0;477 } else {478 /* input capture is occurred */479 if (flag & flag_cap)480 npcm7xx_fan_compute(data, fan, cmp, fan_id, flag_int,481 flag_mode, flag_clear);482 }483}484 485static irqreturn_t npcm7xx_fan_isr(int irq, void *dev_id)486{487 struct npcm7xx_pwm_fan_data *data = dev_id;488 unsigned long flags;489 int module;490 u8 flag;491 492 module = irq - data->fan_irq[0];493 spin_lock_irqsave(&data->fan_lock[module], flags);494 495 flag = ioread8(NPCM7XX_FAN_REG_TICTRL(data->fan_base, module));496 if (flag > 0) {497 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPA, flag);498 npcm7xx_check_cmp(data, module, NPCM7XX_FAN_CMPB, flag);499 spin_unlock_irqrestore(&data->fan_lock[module], flags);500 return IRQ_HANDLED;501 }502 503 spin_unlock_irqrestore(&data->fan_lock[module], flags);504 505 return IRQ_NONE;506}507 508static int npcm7xx_read_pwm(struct device *dev, u32 attr, int channel,509 long *val)510{511 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);512 u32 pmw_ch = (channel % NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);513 u32 module = (channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE);514 515 switch (attr) {516 case hwmon_pwm_input:517 *val = ioread32518 (NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pmw_ch));519 return 0;520 default:521 return -EOPNOTSUPP;522 }523}524 525static int npcm7xx_write_pwm(struct device *dev, u32 attr, int channel,526 long val)527{528 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);529 int err;530 531 switch (attr) {532 case hwmon_pwm_input:533 if (val < 0 || val > NPCM7XX_PWM_CMR_MAX)534 return -EINVAL;535 err = npcm7xx_pwm_config_set(data, channel, (u16)val);536 break;537 default:538 err = -EOPNOTSUPP;539 break;540 }541 542 return err;543}544 545static umode_t npcm7xx_pwm_is_visible(const void *_data, u32 attr, int channel)546{547 const struct npcm7xx_pwm_fan_data *data = _data;548 549 if (!data->pwm_present[channel] || channel >= data->info->pwm_max_channel)550 return 0;551 552 switch (attr) {553 case hwmon_pwm_input:554 return 0644;555 default:556 return 0;557 }558}559 560static int npcm7xx_read_fan(struct device *dev, u32 attr, int channel,561 long *val)562{563 struct npcm7xx_pwm_fan_data *data = dev_get_drvdata(dev);564 565 switch (attr) {566 case hwmon_fan_input:567 *val = 0;568 if (data->fan_dev[channel].fan_cnt <= 0)569 return data->fan_dev[channel].fan_cnt;570 571 /* Convert the raw reading to RPM */572 if (data->fan_dev[channel].fan_cnt > 0 &&573 data->fan_dev[channel].fan_pls_per_rev > 0)574 *val = ((data->input_clk_freq * 60) /575 (data->fan_dev[channel].fan_cnt *576 data->fan_dev[channel].fan_pls_per_rev));577 return 0;578 default:579 return -EOPNOTSUPP;580 }581}582 583static umode_t npcm7xx_fan_is_visible(const void *_data, u32 attr, int channel)584{585 const struct npcm7xx_pwm_fan_data *data = _data;586 587 if (!data->fan_present[channel])588 return 0;589 590 switch (attr) {591 case hwmon_fan_input:592 return 0444;593 default:594 return 0;595 }596}597 598static int npcm7xx_read(struct device *dev, enum hwmon_sensor_types type,599 u32 attr, int channel, long *val)600{601 switch (type) {602 case hwmon_pwm:603 return npcm7xx_read_pwm(dev, attr, channel, val);604 case hwmon_fan:605 return npcm7xx_read_fan(dev, attr, channel, val);606 default:607 return -EOPNOTSUPP;608 }609}610 611static int npcm7xx_write(struct device *dev, enum hwmon_sensor_types type,612 u32 attr, int channel, long val)613{614 switch (type) {615 case hwmon_pwm:616 return npcm7xx_write_pwm(dev, attr, channel, val);617 default:618 return -EOPNOTSUPP;619 }620}621 622static umode_t npcm7xx_is_visible(const void *data,623 enum hwmon_sensor_types type,624 u32 attr, int channel)625{626 switch (type) {627 case hwmon_pwm:628 return npcm7xx_pwm_is_visible(data, attr, channel);629 case hwmon_fan:630 return npcm7xx_fan_is_visible(data, attr, channel);631 default:632 return 0;633 }634}635 636static const struct hwmon_channel_info * const npcm7xx_info[] = {637 HWMON_CHANNEL_INFO(pwm,638 HWMON_PWM_INPUT,639 HWMON_PWM_INPUT,640 HWMON_PWM_INPUT,641 HWMON_PWM_INPUT,642 HWMON_PWM_INPUT,643 HWMON_PWM_INPUT,644 HWMON_PWM_INPUT,645 HWMON_PWM_INPUT,646 HWMON_PWM_INPUT,647 HWMON_PWM_INPUT,648 HWMON_PWM_INPUT,649 HWMON_PWM_INPUT),650 HWMON_CHANNEL_INFO(fan,651 HWMON_F_INPUT,652 HWMON_F_INPUT,653 HWMON_F_INPUT,654 HWMON_F_INPUT,655 HWMON_F_INPUT,656 HWMON_F_INPUT,657 HWMON_F_INPUT,658 HWMON_F_INPUT,659 HWMON_F_INPUT,660 HWMON_F_INPUT,661 HWMON_F_INPUT,662 HWMON_F_INPUT,663 HWMON_F_INPUT,664 HWMON_F_INPUT,665 HWMON_F_INPUT,666 HWMON_F_INPUT),667 NULL668};669 670static const struct hwmon_ops npcm7xx_hwmon_ops = {671 .is_visible = npcm7xx_is_visible,672 .read = npcm7xx_read,673 .write = npcm7xx_write,674};675 676static const struct hwmon_chip_info npcm7xx_chip_info = {677 .ops = &npcm7xx_hwmon_ops,678 .info = npcm7xx_info,679};680 681static const struct npcm_hwmon_info npxm7xx_hwmon_info = {682 .pwm_max_channel = 8,683};684 685static const struct npcm_hwmon_info npxm8xx_hwmon_info = {686 .pwm_max_channel = 12,687};688 689static u32 npcm7xx_pwm_init(struct npcm7xx_pwm_fan_data *data)690{691 int m, ch;692 u32 prescale_val, output_freq;693 unsigned long pwm_clk_freq;694 695 pwm_clk_freq = clk_get_rate(data->pwm_clk);696 697 /* Adjust NPCM7xx PWMs output frequency to ~25Khz */698 output_freq = pwm_clk_freq / PWN_CNT_DEFAULT;699 prescale_val = DIV_ROUND_CLOSEST(output_freq, PWM_OUTPUT_FREQ_25KHZ);700 701 /* If prescale_val = 0, then the prescale output clock is stopped */702 if (prescale_val < MIN_PRESCALE1)703 prescale_val = MIN_PRESCALE1;704 /*705 * prescale_val need to decrement in one because in the PWM Prescale706 * register the Prescale value increment by one707 */708 prescale_val--;709 710 /* Setting PWM Prescale Register value register to both modules */711 prescale_val |= (prescale_val << NPCM7XX_PWM_PRESCALE_SHIFT_CH01);712 713 for (m = 0; m < data->pwm_modules; m++) {714 iowrite32(prescale_val, NPCM7XX_PWM_REG_PR(data->pwm_base, m));715 iowrite32(NPCM7XX_PWM_PRESCALE2_DEFAULT,716 NPCM7XX_PWM_REG_CSR(data->pwm_base, m));717 iowrite32(NPCM7XX_PWM_CTRL_MODE_DEFAULT,718 NPCM7XX_PWM_REG_CR(data->pwm_base, m));719 720 for (ch = 0; ch < NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE; ch++) {721 iowrite32(NPCM7XX_PWM_COUNTER_DEFAULT_NUM,722 NPCM7XX_PWM_REG_CNRx(data->pwm_base, m, ch));723 }724 }725 726 return output_freq / ((prescale_val & 0xf) + 1);727}728 729static void npcm7xx_fan_init(struct npcm7xx_pwm_fan_data *data)730{731 int md;732 int ch;733 int i;734 u32 apb_clk_freq;735 736 for (md = 0; md < NPCM7XX_FAN_MAX_MODULE; md++) {737 /* stop FAN0~7 clock */738 iowrite8(NPCM7XX_FAN_TCKC_CLKX_NONE,739 NPCM7XX_FAN_REG_TCKC(data->fan_base, md));740 741 /* disable all interrupt */742 iowrite8(0x00, NPCM7XX_FAN_REG_TIEN(data->fan_base, md));743 744 /* clear all interrupt */745 iowrite8(NPCM7XX_FAN_TICLR_CLEAR_ALL,746 NPCM7XX_FAN_REG_TICLR(data->fan_base, md));747 748 /* set FAN0~7 clock prescaler */749 iowrite8(NPCM7XX_FAN_CLK_PRESCALE,750 NPCM7XX_FAN_REG_TPRSC(data->fan_base, md));751 752 /* set FAN0~7 mode (high-to-low transition) */753 iowrite8((NPCM7XX_FAN_TMCTRL_MODE_5 | NPCM7XX_FAN_TMCTRL_TBEN |754 NPCM7XX_FAN_TMCTRL_TAEN),755 NPCM7XX_FAN_REG_TMCTRL(data->fan_base, md));756 757 /* set FAN0~7 Initial Count/Cap */758 iowrite16(NPCM7XX_FAN_TCNT,759 NPCM7XX_FAN_REG_TCNT1(data->fan_base, md));760 iowrite16(NPCM7XX_FAN_TCNT,761 NPCM7XX_FAN_REG_TCNT2(data->fan_base, md));762 763 /* set FAN0~7 compare (equal to count) */764 iowrite8((NPCM7XX_FAN_TCPCFG_EQAEN | NPCM7XX_FAN_TCPCFG_EQBEN),765 NPCM7XX_FAN_REG_TCPCFG(data->fan_base, md));766 767 /* set FAN0~7 compare value */768 iowrite16(NPCM7XX_FAN_TCPA,769 NPCM7XX_FAN_REG_TCPA(data->fan_base, md));770 iowrite16(NPCM7XX_FAN_TCPB,771 NPCM7XX_FAN_REG_TCPB(data->fan_base, md));772 773 /* set FAN0~7 fan input FANIN 0~15 */774 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,775 NPCM7XX_FAN_REG_TINASEL(data->fan_base, md));776 iowrite8(NPCM7XX_FAN_TINASEL_FANIN_DEFAULT,777 NPCM7XX_FAN_REG_TINBSEL(data->fan_base, md));778 779 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE; i++) {780 ch = md * NPCM7XX_FAN_MAX_CHN_NUM_IN_A_MODULE + i;781 data->fan_dev[ch].fan_st_flg = FAN_DISABLE;782 data->fan_dev[ch].fan_pls_per_rev =783 NPCM7XX_FAN_DEFAULT_PULSE_PER_REVOLUTION;784 data->fan_dev[ch].fan_cnt = 0;785 }786 }787 788 apb_clk_freq = clk_get_rate(data->fan_clk);789 790 /* Fan tach input clock = APB clock / prescalar, default is 255. */791 data->input_clk_freq = apb_clk_freq / (NPCM7XX_FAN_CLK_PRESCALE + 1);792}793 794static int795npcm7xx_pwm_cz_get_max_state(struct thermal_cooling_device *tcdev,796 unsigned long *state)797{798 struct npcm7xx_cooling_device *cdev = tcdev->devdata;799 800 *state = cdev->max_state;801 802 return 0;803}804 805static int806npcm7xx_pwm_cz_get_cur_state(struct thermal_cooling_device *tcdev,807 unsigned long *state)808{809 struct npcm7xx_cooling_device *cdev = tcdev->devdata;810 811 *state = cdev->cur_state;812 813 return 0;814}815 816static int817npcm7xx_pwm_cz_set_cur_state(struct thermal_cooling_device *tcdev,818 unsigned long state)819{820 struct npcm7xx_cooling_device *cdev = tcdev->devdata;821 int ret;822 823 if (state > cdev->max_state)824 return -EINVAL;825 826 cdev->cur_state = state;827 ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,828 cdev->cooling_levels[cdev->cur_state]);829 830 return ret;831}832 833static const struct thermal_cooling_device_ops npcm7xx_pwm_cool_ops = {834 .get_max_state = npcm7xx_pwm_cz_get_max_state,835 .get_cur_state = npcm7xx_pwm_cz_get_cur_state,836 .set_cur_state = npcm7xx_pwm_cz_set_cur_state,837};838 839static int npcm7xx_create_pwm_cooling(struct device *dev,840 struct device_node *child,841 struct npcm7xx_pwm_fan_data *data,842 u32 pwm_port, u8 num_levels)843{844 int ret;845 struct npcm7xx_cooling_device *cdev;846 847 cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);848 if (!cdev)849 return -ENOMEM;850 851 cdev->cooling_levels = devm_kzalloc(dev, num_levels, GFP_KERNEL);852 if (!cdev->cooling_levels)853 return -ENOMEM;854 855 cdev->max_state = num_levels - 1;856 ret = of_property_read_u8_array(child, "cooling-levels",857 cdev->cooling_levels,858 num_levels);859 if (ret) {860 dev_err(dev, "Property 'cooling-levels' cannot be read.\n");861 return ret;862 }863 snprintf(cdev->name, THERMAL_NAME_LENGTH, "%pOFn%d", child,864 pwm_port);865 866 cdev->tcdev = devm_thermal_of_cooling_device_register(dev, child,867 cdev->name, cdev, &npcm7xx_pwm_cool_ops);868 if (IS_ERR(cdev->tcdev))869 return PTR_ERR(cdev->tcdev);870 871 cdev->data = data;872 cdev->pwm_port = pwm_port;873 874 data->cdev[pwm_port] = cdev;875 876 return 0;877}878 879static int npcm7xx_en_pwm_fan(struct device *dev,880 struct device_node *child,881 struct npcm7xx_pwm_fan_data *data)882{883 u8 *fan_ch;884 u32 pwm_port;885 int ret, fan_cnt;886 u8 index, ch;887 888 ret = of_property_read_u32(child, "reg", &pwm_port);889 if (ret)890 return ret;891 892 data->pwm_present[pwm_port] = true;893 ret = npcm7xx_pwm_config_set(data, pwm_port,894 NPCM7XX_PWM_CMR_DEFAULT_NUM);895 if (ret)896 return ret;897 898 ret = of_property_count_u8_elems(child, "cooling-levels");899 if (ret > 0) {900 ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,901 ret);902 if (ret)903 return ret;904 }905 906 fan_cnt = of_property_count_u8_elems(child, "fan-tach-ch");907 if (fan_cnt < 1)908 return -EINVAL;909 910 fan_ch = devm_kcalloc(dev, fan_cnt, sizeof(*fan_ch), GFP_KERNEL);911 if (!fan_ch)912 return -ENOMEM;913 914 ret = of_property_read_u8_array(child, "fan-tach-ch", fan_ch, fan_cnt);915 if (ret)916 return ret;917 918 for (ch = 0; ch < fan_cnt; ch++) {919 index = fan_ch[ch];920 data->fan_present[index] = true;921 data->fan_dev[index].fan_st_flg = FAN_INIT;922 }923 924 return 0;925}926 927static int npcm7xx_pwm_fan_probe(struct platform_device *pdev)928{929 struct device *dev = &pdev->dev;930 struct device_node *np;931 struct npcm7xx_pwm_fan_data *data;932 struct resource *res;933 struct device *hwmon;934 char name[20];935 int ret, cnt;936 u32 output_freq;937 u32 i;938 939 np = dev->of_node;940 941 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);942 if (!data)943 return -ENOMEM;944 945 data->info = device_get_match_data(dev);946 if (!data->info)947 return -EINVAL;948 949 data->pwm_modules = data->info->pwm_max_channel / NPCM7XX_PWM_MAX_CHN_NUM_IN_A_MODULE;950 951 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm");952 if (!res) {953 dev_err(dev, "pwm resource not found\n");954 return -ENODEV;955 }956 957 data->pwm_base = devm_ioremap_resource(dev, res);958 dev_dbg(dev, "pwm base resource is %pR\n", res);959 if (IS_ERR(data->pwm_base))960 return PTR_ERR(data->pwm_base);961 962 data->pwm_clk = devm_clk_get(dev, "pwm");963 if (IS_ERR(data->pwm_clk)) {964 dev_err(dev, "couldn't get pwm clock\n");965 return PTR_ERR(data->pwm_clk);966 }967 968 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fan");969 if (!res) {970 dev_err(dev, "fan resource not found\n");971 return -ENODEV;972 }973 974 data->fan_base = devm_ioremap_resource(dev, res);975 dev_dbg(dev, "fan base resource is %pR\n", res);976 if (IS_ERR(data->fan_base))977 return PTR_ERR(data->fan_base);978 979 data->fan_clk = devm_clk_get(dev, "fan");980 if (IS_ERR(data->fan_clk)) {981 dev_err(dev, "couldn't get fan clock\n");982 return PTR_ERR(data->fan_clk);983 }984 985 output_freq = npcm7xx_pwm_init(data);986 npcm7xx_fan_init(data);987 988 for (cnt = 0; cnt < data->pwm_modules; cnt++)989 mutex_init(&data->pwm_lock[cnt]);990 991 for (i = 0; i < NPCM7XX_FAN_MAX_MODULE; i++) {992 spin_lock_init(&data->fan_lock[i]);993 994 data->fan_irq[i] = platform_get_irq(pdev, i);995 if (data->fan_irq[i] < 0)996 return data->fan_irq[i];997 998 sprintf(name, "NPCM7XX-FAN-MD%d", i);999 ret = devm_request_irq(dev, data->fan_irq[i], npcm7xx_fan_isr,1000 0, name, (void *)data);1001 if (ret) {1002 dev_err(dev, "register IRQ fan%d failed\n", i);1003 return ret;1004 }1005 }1006 1007 for_each_child_of_node_scoped(np, child) {1008 ret = npcm7xx_en_pwm_fan(dev, child, data);1009 if (ret) {1010 dev_err(dev, "enable pwm and fan failed\n");1011 return ret;1012 }1013 }1014 1015 hwmon = devm_hwmon_device_register_with_info(dev, "npcm7xx_pwm_fan",1016 data, &npcm7xx_chip_info,1017 NULL);1018 if (IS_ERR(hwmon)) {1019 dev_err(dev, "unable to register hwmon device\n");1020 return PTR_ERR(hwmon);1021 }1022 1023 for (i = 0; i < NPCM7XX_FAN_MAX_CHN_NUM; i++) {1024 if (data->fan_present[i]) {1025 /* fan timer initialization */1026 data->fan_timer.expires = jiffies +1027 msecs_to_jiffies(NPCM7XX_FAN_POLL_TIMER_200MS);1028 timer_setup(&data->fan_timer,1029 npcm7xx_fan_polling, 0);1030 add_timer(&data->fan_timer);1031 break;1032 }1033 }1034 1035 pr_info("NPCM7XX PWM-FAN Driver probed, output Freq %dHz[PWM], input Freq %dHz[FAN]\n",1036 output_freq, data->input_clk_freq);1037 1038 return 0;1039}1040 1041static const struct of_device_id of_pwm_fan_match_table[] = {1042 { .compatible = "nuvoton,npcm750-pwm-fan", .data = &npxm7xx_hwmon_info},1043 { .compatible = "nuvoton,npcm845-pwm-fan", .data = &npxm8xx_hwmon_info},1044 {},1045};1046MODULE_DEVICE_TABLE(of, of_pwm_fan_match_table);1047 1048static struct platform_driver npcm7xx_pwm_fan_driver = {1049 .probe = npcm7xx_pwm_fan_probe,1050 .driver = {1051 .name = "npcm7xx_pwm_fan",1052 .of_match_table = of_pwm_fan_match_table,1053 },1054};1055 1056module_platform_driver(npcm7xx_pwm_fan_driver);1057 1058MODULE_DESCRIPTION("Nuvoton NPCM7XX PWM and Fan Tacho driver");1059MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");1060MODULE_LICENSE("GPL v2");1061