211 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * sun6i_hwspinlock.c - hardware spinlock driver for sun6i compatible Allwinner SoCs4 * Copyright (C) 2020 Wilken Gottwalt <wilken.gottwalt@posteo.net>5 */6 7#include <linux/clk.h>8#include <linux/debugfs.h>9#include <linux/errno.h>10#include <linux/hwspinlock.h>11#include <linux/io.h>12#include <linux/module.h>13#include <linux/of.h>14#include <linux/platform_device.h>15#include <linux/reset.h>16#include <linux/slab.h>17#include <linux/spinlock.h>18#include <linux/types.h>19 20#include "hwspinlock_internal.h"21 22#define DRIVER_NAME "sun6i_hwspinlock"23 24#define SPINLOCK_BASE_ID 0 /* there is only one hwspinlock device per SoC */25#define SPINLOCK_SYSSTATUS_REG 0x000026#define SPINLOCK_LOCK_REGN 0x010027#define SPINLOCK_NOTTAKEN 028 29struct sun6i_hwspinlock_data {30 struct hwspinlock_device *bank;31 struct reset_control *reset;32 struct clk *ahb_clk;33 struct dentry *debugfs;34 int nlocks;35};36 37#ifdef CONFIG_DEBUG_FS38 39static int hwlocks_supported_show(struct seq_file *seqf, void *unused)40{41 struct sun6i_hwspinlock_data *priv = seqf->private;42 43 seq_printf(seqf, "%d\n", priv->nlocks);44 45 return 0;46}47DEFINE_SHOW_ATTRIBUTE(hwlocks_supported);48 49static void sun6i_hwspinlock_debugfs_init(struct sun6i_hwspinlock_data *priv)50{51 priv->debugfs = debugfs_create_dir(DRIVER_NAME, NULL);52 debugfs_create_file("supported", 0444, priv->debugfs, priv, &hwlocks_supported_fops);53}54 55#else56 57static void sun6i_hwspinlock_debugfs_init(struct sun6i_hwspinlock_data *priv)58{59}60 61#endif62 63static int sun6i_hwspinlock_trylock(struct hwspinlock *lock)64{65 void __iomem *lock_addr = lock->priv;66 67 return (readl(lock_addr) == SPINLOCK_NOTTAKEN);68}69 70static void sun6i_hwspinlock_unlock(struct hwspinlock *lock)71{72 void __iomem *lock_addr = lock->priv;73 74 writel(SPINLOCK_NOTTAKEN, lock_addr);75}76 77static const struct hwspinlock_ops sun6i_hwspinlock_ops = {78 .trylock = sun6i_hwspinlock_trylock,79 .unlock = sun6i_hwspinlock_unlock,80};81 82static void sun6i_hwspinlock_disable(void *data)83{84 struct sun6i_hwspinlock_data *priv = data;85 86 debugfs_remove_recursive(priv->debugfs);87 clk_disable_unprepare(priv->ahb_clk);88 reset_control_assert(priv->reset);89}90 91static int sun6i_hwspinlock_probe(struct platform_device *pdev)92{93 struct sun6i_hwspinlock_data *priv;94 struct hwspinlock *hwlock;95 void __iomem *io_base;96 u32 num_banks;97 int err, i;98 99 io_base = devm_platform_ioremap_resource(pdev, SPINLOCK_BASE_ID);100 if (IS_ERR(io_base))101 return PTR_ERR(io_base);102 103 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);104 if (!priv)105 return -ENOMEM;106 107 priv->ahb_clk = devm_clk_get(&pdev->dev, "ahb");108 if (IS_ERR(priv->ahb_clk)) {109 err = PTR_ERR(priv->ahb_clk);110 dev_err(&pdev->dev, "unable to get AHB clock (%d)\n", err);111 return err;112 }113 114 priv->reset = devm_reset_control_get(&pdev->dev, "ahb");115 if (IS_ERR(priv->reset))116 return dev_err_probe(&pdev->dev, PTR_ERR(priv->reset),117 "unable to get reset control\n");118 119 err = reset_control_deassert(priv->reset);120 if (err) {121 dev_err(&pdev->dev, "deassert reset control failure (%d)\n", err);122 return err;123 }124 125 err = clk_prepare_enable(priv->ahb_clk);126 if (err) {127 dev_err(&pdev->dev, "unable to prepare AHB clk (%d)\n", err);128 goto clk_fail;129 }130 131 /*132 * bit 28 and 29 represents the hwspinlock setup133 *134 * every datasheet (A64, A80, A83T, H3, H5, H6 ...) says the default value is 0x1 and 0x1135 * to 0x4 represent 32, 64, 128 and 256 locks136 * but later datasheets (H5, H6) say 00, 01, 10, 11 represent 32, 64, 128 and 256 locks,137 * but that would mean H5 and H6 have 64 locks, while their datasheets talk about 32 locks138 * all the time, not a single mentioning of 64 locks139 * the 0x4 value is also not representable by 2 bits alone, so some datasheets are not140 * correct141 * one thing have all in common, default value of the sysstatus register is 0x10000000,142 * which results in bit 28 being set143 * this is the reason 0x1 is considered being 32 locks and bit 30 is taken into account144 * verified on H2+ (datasheet 0x1 = 32 locks) and H5 (datasheet 01 = 64 locks)145 */146 num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28;147 switch (num_banks) {148 case 1 ... 4:149 priv->nlocks = 1 << (4 + num_banks);150 break;151 default:152 err = -EINVAL;153 dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks);154 goto bank_fail;155 }156 157 priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks),158 GFP_KERNEL);159 if (!priv->bank) {160 err = -ENOMEM;161 goto bank_fail;162 }163 164 for (i = 0; i < priv->nlocks; ++i) {165 hwlock = &priv->bank->lock[i];166 hwlock->priv = io_base + SPINLOCK_LOCK_REGN + sizeof(u32) * i;167 }168 169 /* failure of debugfs is considered non-fatal */170 sun6i_hwspinlock_debugfs_init(priv);171 if (IS_ERR(priv->debugfs))172 priv->debugfs = NULL;173 174 err = devm_add_action_or_reset(&pdev->dev, sun6i_hwspinlock_disable, priv);175 if (err) {176 dev_err(&pdev->dev, "failed to add hwspinlock disable action\n");177 goto bank_fail;178 }179 180 platform_set_drvdata(pdev, priv);181 182 return devm_hwspin_lock_register(&pdev->dev, priv->bank, &sun6i_hwspinlock_ops,183 SPINLOCK_BASE_ID, priv->nlocks);184 185bank_fail:186 clk_disable_unprepare(priv->ahb_clk);187clk_fail:188 reset_control_assert(priv->reset);189 190 return err;191}192 193static const struct of_device_id sun6i_hwspinlock_ids[] = {194 { .compatible = "allwinner,sun6i-a31-hwspinlock", },195 {},196};197MODULE_DEVICE_TABLE(of, sun6i_hwspinlock_ids);198 199static struct platform_driver sun6i_hwspinlock_driver = {200 .probe = sun6i_hwspinlock_probe,201 .driver = {202 .name = DRIVER_NAME,203 .of_match_table = sun6i_hwspinlock_ids,204 },205};206module_platform_driver(sun6i_hwspinlock_driver);207 208MODULE_LICENSE("GPL");209MODULE_DESCRIPTION("SUN6I hardware spinlock driver");210MODULE_AUTHOR("Wilken Gottwalt <wilken.gottwalt@posteo.net>");211