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1# SPDX-License-Identifier: GPL-2.0-only2#3# Coresight configuration4#5menuconfig CORESIGHT6 tristate "CoreSight Tracing Support"7 depends on ARM || ARM648 depends on OF || ACPI9 select ARM_AMBA10 select PERF_EVENTS11 select CONFIGFS_FS12 help13 This framework provides a kernel interface for the CoreSight debug14 and trace drivers to register themselves with. It's intended to build15 a topological view of the CoreSight components based on a DT16 specification and configure the right series of components when a17 trace source gets enabled.18 19 To compile this driver as a module, choose M here: the20 module will be called coresight.21 22if CORESIGHT23config CORESIGHT_LINKS_AND_SINKS24 tristate "CoreSight Link and Sink drivers"25 help26 This enables support for CoreSight link and sink drivers that are27 responsible for transporting and collecting the trace data28 respectively. Link and sinks are dynamically aggregated with a trace29 entity at run time to form a complete trace path.30 31 To compile these drivers as modules, choose M here: the32 modules will be called coresight-funnel and coresight-replicator.33 34config CORESIGHT_LINK_AND_SINK_TMC35 tristate "Coresight generic TMC driver"36 37 depends on CORESIGHT_LINKS_AND_SINKS38 help39 This enables support for the Trace Memory Controller driver.40 Depending on its configuration the device can act as a link (embedded41 trace router - ETR) or sink (embedded trace FIFO). The driver42 complies with the generic implementation of the component without43 special enhancement or added features.44 45 To compile this driver as a module, choose M here: the46 module will be called coresight-tmc.47 48config CORESIGHT_CATU49 tristate "Coresight Address Translation Unit (CATU) driver"50 depends on CORESIGHT_LINK_AND_SINK_TMC51 help52 Enable support for the Coresight Address Translation Unit (CATU).53 CATU supports a scatter gather table of 4K pages, with forward/backward54 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace55 buffer by translating the addresses used by ETR to the physical address56 by looking up the provided table. CATU can also be used in pass-through57 mode where the address is not translated.58 59 To compile this driver as a module, choose M here: the60 module will be called coresight-catu.61 62config CORESIGHT_SINK_TPIU63 tristate "Coresight generic TPIU driver"64 depends on CORESIGHT_LINKS_AND_SINKS65 help66 This enables support for the Trace Port Interface Unit driver,67 responsible for bridging the gap between the on-chip coresight68 components and a trace for bridging the gap between the on-chip69 coresight components and a trace port collection engine, typically70 connected to an external host for use case capturing more traces than71 the on-board coresight memory can handle.72 73 To compile this driver as a module, choose M here: the74 module will be called coresight-tpiu.75 76config CORESIGHT_SINK_ETBV1077 tristate "Coresight ETBv1.0 driver"78 depends on CORESIGHT_LINKS_AND_SINKS79 help80 This enables support for the Embedded Trace Buffer version 1.0 driver81 that complies with the generic implementation of the component without82 special enhancement or added features.83 84 To compile this driver as a module, choose M here: the85 module will be called coresight-etb10.86 87config CORESIGHT_SOURCE_ETM3X88 tristate "CoreSight Embedded Trace Macrocell 3.x driver"89 depends on !ARM6490 select CORESIGHT_LINKS_AND_SINKS91 help92 This driver provides support for processor ETM3.x and PTM1.x modules,93 which allows tracing the instructions that a processor is executing94 This is primarily useful for instruction level tracing. Depending95 the ETM version data tracing may also be available.96 97 To compile this driver as a module, choose M here: the98 module will be called coresight-etm3x.99 100config CORESIGHT_SOURCE_ETM4X101 tristate "CoreSight ETMv4.x / ETE driver"102 depends on ARM64103 select CORESIGHT_LINKS_AND_SINKS104 select PID_IN_CONTEXTIDR105 help106 This driver provides support for the CoreSight Embedded Trace Macrocell107 version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer108 modules, tracing the instructions that a processor is executing. This is109 primarily useful for instruction level tracing.110 111 To compile this driver as a module, choose M here: the112 module will be called coresight-etm4x.113 114config ETM4X_IMPDEF_FEATURE115 bool "Control implementation defined overflow support in ETM 4.x driver"116 depends on CORESIGHT_SOURCE_ETM4X117 help118 This control provides implementation define control for CoreSight119 ETM 4.x tracer module that can't reduce commit rate automatically.120 This avoids overflow between the ETM tracer module and the cpu core.121 122config CORESIGHT_STM123 tristate "CoreSight System Trace Macrocell driver"124 depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64125 select CORESIGHT_LINKS_AND_SINKS126 select STM127 help128 This driver provides support for hardware assisted software129 instrumentation based tracing. This is primarily used for130 logging useful software events or data coming from various entities131 in the system, possibly running different OSs132 133 To compile this driver as a module, choose M here: the134 module will be called coresight-stm.135 136config CORESIGHT_CPU_DEBUG137 tristate "CoreSight CPU Debug driver"138 depends on ARM || ARM64139 depends on DEBUG_FS140 help141 This driver provides support for coresight debugging module. This142 is primarily used to dump sample-based profiling registers when143 system triggers panic, the driver will parse context registers so144 can quickly get to know program counter (PC), secure state,145 exception level, etc. Before use debugging functionality, platform146 needs to ensure the clock domain and power domain are enabled147 properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst148 for detailed description and the example for usage.149 150 To compile this driver as a module, choose M here: the151 module will be called coresight-cpu-debug.152 153config CORESIGHT_CPU_DEBUG_DEFAULT_ON154 bool "Enable CoreSight CPU Debug by default"155 depends on CORESIGHT_CPU_DEBUG156 help157 Say Y here to enable the CoreSight Debug panic-debug by default. This158 can also be enabled via debugfs, but this ensures the debug feature159 is enabled as early as possible.160 161 Has the same effect as setting coresight_cpu_debug.enable=1 on the162 kernel command line.163 164 Say N if unsure.165 166config CORESIGHT_CTI167 tristate "CoreSight Cross Trigger Interface (CTI) driver"168 depends on ARM || ARM64169 help170 This driver provides support for CoreSight CTI and CTM components.171 These provide hardware triggering events between CoreSight trace172 source and sink components. These can be used to halt trace or173 inject events into the trace stream. CTI also provides a software174 control to trigger the same halt events. This can provide fast trace175 halt compared to disabling sources and sinks normally in driver176 software.177 178 To compile this driver as a module, choose M here: the179 module will be called coresight-cti.180 181config CORESIGHT_CTI_INTEGRATION_REGS182 bool "Access CTI CoreSight Integration Registers"183 depends on CORESIGHT_CTI184 help185 This option adds support for the CoreSight integration registers on186 this device. The integration registers allow the exploration of the187 CTI trigger connections between this and other devices.These188 registers are not used in normal operation and can leave devices in189 an inconsistent state.190 191config CORESIGHT_TRBE192 tristate "Trace Buffer Extension (TRBE) driver"193 depends on ARM64 && CORESIGHT_SOURCE_ETM4X194 help195 This driver provides support for percpu Trace Buffer Extension (TRBE).196 TRBE always needs to be used along with its corresponding percpu ETE197 component. ETE generates trace data which is then captured with TRBE.198 Unlike traditional sink devices, TRBE is a CPU feature accessible via199 system registers. But its explicit dependency with trace unit (ETE)200 requires it to be plugged in as a coresight sink device.201 202 To compile this driver as a module, choose M here: the module will be203 called coresight-trbe.204 205config ULTRASOC_SMB206 tristate "Ultrasoc system memory buffer drivers"207 depends on ACPI || COMPILE_TEST208 depends on ARM64 && CORESIGHT_LINKS_AND_SINKS209 help210 This driver provides support for the Ultrasoc system memory buffer (SMB).211 SMB is responsible for receiving the trace data from Coresight ETM devices212 and storing them to a system buffer.213 214 To compile this driver as a module, choose M here: the module will be215 called ultrasoc-smb.216 217config CORESIGHT_TPDM218 tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver"219 select CORESIGHT_LINKS_AND_SINKS220 select CORESIGHT_TPDA221 help222 This driver provides support for configuring monitor. Monitors are223 primarily responsible for data set collection and support the224 ability to collect any permutation of data set types.225 226 To compile this driver as a module, choose M here: the module will be227 called coresight-tpdm.228 229config CORESIGHT_TPDA230 tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver"231 help232 This driver provides support for configuring aggregator. This is233 primarily useful for pulling the data sets from one or more234 attached monitors and pushing the resultant data out. Multiple235 monitors are connected on different input ports of TPDA.236 237 To compile this driver as a module, choose M here: the module will be238 called coresight-tpda.239 240config CORESIGHT_DUMMY241 tristate "Dummy driver support"242 help243 Enables support for dummy driver. Dummy driver can be used for244 CoreSight sources/sinks that are owned and configured by some245 other subsystem and use Linux drivers to configure rest of trace246 path.247 248 To compile this driver as a module, choose M here: the module will be249 called coresight-dummy.250endif251