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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright(C) 2015 Linaro Limited. All rights reserved.4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>5 */6 7#ifndef _CORESIGHT_TMC_H8#define _CORESIGHT_TMC_H9 10#include <linux/dma-mapping.h>11#include <linux/idr.h>12#include <linux/miscdevice.h>13#include <linux/mutex.h>14#include <linux/refcount.h>15 16#define TMC_RSZ 0x00417#define TMC_STS 0x00c18#define TMC_RRD 0x01019#define TMC_RRP 0x01420#define TMC_RWP 0x01821#define TMC_TRG 0x01c22#define TMC_CTL 0x02023#define TMC_RWD 0x02424#define TMC_MODE 0x02825#define TMC_LBUFLEVEL 0x02c26#define TMC_CBUFLEVEL 0x03027#define TMC_BUFWM 0x03428#define TMC_RRPHI 0x03829#define TMC_RWPHI 0x03c30#define TMC_AXICTL 0x11031#define TMC_DBALO 0x11832#define TMC_DBAHI 0x11c33#define TMC_FFSR 0x30034#define TMC_FFCR 0x30435#define TMC_PSCR 0x30836#define TMC_ITMISCOP0 0xee037#define TMC_ITTRFLIN 0xee838#define TMC_ITATBDATA0 0xeec39#define TMC_ITATBCTR2 0xef040#define TMC_ITATBCTR1 0xef441#define TMC_ITATBCTR0 0xef842#define TMC_AUTHSTATUS 0xfb843 44/* register description */45/* TMC_CTL - 0x020 */46#define TMC_CTL_CAPT_EN BIT(0)47/* TMC_STS - 0x00C */48#define TMC_STS_TMCREADY_BIT 249#define TMC_STS_FULL BIT(0)50#define TMC_STS_TRIGGERED BIT(1)51#define TMC_STS_MEMERR BIT(5)52/*53 * TMC_AXICTL - 0x11054 *55 * TMC AXICTL format for SoC-40056 * Bits [0-1] : ProtCtrlBit0-157 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)58 * Bit 6 : Reserved59 * Bit 7 : ScatterGatherMode60 * Bits [8-11] : WrBurstLen61 * Bits [12-31] : Reserved.62 * TMC AXICTL format for SoC-600, as above except:63 * Bits [2-5] : AXI WCACHE64 * Bits [16-19] : AXI RCACHE65 * Bits [20-31] : Reserved66 */67#define TMC_AXICTL_CLEAR_MASK 0xfbf68#define TMC_AXICTL_ARCACHE_MASK (0xf << 16)69 70#define TMC_AXICTL_PROT_CTL_B0 BIT(0)71#define TMC_AXICTL_PROT_CTL_B1 BIT(1)72#define TMC_AXICTL_SCT_GAT_MODE BIT(7)73#define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8)74#define TMC_AXICTL_WR_BURST_16 0xf75/* Write-back Read and Write-allocate */76#define TMC_AXICTL_AXCACHE_OS (0xf << 2)77#define TMC_AXICTL_ARCACHE_OS (0xf << 16)78 79/* TMC_FFCR - 0x304 */80#define TMC_FFCR_FLUSHMAN_BIT 681#define TMC_FFCR_EN_FMT BIT(0)82#define TMC_FFCR_EN_TI BIT(1)83#define TMC_FFCR_FON_FLIN BIT(4)84#define TMC_FFCR_FON_TRIG_EVT BIT(5)85#define TMC_FFCR_TRIGON_TRIGIN BIT(8)86#define TMC_FFCR_STOP_ON_FLUSH BIT(12)87 88 89#define TMC_DEVID_NOSCAT BIT(24)90 91#define TMC_DEVID_AXIAW_VALID BIT(16)92#define TMC_DEVID_AXIAW_SHIFT 1793#define TMC_DEVID_AXIAW_MASK 0x7f94 95#define TMC_AUTH_NSID_MASK GENMASK(1, 0)96 97enum tmc_config_type {98 TMC_CONFIG_TYPE_ETB,99 TMC_CONFIG_TYPE_ETR,100 TMC_CONFIG_TYPE_ETF,101};102 103enum tmc_mode {104 TMC_MODE_CIRCULAR_BUFFER,105 TMC_MODE_SOFTWARE_FIFO,106 TMC_MODE_HARDWARE_FIFO,107};108 109enum tmc_mem_intf_width {110 TMC_MEM_INTF_WIDTH_32BITS = 1,111 TMC_MEM_INTF_WIDTH_64BITS = 2,112 TMC_MEM_INTF_WIDTH_128BITS = 4,113 TMC_MEM_INTF_WIDTH_256BITS = 8,114};115 116/* TMC ETR Capability bit definitions */117#define TMC_ETR_SG (0x1U << 0)118/* ETR has separate read/write cache encodings */119#define TMC_ETR_AXI_ARCACHE (0x1U << 1)120/*121 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are122 * retained when TMC leaves Disabled state, allowing us to continue123 * the tracing from a point where we stopped. This also implies that124 * the RRP/RWP/STS.Full should always be programmed to the correct125 * value. Unfortunately this is not advertised by the hardware,126 * so we have to rely on PID of the IP to detect the functionality.127 */128#define TMC_ETR_SAVE_RESTORE (0x1U << 2)129 130/* Coresight SoC-600 TMC-ETR unadvertised capabilities */131#define CORESIGHT_SOC_600_ETR_CAPS \132 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)133 134enum etr_mode {135 ETR_MODE_FLAT, /* Uses contiguous flat buffer */136 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */137 ETR_MODE_CATU, /* Use SG mechanism in CATU */138 ETR_MODE_AUTO, /* Use the default mechanism */139};140 141struct etr_buf_operations;142 143/**144 * struct etr_buf - Details of the buffer used by ETR145 * refcount ; Number of sources currently using this etr_buf.146 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc.147 * @full : Trace data overflow148 * @size : Size of the buffer.149 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI}150 * @offset : Offset of the trace data in the buffer for consumption.151 * @len : Available trace data @buf (may round up to the beginning).152 * @ops : ETR buffer operations for the mode.153 * @private : Backend specific information for the buf154 */155struct etr_buf {156 refcount_t refcount;157 enum etr_mode mode;158 bool full;159 ssize_t size;160 dma_addr_t hwaddr;161 unsigned long offset;162 s64 len;163 const struct etr_buf_operations *ops;164 void *private;165};166 167/**168 * struct tmc_drvdata - specifics associated to an TMC component169 * @pclk: APB clock if present, otherwise NULL170 * @base: memory mapped base address for this component.171 * @csdev: component vitals needed by the framework.172 * @miscdev: specifics to handle "/dev/xyz.tmc" entry.173 * @spinlock: only one at a time pls.174 * @pid: Process ID of the process that owns the session that is using175 * this component. For example this would be the pid of the Perf176 * process.177 * @buf: Snapshot of the trace data for ETF/ETB.178 * @etr_buf: details of buffer used in TMC-ETR179 * @len: size of the available trace for ETF/ETB.180 * @size: trace buffer size for this TMC (common for all modes).181 * @max_burst_size: The maximum burst size that can be initiated by182 * TMC-ETR on AXI bus.183 * @config_type: TMC variant, must be of type @tmc_config_type.184 * @memwidth: width of the memory interface databus, in bytes.185 * @trigger_cntr: amount of words to store after a trigger.186 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the187 * device configuration register (DEVID)188 * @idr: Holds etr_bufs allocated for this ETR.189 * @idr_mutex: Access serialisation for idr.190 * @sysfs_buf: SYSFS buffer for ETR.191 * @perf_buf: PERF buffer for ETR.192 */193struct tmc_drvdata {194 struct clk *pclk;195 void __iomem *base;196 struct coresight_device *csdev;197 struct miscdevice miscdev;198 spinlock_t spinlock;199 pid_t pid;200 bool reading;201 union {202 char *buf; /* TMC ETB */203 struct etr_buf *etr_buf; /* TMC ETR */204 };205 u32 len;206 u32 size;207 u32 max_burst_size;208 enum tmc_config_type config_type;209 enum tmc_mem_intf_width memwidth;210 u32 trigger_cntr;211 u32 etr_caps;212 enum etr_mode etr_mode;213 struct idr idr;214 struct mutex idr_mutex;215 struct etr_buf *sysfs_buf;216 struct etr_buf *perf_buf;217};218 219struct etr_buf_operations {220 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf,221 int node, void **pages);222 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp);223 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len,224 char **bufpp);225 void (*free)(struct etr_buf *etr_buf);226};227 228/**229 * struct tmc_pages - Collection of pages used for SG.230 * @nr_pages: Number of pages in the list.231 * @daddrs: Array of DMA'able page address.232 * @pages: Array pages for the buffer.233 */234struct tmc_pages {235 int nr_pages;236 dma_addr_t *daddrs;237 struct page **pages;238};239 240/*241 * struct tmc_sg_table - Generic SG table for TMC242 * @dev: Device for DMA allocations243 * @table_vaddr: Contiguous Virtual address for PageTable244 * @data_vaddr: Contiguous Virtual address for Data Buffer245 * @table_daddr: DMA address of the PageTable base246 * @node: Node for Page allocations247 * @table_pages: List of pages & dma address for Table248 * @data_pages: List of pages & dma address for Data249 */250struct tmc_sg_table {251 struct device *dev;252 void *table_vaddr;253 void *data_vaddr;254 dma_addr_t table_daddr;255 int node;256 struct tmc_pages table_pages;257 struct tmc_pages data_pages;258};259 260/* Generic functions */261int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);262void tmc_flush_and_stop(struct tmc_drvdata *drvdata);263void tmc_enable_hw(struct tmc_drvdata *drvdata);264void tmc_disable_hw(struct tmc_drvdata *drvdata);265u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);266 267/* ETB/ETF functions */268int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);269int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);270extern const struct coresight_ops tmc_etb_cs_ops;271extern const struct coresight_ops tmc_etf_cs_ops;272 273ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata,274 loff_t pos, size_t len, char **bufpp);275/* ETR functions */276int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);277int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);278void tmc_etr_disable_hw(struct tmc_drvdata *drvdata);279extern const struct coresight_ops tmc_etr_cs_ops;280ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,281 loff_t pos, size_t len, char **bufpp);282 283 284#define TMC_REG_PAIR(name, lo_off, hi_off) \285static inline u64 \286tmc_read_##name(struct tmc_drvdata *drvdata) \287{ \288 return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \289} \290static inline void \291tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \292{ \293 csdev_access_relaxed_write_pair(&drvdata->csdev->access, val, lo_off, hi_off); \294}295 296TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)297TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)298TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)299 300/* Initialise the caps from unadvertised static capabilities of the device */301static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps)302{303 WARN_ON(drvdata->etr_caps);304 drvdata->etr_caps = dev_caps;305}306 307static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap)308{309 drvdata->etr_caps |= cap;310}311 312static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)313{314 return !!(drvdata->etr_caps & cap);315}316 317struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev,318 int node,319 int nr_tpages,320 int nr_dpages,321 void **pages);322void tmc_free_sg_table(struct tmc_sg_table *sg_table);323void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table);324void tmc_sg_table_sync_data_range(struct tmc_sg_table *table,325 u64 offset, u64 size);326ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table,327 u64 offset, size_t len, char **bufpp);328static inline unsigned long329tmc_sg_table_buf_size(struct tmc_sg_table *sg_table)330{331 return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT;332}333 334struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);335 336void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);337void tmc_etr_remove_catu_ops(void);338struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,339 enum cs_mode mode, void *data);340extern const struct attribute_group coresight_etr_group;341 342#endif343