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1// SPDX-License-Identifier: GPL-2.0-only2// Copyright (C) 2014 Broadcom Corporation3 4#include <linux/delay.h>5#include <linux/i2c.h>6#include <linux/interrupt.h>7#include <linux/io.h>8#include <linux/kernel.h>9#include <linux/module.h>10#include <linux/of.h>11#include <linux/platform_device.h>12#include <linux/slab.h>13 14#define IDM_CTRL_DIRECT_OFFSET 0x0015#define CFG_OFFSET 0x0016#define CFG_RESET_SHIFT 3117#define CFG_EN_SHIFT 3018#define CFG_SLAVE_ADDR_0_SHIFT 2819#define CFG_M_RETRY_CNT_SHIFT 1620#define CFG_M_RETRY_CNT_MASK 0x0f21 22#define TIM_CFG_OFFSET 0x0423#define TIM_CFG_MODE_400_SHIFT 3124#define TIM_RAND_SLAVE_STRETCH_SHIFT 2425#define TIM_RAND_SLAVE_STRETCH_MASK 0x7f26#define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 1627#define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f28 29#define S_CFG_SMBUS_ADDR_OFFSET 0x0830#define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 3131#define S_CFG_NIC_SMB_ADDR3_SHIFT 2432#define S_CFG_NIC_SMB_ADDR3_MASK 0x7f33#define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 2334#define S_CFG_NIC_SMB_ADDR2_SHIFT 1635#define S_CFG_NIC_SMB_ADDR2_MASK 0x7f36#define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 1537#define S_CFG_NIC_SMB_ADDR1_SHIFT 838#define S_CFG_NIC_SMB_ADDR1_MASK 0x7f39#define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 740#define S_CFG_NIC_SMB_ADDR0_SHIFT 041#define S_CFG_NIC_SMB_ADDR0_MASK 0x7f42 43#define M_FIFO_CTRL_OFFSET 0x0c44#define M_FIFO_RX_FLUSH_SHIFT 3145#define M_FIFO_TX_FLUSH_SHIFT 3046#define M_FIFO_RX_CNT_SHIFT 1647#define M_FIFO_RX_CNT_MASK 0x7f48#define M_FIFO_RX_THLD_SHIFT 849#define M_FIFO_RX_THLD_MASK 0x3f50 51#define S_FIFO_CTRL_OFFSET 0x1052#define S_FIFO_RX_FLUSH_SHIFT 3153#define S_FIFO_TX_FLUSH_SHIFT 3054#define S_FIFO_RX_CNT_SHIFT 1655#define S_FIFO_RX_CNT_MASK 0x7f56#define S_FIFO_RX_THLD_SHIFT 857#define S_FIFO_RX_THLD_MASK 0x3f58 59#define M_CMD_OFFSET 0x3060#define M_CMD_START_BUSY_SHIFT 3161#define M_CMD_STATUS_SHIFT 2562#define M_CMD_STATUS_MASK 0x0763#define M_CMD_STATUS_SUCCESS 0x064#define M_CMD_STATUS_LOST_ARB 0x165#define M_CMD_STATUS_NACK_ADDR 0x266#define M_CMD_STATUS_NACK_DATA 0x367#define M_CMD_STATUS_TIMEOUT 0x468#define M_CMD_STATUS_FIFO_UNDERRUN 0x569#define M_CMD_STATUS_RX_FIFO_FULL 0x670#define M_CMD_PROTOCOL_SHIFT 971#define M_CMD_PROTOCOL_MASK 0xf72#define M_CMD_PROTOCOL_QUICK 0x073#define M_CMD_PROTOCOL_BLK_WR 0x774#define M_CMD_PROTOCOL_BLK_RD 0x875#define M_CMD_PROTOCOL_PROCESS 0xa76#define M_CMD_PEC_SHIFT 877#define M_CMD_RD_CNT_SHIFT 078#define M_CMD_RD_CNT_MASK 0xff79 80#define S_CMD_OFFSET 0x3481#define S_CMD_START_BUSY_SHIFT 3182#define S_CMD_STATUS_SHIFT 2383#define S_CMD_STATUS_MASK 0x0784#define S_CMD_STATUS_SUCCESS 0x085#define S_CMD_STATUS_TIMEOUT 0x586#define S_CMD_STATUS_MASTER_ABORT 0x787 88#define IE_OFFSET 0x3889#define IE_M_RX_FIFO_FULL_SHIFT 3190#define IE_M_RX_THLD_SHIFT 3091#define IE_M_START_BUSY_SHIFT 2892#define IE_M_TX_UNDERRUN_SHIFT 2793#define IE_S_RX_FIFO_FULL_SHIFT 2694#define IE_S_RX_THLD_SHIFT 2595#define IE_S_RX_EVENT_SHIFT 2496#define IE_S_START_BUSY_SHIFT 2397#define IE_S_TX_UNDERRUN_SHIFT 2298#define IE_S_RD_EVENT_SHIFT 2199 100#define IS_OFFSET 0x3c101#define IS_M_RX_FIFO_FULL_SHIFT 31102#define IS_M_RX_THLD_SHIFT 30103#define IS_M_START_BUSY_SHIFT 28104#define IS_M_TX_UNDERRUN_SHIFT 27105#define IS_S_RX_FIFO_FULL_SHIFT 26106#define IS_S_RX_THLD_SHIFT 25107#define IS_S_RX_EVENT_SHIFT 24108#define IS_S_START_BUSY_SHIFT 23109#define IS_S_TX_UNDERRUN_SHIFT 22110#define IS_S_RD_EVENT_SHIFT 21111 112#define M_TX_OFFSET 0x40113#define M_TX_WR_STATUS_SHIFT 31114#define M_TX_DATA_SHIFT 0115#define M_TX_DATA_MASK 0xff116 117#define M_RX_OFFSET 0x44118#define M_RX_STATUS_SHIFT 30119#define M_RX_STATUS_MASK 0x03120#define M_RX_PEC_ERR_SHIFT 29121#define M_RX_DATA_SHIFT 0122#define M_RX_DATA_MASK 0xff123 124#define S_TX_OFFSET 0x48125#define S_TX_WR_STATUS_SHIFT 31126#define S_TX_DATA_SHIFT 0127#define S_TX_DATA_MASK 0xff128 129#define S_RX_OFFSET 0x4c130#define S_RX_STATUS_SHIFT 30131#define S_RX_STATUS_MASK 0x03132#define S_RX_PEC_ERR_SHIFT 29133#define S_RX_DATA_SHIFT 0134#define S_RX_DATA_MASK 0xff135 136#define I2C_TIMEOUT_MSEC 50000137#define M_TX_RX_FIFO_SIZE 64138#define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)139 140#define M_RX_MAX_READ_LEN 255141#define M_RX_FIFO_THLD_VALUE 50142 143#define IE_M_ALL_INTERRUPT_SHIFT 27144#define IE_M_ALL_INTERRUPT_MASK 0x1e145 146#define SLAVE_READ_WRITE_BIT_MASK 0x1147#define SLAVE_READ_WRITE_BIT_SHIFT 0x1148#define SLAVE_MAX_SIZE_TRANSACTION 64149#define SLAVE_CLOCK_STRETCH_TIME 25150 151#define IE_S_ALL_INTERRUPT_SHIFT 21152#define IE_S_ALL_INTERRUPT_MASK 0x3f153/*154 * It takes ~18us to reading 10bytes of data, hence to keep tasklet155 * running for less time, max slave read per tasklet is set to 10 bytes.156 */157#define MAX_SLAVE_RX_PER_INT 10158 159enum i2c_slave_read_status {160 I2C_SLAVE_RX_FIFO_EMPTY = 0,161 I2C_SLAVE_RX_START,162 I2C_SLAVE_RX_DATA,163 I2C_SLAVE_RX_END,164};165 166enum bus_speed_index {167 I2C_SPD_100K = 0,168 I2C_SPD_400K,169};170 171enum bcm_iproc_i2c_type {172 IPROC_I2C,173 IPROC_I2C_NIC174};175 176struct bcm_iproc_i2c_dev {177 struct device *device;178 enum bcm_iproc_i2c_type type;179 int irq;180 181 void __iomem *base;182 void __iomem *idm_base;183 184 u32 ape_addr_mask;185 186 /* lock for indirect access through IDM */187 spinlock_t idm_lock;188 189 struct i2c_adapter adapter;190 unsigned int bus_speed;191 192 struct completion done;193 int xfer_is_done;194 195 struct i2c_msg *msg;196 197 struct i2c_client *slave;198 199 /* bytes that have been transferred */200 unsigned int tx_bytes;201 /* bytes that have been read */202 unsigned int rx_bytes;203 unsigned int thld_bytes;204 205 bool slave_rx_only;206 bool rx_start_rcvd;207 bool slave_read_complete;208 u32 tx_underrun;209 u32 slave_int_mask;210 struct tasklet_struct slave_rx_tasklet;211};212 213/* tasklet to process slave rx data */214static void slave_rx_tasklet_fn(unsigned long);215 216/*217 * Can be expanded in the future if more interrupt status bits are utilized218 */219#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\220 | BIT(IS_M_RX_THLD_SHIFT))221 222#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\223 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\224 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\225 | BIT(IS_S_RX_THLD_SHIFT))226 227static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);228static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);229static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,230 bool enable);231 232static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,233 u32 offset)234{235 u32 val;236 unsigned long flags;237 238 if (iproc_i2c->idm_base) {239 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);240 writel(iproc_i2c->ape_addr_mask,241 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);242 val = readl(iproc_i2c->base + offset);243 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags);244 } else {245 val = readl(iproc_i2c->base + offset);246 }247 248 return val;249}250 251static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,252 u32 offset, u32 val)253{254 unsigned long flags;255 256 if (iproc_i2c->idm_base) {257 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);258 writel(iproc_i2c->ape_addr_mask,259 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);260 writel(val, iproc_i2c->base + offset);261 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags);262 } else {263 writel(val, iproc_i2c->base + offset);264 }265}266 267static void bcm_iproc_i2c_slave_init(268 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)269{270 u32 val;271 272 iproc_i2c->tx_underrun = 0;273 if (need_reset) {274 /* put controller in reset */275 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);276 val |= BIT(CFG_RESET_SHIFT);277 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);278 279 /* wait 100 usec per spec */280 udelay(100);281 282 /* bring controller out of reset */283 val &= ~(BIT(CFG_RESET_SHIFT));284 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);285 }286 287 /* flush TX/RX FIFOs */288 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));289 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);290 291 /* Maximum slave stretch time */292 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);293 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);294 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);295 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);296 297 /* Configure the slave address */298 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);299 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);300 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);301 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);302 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);303 304 /* clear all pending slave interrupts */305 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);306 307 /* Enable interrupt register to indicate a valid byte in receive fifo */308 val = BIT(IE_S_RX_EVENT_SHIFT);309 /* Enable interrupt register to indicate Slave Rx FIFO Full */310 val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);311 /* Enable interrupt register to indicate a Master read transaction */312 val |= BIT(IE_S_RD_EVENT_SHIFT);313 /* Enable interrupt register for the Slave BUSY command */314 val |= BIT(IE_S_START_BUSY_SHIFT);315 iproc_i2c->slave_int_mask = val;316 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);317}318 319static bool bcm_iproc_i2c_check_slave_status320 (struct bcm_iproc_i2c_dev *iproc_i2c, u32 status)321{322 u32 val;323 bool recover = false;324 325 /* check slave transmit status only if slave is transmitting */326 if (!iproc_i2c->slave_rx_only) {327 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);328 /* status is valid only when START_BUSY is cleared */329 if (!(val & BIT(S_CMD_START_BUSY_SHIFT))) {330 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;331 if (val == S_CMD_STATUS_TIMEOUT ||332 val == S_CMD_STATUS_MASTER_ABORT) {333 dev_warn(iproc_i2c->device,334 (val == S_CMD_STATUS_TIMEOUT) ?335 "slave random stretch time timeout\n" :336 "Master aborted read transaction\n");337 recover = true;338 }339 }340 }341 342 /* RX_EVENT is not valid when START_BUSY is set */343 if ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&344 (status & BIT(IS_S_START_BUSY_SHIFT))) {345 dev_warn(iproc_i2c->device, "Slave aborted read transaction\n");346 recover = true;347 }348 349 if (recover) {350 /* re-initialize i2c for recovery */351 bcm_iproc_i2c_enable_disable(iproc_i2c, false);352 bcm_iproc_i2c_slave_init(iproc_i2c, true);353 bcm_iproc_i2c_enable_disable(iproc_i2c, true);354 }355 356 return recover;357}358 359static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)360{361 u8 rx_data, rx_status;362 u32 rx_bytes = 0;363 u32 val;364 365 while (rx_bytes < MAX_SLAVE_RX_PER_INT) {366 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);367 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;368 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);369 370 if (rx_status == I2C_SLAVE_RX_START) {371 /* Start of SMBUS Master write */372 i2c_slave_event(iproc_i2c->slave,373 I2C_SLAVE_WRITE_REQUESTED, &rx_data);374 iproc_i2c->rx_start_rcvd = true;375 iproc_i2c->slave_read_complete = false;376 } else if (rx_status == I2C_SLAVE_RX_DATA &&377 iproc_i2c->rx_start_rcvd) {378 /* Middle of SMBUS Master write */379 i2c_slave_event(iproc_i2c->slave,380 I2C_SLAVE_WRITE_RECEIVED, &rx_data);381 } else if (rx_status == I2C_SLAVE_RX_END &&382 iproc_i2c->rx_start_rcvd) {383 /* End of SMBUS Master write */384 if (iproc_i2c->slave_rx_only)385 i2c_slave_event(iproc_i2c->slave,386 I2C_SLAVE_WRITE_RECEIVED,387 &rx_data);388 389 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,390 &rx_data);391 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {392 iproc_i2c->rx_start_rcvd = false;393 iproc_i2c->slave_read_complete = true;394 break;395 }396 397 rx_bytes++;398 }399}400 401static void slave_rx_tasklet_fn(unsigned long data)402{403 struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;404 u32 int_clr;405 406 bcm_iproc_i2c_slave_read(iproc_i2c);407 408 /* clear pending IS_S_RX_EVENT_SHIFT interrupt */409 int_clr = BIT(IS_S_RX_EVENT_SHIFT);410 411 if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {412 /*413 * In case of single byte master-read request,414 * IS_S_TX_UNDERRUN_SHIFT event is generated before415 * IS_S_START_BUSY_SHIFT event. Hence start slave data send416 * from first IS_S_TX_UNDERRUN_SHIFT event.417 *418 * This means don't send any data from slave when419 * IS_S_RD_EVENT_SHIFT event is generated else it will increment420 * eeprom or other backend slave driver read pointer twice.421 */422 iproc_i2c->tx_underrun = 0;423 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);424 425 /* clear IS_S_RD_EVENT_SHIFT interrupt */426 int_clr |= BIT(IS_S_RD_EVENT_SHIFT);427 }428 429 /* clear slave interrupt */430 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);431 /* enable slave interrupts */432 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);433}434 435static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,436 u32 status)437{438 u32 val;439 u8 value;440 441 442 if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {443 iproc_i2c->tx_underrun++;444 if (iproc_i2c->tx_underrun == 1)445 /* Start of SMBUS for Master Read */446 i2c_slave_event(iproc_i2c->slave,447 I2C_SLAVE_READ_REQUESTED,448 &value);449 else450 /* Master read other than start */451 i2c_slave_event(iproc_i2c->slave,452 I2C_SLAVE_READ_PROCESSED,453 &value);454 455 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);456 /* start transfer */457 val = BIT(S_CMD_START_BUSY_SHIFT);458 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);459 460 /* clear interrupt */461 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,462 BIT(IS_S_TX_UNDERRUN_SHIFT));463 }464 465 /* Stop received from master in case of master read transaction */466 if (status & BIT(IS_S_START_BUSY_SHIFT)) {467 /*468 * Disable interrupt for TX FIFO becomes empty and469 * less than PKT_LENGTH bytes were output on the SMBUS470 */471 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);472 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);473 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);474 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);475 476 /* End of SMBUS for Master Read */477 val = BIT(S_TX_WR_STATUS_SHIFT);478 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);479 480 val = BIT(S_CMD_START_BUSY_SHIFT);481 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);482 483 /* flush TX FIFOs */484 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);485 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));486 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);487 488 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);489 490 /* clear interrupt */491 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,492 BIT(IS_S_START_BUSY_SHIFT));493 }494 495 /* if the controller has been reset, immediately return from the ISR */496 if (bcm_iproc_i2c_check_slave_status(iproc_i2c, status))497 return true;498 499 /*500 * Slave events in case of master-write, master-write-read and,501 * master-read502 *503 * Master-write : only IS_S_RX_EVENT_SHIFT event504 * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT505 * events506 * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT507 * events or only IS_S_RD_EVENT_SHIFT508 *509 * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt510 * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes511 * full. This can happen if Master issues write requests of more than512 * 64 bytes.513 */514 if (status & BIT(IS_S_RX_EVENT_SHIFT) ||515 status & BIT(IS_S_RD_EVENT_SHIFT) ||516 status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {517 /* disable slave interrupts */518 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);519 val &= ~iproc_i2c->slave_int_mask;520 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);521 522 if (status & BIT(IS_S_RD_EVENT_SHIFT))523 /* Master-write-read request */524 iproc_i2c->slave_rx_only = false;525 else526 /* Master-write request only */527 iproc_i2c->slave_rx_only = true;528 529 /* schedule tasklet to read data later */530 tasklet_schedule(&iproc_i2c->slave_rx_tasklet);531 532 /* clear IS_S_RX_FIFO_FULL_SHIFT interrupt */533 if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {534 val = BIT(IS_S_RX_FIFO_FULL_SHIFT);535 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val);536 }537 }538 539 return true;540}541 542static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)543{544 struct i2c_msg *msg = iproc_i2c->msg;545 uint32_t val;546 547 /* Read valid data from RX FIFO */548 while (iproc_i2c->rx_bytes < msg->len) {549 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);550 551 /* rx fifo empty */552 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))553 break;554 555 msg->buf[iproc_i2c->rx_bytes] =556 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;557 iproc_i2c->rx_bytes++;558 }559}560 561static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)562{563 struct i2c_msg *msg = iproc_i2c->msg;564 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;565 unsigned int i;566 u32 val;567 568 /* can only fill up to the FIFO size */569 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);570 for (i = 0; i < tx_bytes; i++) {571 /* start from where we left over */572 unsigned int idx = iproc_i2c->tx_bytes + i;573 574 val = msg->buf[idx];575 576 /* mark the last byte */577 if (idx == msg->len - 1) {578 val |= BIT(M_TX_WR_STATUS_SHIFT);579 580 if (iproc_i2c->irq) {581 u32 tmp;582 583 /*584 * Since this is the last byte, we should now585 * disable TX FIFO underrun interrupt586 */587 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);588 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);589 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,590 tmp);591 }592 }593 594 /* load data into TX FIFO */595 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);596 }597 598 /* update number of transferred bytes */599 iproc_i2c->tx_bytes += tx_bytes;600}601 602static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)603{604 struct i2c_msg *msg = iproc_i2c->msg;605 u32 bytes_left, val;606 607 bcm_iproc_i2c_read_valid_bytes(iproc_i2c);608 bytes_left = msg->len - iproc_i2c->rx_bytes;609 if (bytes_left == 0) {610 if (iproc_i2c->irq) {611 /* finished reading all data, disable rx thld event */612 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);613 val &= ~BIT(IS_M_RX_THLD_SHIFT);614 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);615 }616 } else if (bytes_left < iproc_i2c->thld_bytes) {617 /* set bytes left as threshold */618 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);619 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);620 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);621 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);622 iproc_i2c->thld_bytes = bytes_left;623 }624 /*625 * bytes_left >= iproc_i2c->thld_bytes,626 * hence no need to change the THRESHOLD SET.627 * It will remain as iproc_i2c->thld_bytes itself628 */629}630 631static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,632 u32 status)633{634 /* TX FIFO is empty and we have more data to send */635 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))636 bcm_iproc_i2c_send(iproc_i2c);637 638 /* RX FIFO threshold is reached and data needs to be read out */639 if (status & BIT(IS_M_RX_THLD_SHIFT))640 bcm_iproc_i2c_read(iproc_i2c);641 642 /* transfer is done */643 if (status & BIT(IS_M_START_BUSY_SHIFT)) {644 iproc_i2c->xfer_is_done = 1;645 if (iproc_i2c->irq)646 complete(&iproc_i2c->done);647 }648}649 650static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)651{652 struct bcm_iproc_i2c_dev *iproc_i2c = data;653 u32 slave_status;654 u32 status;655 bool ret;656 657 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);658 /* process only slave interrupt which are enabled */659 slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &660 ISR_MASK_SLAVE;661 662 if (slave_status) {663 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);664 if (ret)665 return IRQ_HANDLED;666 else667 return IRQ_NONE;668 }669 670 status &= ISR_MASK;671 if (!status)672 return IRQ_NONE;673 674 /* process all master based events */675 bcm_iproc_i2c_process_m_event(iproc_i2c, status);676 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);677 678 return IRQ_HANDLED;679}680 681static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)682{683 u32 val;684 685 /* put controller in reset */686 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);687 val |= BIT(CFG_RESET_SHIFT);688 val &= ~(BIT(CFG_EN_SHIFT));689 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);690 691 /* wait 100 usec per spec */692 udelay(100);693 694 /* bring controller out of reset */695 val &= ~(BIT(CFG_RESET_SHIFT));696 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);697 698 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */699 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));700 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);701 /* disable all interrupts */702 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);703 val &= ~(IE_M_ALL_INTERRUPT_MASK <<704 IE_M_ALL_INTERRUPT_SHIFT);705 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);706 707 /* clear all pending interrupts */708 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);709 710 return 0;711}712 713static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,714 bool enable)715{716 u32 val;717 718 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);719 if (enable)720 val |= BIT(CFG_EN_SHIFT);721 else722 val &= ~BIT(CFG_EN_SHIFT);723 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);724}725 726static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,727 struct i2c_msg *msg)728{729 u32 val;730 731 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);732 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;733 734 switch (val) {735 case M_CMD_STATUS_SUCCESS:736 return 0;737 738 case M_CMD_STATUS_LOST_ARB:739 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");740 return -EAGAIN;741 742 case M_CMD_STATUS_NACK_ADDR:743 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);744 return -ENXIO;745 746 case M_CMD_STATUS_NACK_DATA:747 dev_dbg(iproc_i2c->device, "NAK data\n");748 return -ENXIO;749 750 case M_CMD_STATUS_TIMEOUT:751 dev_dbg(iproc_i2c->device, "bus timeout\n");752 return -ETIMEDOUT;753 754 case M_CMD_STATUS_FIFO_UNDERRUN:755 dev_dbg(iproc_i2c->device, "FIFO under-run\n");756 return -ENXIO;757 758 case M_CMD_STATUS_RX_FIFO_FULL:759 dev_dbg(iproc_i2c->device, "RX FIFO full\n");760 return -ETIMEDOUT;761 762 default:763 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);764 765 /* re-initialize i2c for recovery */766 bcm_iproc_i2c_enable_disable(iproc_i2c, false);767 bcm_iproc_i2c_init(iproc_i2c);768 bcm_iproc_i2c_enable_disable(iproc_i2c, true);769 770 return -EIO;771 }772}773 774static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,775 struct i2c_msg *msg,776 u32 cmd)777{778 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);779 u32 val, status;780 int ret;781 782 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);783 784 if (iproc_i2c->irq) {785 time_left = wait_for_completion_timeout(&iproc_i2c->done,786 time_left);787 /* disable all interrupts */788 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);789 /* read it back to flush the write */790 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);791 /* make sure the interrupt handler isn't running */792 synchronize_irq(iproc_i2c->irq);793 794 } else { /* polling mode */795 unsigned long timeout = jiffies + time_left;796 797 do {798 status = iproc_i2c_rd_reg(iproc_i2c,799 IS_OFFSET) & ISR_MASK;800 bcm_iproc_i2c_process_m_event(iproc_i2c, status);801 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);802 803 if (time_after(jiffies, timeout)) {804 time_left = 0;805 break;806 }807 808 cpu_relax();809 cond_resched();810 } while (!iproc_i2c->xfer_is_done);811 }812 813 if (!time_left && !iproc_i2c->xfer_is_done) {814 /* flush both TX/RX FIFOs */815 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);816 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);817 return -ETIMEDOUT;818 }819 820 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);821 if (ret) {822 /* flush both TX/RX FIFOs */823 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);824 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);825 return ret;826 }827 828 return 0;829}830 831/*832 * If 'process_call' is true, then this is a multi-msg transfer that requires833 * a repeated start between the messages.834 * More specifically, it must be a write (reg) followed by a read (data).835 * The i2c quirks are set to enforce this rule.836 */837static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,838 struct i2c_msg *msgs, bool process_call)839{840 int i;841 u8 addr;842 u32 val, tmp, val_intr_en;843 unsigned int tx_bytes;844 struct i2c_msg *msg = &msgs[0];845 846 /* check if bus is busy */847 if (!!(iproc_i2c_rd_reg(iproc_i2c,848 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {849 dev_warn(iproc_i2c->device, "bus is busy\n");850 return -EBUSY;851 }852 853 iproc_i2c->msg = msg;854 855 /* format and load slave address into the TX FIFO */856 addr = i2c_8bit_addr_from_msg(msg);857 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);858 859 /*860 * For a write transaction, load data into the TX FIFO. Only allow861 * loading up to TX FIFO size - 1 bytes of data since the first byte862 * has been used up by the slave address863 */864 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);865 if (!(msg->flags & I2C_M_RD)) {866 for (i = 0; i < tx_bytes; i++) {867 val = msg->buf[i];868 869 /* mark the last byte */870 if (!process_call && (i == msg->len - 1))871 val |= BIT(M_TX_WR_STATUS_SHIFT);872 873 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);874 }875 iproc_i2c->tx_bytes = tx_bytes;876 }877 878 /* Process the read message if this is process call */879 if (process_call) {880 msg++;881 iproc_i2c->msg = msg; /* point to second msg */882 883 /*884 * The last byte to be sent out should be a slave885 * address with read operation886 */887 addr = i2c_8bit_addr_from_msg(msg);888 /* mark it the last byte out */889 val = addr | BIT(M_TX_WR_STATUS_SHIFT);890 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);891 }892 893 /* mark as incomplete before starting the transaction */894 if (iproc_i2c->irq)895 reinit_completion(&iproc_i2c->done);896 897 iproc_i2c->xfer_is_done = 0;898 899 /*900 * Enable the "start busy" interrupt, which will be triggered after the901 * transaction is done, i.e., the internal start_busy bit, transitions902 * from 1 to 0.903 */904 val_intr_en = BIT(IE_M_START_BUSY_SHIFT);905 906 /*907 * If TX data size is larger than the TX FIFO, need to enable TX908 * underrun interrupt, which will be triggerred when the TX FIFO is909 * empty. When that happens we can then pump more data into the FIFO910 */911 if (!process_call && !(msg->flags & I2C_M_RD) &&912 msg->len > iproc_i2c->tx_bytes)913 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);914 915 /*916 * Now we can activate the transfer. For a read operation, specify the917 * number of bytes to read918 */919 val = BIT(M_CMD_START_BUSY_SHIFT);920 921 if (msg->len == 0) {922 /* SMBUS QUICK Command (Read/Write) */923 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);924 } else if (msg->flags & I2C_M_RD) {925 u32 protocol;926 927 iproc_i2c->rx_bytes = 0;928 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)929 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;930 else931 iproc_i2c->thld_bytes = msg->len;932 933 /* set threshold value */934 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);935 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);936 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;937 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);938 939 /* enable the RX threshold interrupt */940 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);941 942 protocol = process_call ?943 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;944 945 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |946 (msg->len << M_CMD_RD_CNT_SHIFT);947 } else {948 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);949 }950 951 if (iproc_i2c->irq)952 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);953 954 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);955}956 957static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,958 struct i2c_msg msgs[], int num)959{960 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);961 bool process_call = false;962 int ret;963 964 if (num == 2) {965 /* Repeated start, use process call */966 process_call = true;967 if (msgs[1].flags & I2C_M_NOSTART) {968 dev_err(iproc_i2c->device, "Invalid repeated start\n");969 return -EOPNOTSUPP;970 }971 }972 973 ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);974 if (ret) {975 dev_dbg(iproc_i2c->device, "xfer failed\n");976 return ret;977 }978 979 return num;980}981 982static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)983{984 u32 val;985 986 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;987 988 if (adap->algo->reg_slave)989 val |= I2C_FUNC_SLAVE;990 991 return val;992}993 994static struct i2c_algorithm bcm_iproc_algo = {995 .master_xfer = bcm_iproc_i2c_xfer,996 .functionality = bcm_iproc_i2c_functionality,997 .reg_slave = bcm_iproc_i2c_reg_slave,998 .unreg_slave = bcm_iproc_i2c_unreg_slave,999};1000 1001static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {1002 .flags = I2C_AQ_COMB_WRITE_THEN_READ,1003 .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,1004 .max_read_len = M_RX_MAX_READ_LEN,1005};1006 1007static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)1008{1009 unsigned int bus_speed;1010 u32 val;1011 int ret = of_property_read_u32(iproc_i2c->device->of_node,1012 "clock-frequency", &bus_speed);1013 if (ret < 0) {1014 dev_info(iproc_i2c->device,1015 "unable to interpret clock-frequency DT property\n");1016 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;1017 }1018 1019 if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {1020 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",1021 bus_speed);1022 dev_err(iproc_i2c->device,1023 "valid speeds are 100khz and 400khz\n");1024 return -EINVAL;1025 } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {1026 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;1027 } else {1028 bus_speed = I2C_MAX_FAST_MODE_FREQ;1029 }1030 1031 iproc_i2c->bus_speed = bus_speed;1032 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);1033 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);1034 val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;1035 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);1036 1037 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);1038 1039 return 0;1040}1041 1042static int bcm_iproc_i2c_probe(struct platform_device *pdev)1043{1044 int irq, ret = 0;1045 struct bcm_iproc_i2c_dev *iproc_i2c;1046 struct i2c_adapter *adap;1047 1048 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),1049 GFP_KERNEL);1050 if (!iproc_i2c)1051 return -ENOMEM;1052 1053 platform_set_drvdata(pdev, iproc_i2c);1054 iproc_i2c->device = &pdev->dev;1055 iproc_i2c->type =1056 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);1057 init_completion(&iproc_i2c->done);1058 1059 iproc_i2c->base = devm_platform_ioremap_resource(pdev, 0);1060 if (IS_ERR(iproc_i2c->base))1061 return PTR_ERR(iproc_i2c->base);1062 1063 if (iproc_i2c->type == IPROC_I2C_NIC) {1064 iproc_i2c->idm_base = devm_platform_ioremap_resource(pdev, 1);1065 if (IS_ERR(iproc_i2c->idm_base))1066 return PTR_ERR(iproc_i2c->idm_base);1067 1068 ret = of_property_read_u32(iproc_i2c->device->of_node,1069 "brcm,ape-hsls-addr-mask",1070 &iproc_i2c->ape_addr_mask);1071 if (ret < 0) {1072 dev_err(iproc_i2c->device,1073 "'brcm,ape-hsls-addr-mask' missing\n");1074 return -EINVAL;1075 }1076 1077 spin_lock_init(&iproc_i2c->idm_lock);1078 1079 /* no slave support */1080 bcm_iproc_algo.reg_slave = NULL;1081 bcm_iproc_algo.unreg_slave = NULL;1082 }1083 1084 ret = bcm_iproc_i2c_init(iproc_i2c);1085 if (ret)1086 return ret;1087 1088 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);1089 if (ret)1090 return ret;1091 1092 irq = platform_get_irq(pdev, 0);1093 if (irq > 0) {1094 ret = devm_request_irq(iproc_i2c->device, irq,1095 bcm_iproc_i2c_isr, 0, pdev->name,1096 iproc_i2c);1097 if (ret < 0) {1098 dev_err(iproc_i2c->device,1099 "unable to request irq %i\n", irq);1100 return ret;1101 }1102 1103 iproc_i2c->irq = irq;1104 } else {1105 dev_warn(iproc_i2c->device,1106 "no irq resource, falling back to poll mode\n");1107 }1108 1109 bcm_iproc_i2c_enable_disable(iproc_i2c, true);1110 1111 adap = &iproc_i2c->adapter;1112 i2c_set_adapdata(adap, iproc_i2c);1113 snprintf(adap->name, sizeof(adap->name),1114 "Broadcom iProc (%s)",1115 of_node_full_name(iproc_i2c->device->of_node));1116 adap->algo = &bcm_iproc_algo;1117 adap->quirks = &bcm_iproc_i2c_quirks;1118 adap->dev.parent = &pdev->dev;1119 adap->dev.of_node = pdev->dev.of_node;1120 1121 return i2c_add_adapter(adap);1122}1123 1124static void bcm_iproc_i2c_remove(struct platform_device *pdev)1125{1126 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);1127 1128 if (iproc_i2c->irq) {1129 /*1130 * Make sure there's no pending interrupt when we remove the1131 * adapter1132 */1133 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);1134 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);1135 synchronize_irq(iproc_i2c->irq);1136 }1137 1138 i2c_del_adapter(&iproc_i2c->adapter);1139 bcm_iproc_i2c_enable_disable(iproc_i2c, false);1140}1141 1142static int bcm_iproc_i2c_suspend(struct device *dev)1143{1144 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);1145 1146 if (iproc_i2c->irq) {1147 /*1148 * Make sure there's no pending interrupt when we go into1149 * suspend1150 */1151 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);1152 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);1153 synchronize_irq(iproc_i2c->irq);1154 }1155 1156 /* now disable the controller */1157 bcm_iproc_i2c_enable_disable(iproc_i2c, false);1158 1159 return 0;1160}1161 1162static int bcm_iproc_i2c_resume(struct device *dev)1163{1164 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);1165 int ret;1166 u32 val;1167 1168 /*1169 * Power domain could have been shut off completely in system deep1170 * sleep, so re-initialize the block here1171 */1172 ret = bcm_iproc_i2c_init(iproc_i2c);1173 if (ret)1174 return ret;1175 1176 /* configure to the desired bus speed */1177 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);1178 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);1179 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;1180 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);1181 1182 bcm_iproc_i2c_enable_disable(iproc_i2c, true);1183 1184 return 0;1185}1186 1187static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {1188 .suspend_late = &bcm_iproc_i2c_suspend,1189 .resume_early = &bcm_iproc_i2c_resume1190};1191 1192static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)1193{1194 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);1195 1196 if (iproc_i2c->slave)1197 return -EBUSY;1198 1199 if (slave->flags & I2C_CLIENT_TEN)1200 return -EAFNOSUPPORT;1201 1202 iproc_i2c->slave = slave;1203 1204 tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,1205 (unsigned long)iproc_i2c);1206 1207 bcm_iproc_i2c_slave_init(iproc_i2c, false);1208 return 0;1209}1210 1211static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)1212{1213 u32 tmp;1214 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);1215 1216 if (!iproc_i2c->slave)1217 return -EINVAL;1218 1219 disable_irq(iproc_i2c->irq);1220 1221 tasklet_kill(&iproc_i2c->slave_rx_tasklet);1222 1223 /* disable all slave interrupts */1224 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);1225 tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<1226 IE_S_ALL_INTERRUPT_SHIFT);1227 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);1228 1229 /* Erase the slave address programmed */1230 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);1231 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);1232 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);1233 1234 /* flush TX/RX FIFOs */1235 tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));1236 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);1237 1238 /* clear all pending slave interrupts */1239 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);1240 1241 iproc_i2c->slave = NULL;1242 1243 enable_irq(iproc_i2c->irq);1244 1245 return 0;1246}1247 1248static const struct of_device_id bcm_iproc_i2c_of_match[] = {1249 {1250 .compatible = "brcm,iproc-i2c",1251 .data = (int *)IPROC_I2C,1252 }, {1253 .compatible = "brcm,iproc-nic-i2c",1254 .data = (int *)IPROC_I2C_NIC,1255 },1256 { /* sentinel */ }1257};1258MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);1259 1260static struct platform_driver bcm_iproc_i2c_driver = {1261 .driver = {1262 .name = "bcm-iproc-i2c",1263 .of_match_table = bcm_iproc_i2c_of_match,1264 .pm = pm_sleep_ptr(&bcm_iproc_i2c_pm_ops),1265 },1266 .probe = bcm_iproc_i2c_probe,1267 .remove_new = bcm_iproc_i2c_remove,1268};1269module_platform_driver(bcm_iproc_i2c_driver);1270 1271MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");1272MODULE_DESCRIPTION("Broadcom iProc I2C Driver");1273MODULE_LICENSE("GPL v2");1274