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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver4 *5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.6*/7 8#include <linux/kernel.h>9#include <linux/module.h>10 11#include <linux/i2c.h>12#include <linux/time.h>13#include <linux/interrupt.h>14#include <linux/delay.h>15#include <linux/errno.h>16#include <linux/err.h>17#include <linux/platform_device.h>18#include <linux/clk.h>19#include <linux/slab.h>20#include <linux/io.h>21#include <linux/of.h>22#include <linux/spinlock.h>23 24/*25 * HSI2C controller from Samsung supports 2 modes of operation26 * 1. Auto mode: Where in master automatically controls the whole transaction27 * 2. Manual mode: Software controls the transaction by issuing commands28 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.29 *30 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register31 *32 * Special bits are available for both modes of operation to set commands33 * and for checking transfer status34 */35 36/* Register Map */37#define HSI2C_CTL 0x0038#define HSI2C_FIFO_CTL 0x0439#define HSI2C_TRAILIG_CTL 0x0840#define HSI2C_CLK_CTL 0x0C41#define HSI2C_CLK_SLOT 0x1042#define HSI2C_INT_ENABLE 0x2043#define HSI2C_INT_STATUS 0x2444#define HSI2C_ERR_STATUS 0x2C45#define HSI2C_FIFO_STATUS 0x3046#define HSI2C_TX_DATA 0x3447#define HSI2C_RX_DATA 0x3848#define HSI2C_CONF 0x4049#define HSI2C_AUTO_CONF 0x4450#define HSI2C_TIMEOUT 0x4851#define HSI2C_MANUAL_CMD 0x4C52#define HSI2C_TRANS_STATUS 0x5053#define HSI2C_TIMING_HS1 0x5454#define HSI2C_TIMING_HS2 0x5855#define HSI2C_TIMING_HS3 0x5C56#define HSI2C_TIMING_FS1 0x6057#define HSI2C_TIMING_FS2 0x6458#define HSI2C_TIMING_FS3 0x6859#define HSI2C_TIMING_SLA 0x6C60#define HSI2C_ADDR 0x7061 62/* I2C_CTL Register bits */63#define HSI2C_FUNC_MODE_I2C (1u << 0)64#define HSI2C_MASTER (1u << 3)65#define HSI2C_RXCHON (1u << 6)66#define HSI2C_TXCHON (1u << 7)67#define HSI2C_SW_RST (1u << 31)68 69/* I2C_FIFO_CTL Register bits */70#define HSI2C_RXFIFO_EN (1u << 0)71#define HSI2C_TXFIFO_EN (1u << 1)72#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)73#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)74 75/* I2C_TRAILING_CTL Register bits */76#define HSI2C_TRAILING_COUNT (0xf)77 78/* I2C_INT_EN Register bits */79#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)80#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)81#define HSI2C_INT_TRAILING_EN (1u << 6)82 83/* I2C_INT_STAT Register bits */84#define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)85#define HSI2C_INT_RX_ALMOSTFULL (1u << 1)86#define HSI2C_INT_TX_UNDERRUN (1u << 2)87#define HSI2C_INT_TX_OVERRUN (1u << 3)88#define HSI2C_INT_RX_UNDERRUN (1u << 4)89#define HSI2C_INT_RX_OVERRUN (1u << 5)90#define HSI2C_INT_TRAILING (1u << 6)91#define HSI2C_INT_I2C (1u << 9)92 93#define HSI2C_INT_TRANS_DONE (1u << 7)94#define HSI2C_INT_TRANS_ABORT (1u << 8)95#define HSI2C_INT_NO_DEV_ACK (1u << 9)96#define HSI2C_INT_NO_DEV (1u << 10)97#define HSI2C_INT_TIMEOUT (1u << 11)98#define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \99 HSI2C_INT_TRANS_ABORT | \100 HSI2C_INT_NO_DEV_ACK | \101 HSI2C_INT_NO_DEV | \102 HSI2C_INT_TIMEOUT)103 104/* I2C_FIFO_STAT Register bits */105#define HSI2C_RX_FIFO_EMPTY (1u << 24)106#define HSI2C_RX_FIFO_FULL (1u << 23)107#define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)108#define HSI2C_TX_FIFO_EMPTY (1u << 8)109#define HSI2C_TX_FIFO_FULL (1u << 7)110#define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)111 112/* I2C_CONF Register bits */113#define HSI2C_AUTO_MODE (1u << 31)114#define HSI2C_10BIT_ADDR_MODE (1u << 30)115#define HSI2C_HS_MODE (1u << 29)116 117/* I2C_AUTO_CONF Register bits */118#define HSI2C_READ_WRITE (1u << 16)119#define HSI2C_STOP_AFTER_TRANS (1u << 17)120#define HSI2C_MASTER_RUN (1u << 31)121 122/* I2C_TIMEOUT Register bits */123#define HSI2C_TIMEOUT_EN (1u << 31)124#define HSI2C_TIMEOUT_MASK 0xff125 126/* I2C_MANUAL_CMD register bits */127#define HSI2C_CMD_READ_DATA (1u << 4)128#define HSI2C_CMD_SEND_STOP (1u << 2)129 130/* I2C_TRANS_STATUS register bits */131#define HSI2C_MASTER_BUSY (1u << 17)132#define HSI2C_SLAVE_BUSY (1u << 16)133 134/* I2C_TRANS_STATUS register bits for Exynos5 variant */135#define HSI2C_TIMEOUT_AUTO (1u << 4)136#define HSI2C_NO_DEV (1u << 3)137#define HSI2C_NO_DEV_ACK (1u << 2)138#define HSI2C_TRANS_ABORT (1u << 1)139#define HSI2C_TRANS_DONE (1u << 0)140 141/* I2C_TRANS_STATUS register bits for Exynos7 variant */142#define HSI2C_MASTER_ST_MASK 0xf143#define HSI2C_MASTER_ST_IDLE 0x0144#define HSI2C_MASTER_ST_START 0x1145#define HSI2C_MASTER_ST_RESTART 0x2146#define HSI2C_MASTER_ST_STOP 0x3147#define HSI2C_MASTER_ST_MASTER_ID 0x4148#define HSI2C_MASTER_ST_ADDR0 0x5149#define HSI2C_MASTER_ST_ADDR1 0x6150#define HSI2C_MASTER_ST_ADDR2 0x7151#define HSI2C_MASTER_ST_ADDR_SR 0x8152#define HSI2C_MASTER_ST_READ 0x9153#define HSI2C_MASTER_ST_WRITE 0xa154#define HSI2C_MASTER_ST_NO_ACK 0xb155#define HSI2C_MASTER_ST_LOSE 0xc156#define HSI2C_MASTER_ST_WAIT 0xd157#define HSI2C_MASTER_ST_WAIT_CMD 0xe158 159/* I2C_ADDR register bits */160#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)161#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)162#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)163#define MASTER_ID(x) ((x & 0x7) + 0x08)164 165#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))166 167enum i2c_type_exynos {168 I2C_TYPE_EXYNOS5,169 I2C_TYPE_EXYNOS7,170 I2C_TYPE_EXYNOSAUTOV9,171};172 173struct exynos5_i2c {174 struct i2c_adapter adap;175 176 struct i2c_msg *msg;177 struct completion msg_complete;178 unsigned int msg_ptr;179 180 unsigned int irq;181 182 void __iomem *regs;183 struct clk *clk; /* operating clock */184 struct clk *pclk; /* bus clock */185 struct device *dev;186 int state;187 188 spinlock_t lock; /* IRQ synchronization */189 190 /*191 * Since the TRANS_DONE bit is cleared on read, and we may read it192 * either during an IRQ or after a transaction, keep track of its193 * state here.194 */195 int trans_done;196 197 /*198 * Called from atomic context, don't use interrupts.199 */200 unsigned int atomic;201 202 /* Controller operating frequency */203 unsigned int op_clock;204 205 /* Version of HS-I2C Hardware */206 const struct exynos_hsi2c_variant *variant;207};208 209/**210 * struct exynos_hsi2c_variant - platform specific HSI2C driver data211 * @fifo_depth: the fifo depth supported by the HSI2C module212 * @hw: the hardware variant of Exynos I2C controller213 *214 * Specifies platform specific configuration of HSI2C module.215 * Note: A structure for driver specific platform data is used for future216 * expansion of its usage.217 */218struct exynos_hsi2c_variant {219 unsigned int fifo_depth;220 enum i2c_type_exynos hw;221};222 223static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {224 .fifo_depth = 64,225 .hw = I2C_TYPE_EXYNOS5,226};227 228static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {229 .fifo_depth = 16,230 .hw = I2C_TYPE_EXYNOS5,231};232 233static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {234 .fifo_depth = 16,235 .hw = I2C_TYPE_EXYNOS7,236};237 238static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = {239 .fifo_depth = 64,240 .hw = I2C_TYPE_EXYNOSAUTOV9,241};242 243static const struct of_device_id exynos5_i2c_match[] = {244 {245 .compatible = "samsung,exynos5-hsi2c",246 .data = &exynos5250_hsi2c_data247 }, {248 .compatible = "samsung,exynos5250-hsi2c",249 .data = &exynos5250_hsi2c_data250 }, {251 .compatible = "samsung,exynos5260-hsi2c",252 .data = &exynos5260_hsi2c_data253 }, {254 .compatible = "samsung,exynos7-hsi2c",255 .data = &exynos7_hsi2c_data256 }, {257 .compatible = "samsung,exynosautov9-hsi2c",258 .data = &exynosautov9_hsi2c_data259 }, {},260};261MODULE_DEVICE_TABLE(of, exynos5_i2c_match);262 263static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)264{265 writel(readl(i2c->regs + HSI2C_INT_STATUS),266 i2c->regs + HSI2C_INT_STATUS);267}268 269/*270 * exynos5_i2c_set_timing: updates the registers with appropriate271 * timing values calculated272 *273 * Timing values for operation are calculated against 100kHz, 400kHz274 * or 1MHz controller operating frequency.275 *276 * Returns 0 on success, -EINVAL if the cycle length cannot277 * be calculated.278 */279static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)280{281 u32 i2c_timing_s1;282 u32 i2c_timing_s2;283 u32 i2c_timing_s3;284 u32 i2c_timing_sla;285 unsigned int t_start_su, t_start_hd;286 unsigned int t_stop_su;287 unsigned int t_data_su, t_data_hd;288 unsigned int t_scl_l, t_scl_h;289 unsigned int t_sr_release;290 unsigned int t_ftl_cycle;291 unsigned int clkin = clk_get_rate(i2c->clk);292 unsigned int op_clk = hs_timings ? i2c->op_clock :293 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :294 i2c->op_clock;295 int div, clk_cycle, temp;296 297 /*298 * In case of HSI2C controllers in ExynosAutoV9:299 *300 * FSCL = IPCLK / ((CLK_DIV + 1) * 16)301 * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M)302 * [N : number of 0's in the TSCL_H_HS]303 * [M : number of 0's in the TSCL_L_HS]304 * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M)305 * [N : number of 1's in the TSCL_H_HS]306 * [M : number of 1's in the TSCL_L_HS]307 *308 * Result of (N + M) is always 8.309 * In general case, we don't need to control timing_s1 and timing_s2.310 */311 if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) {312 div = ((clkin / (16 * i2c->op_clock)) - 1);313 i2c_timing_s3 = div << 16;314 if (hs_timings)315 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);316 else317 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);318 319 return 0;320 }321 322 /*323 * In case of HSI2C controller in Exynos5 series324 * FPCLK / FI2C =325 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE326 *327 * In case of HSI2C controllers in Exynos7 series328 * FPCLK / FI2C =329 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE330 *331 * clk_cycle := TSCLK_L + TSCLK_H332 * temp := (CLK_DIV + 1) * (clk_cycle + 2)333 *334 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510335 *336 * To split SCL clock into low, high periods appropriately, one337 * proportion factor for each I2C mode is used, which is calculated338 * using this formula.339 * ```340 * ((t_low_min + (scl_clock - t_low_min - t_high_min) / 2) / scl_clock)341 * ```342 * where:343 * t_low_min is the minimal value of low period of the SCL clock in us;344 * t_high_min is the minimal value of high period of the SCL clock in us;345 * scl_clock is converted from SCL clock frequency into us.346 *347 * Below are the proportion factors for these I2C modes:348 * t_low_min, t_high_min, scl_clock, proportion349 * Standard Mode: 4.7us, 4.0us, 10us, 0.535350 * Fast Mode: 1.3us, 0.6us, 2.5us, 0.64351 * Fast-Plus Mode: 0.5us, 0.26us, 1us, 0.62352 *353 */354 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;355 temp = clkin / op_clk - 8 - t_ftl_cycle;356 if (i2c->variant->hw != I2C_TYPE_EXYNOS7)357 temp -= t_ftl_cycle;358 div = temp / 512;359 clk_cycle = temp / (div + 1) - 2;360 if (temp < 4 || div >= 256 || clk_cycle < 2) {361 dev_err(i2c->dev, "%s clock set-up failed\n",362 hs_timings ? "HS" : "FS");363 return -EINVAL;364 }365 366 /*367 * Scale clk_cycle to get t_scl_l using the proption factors for individual I2C modes.368 */369 if (op_clk <= I2C_MAX_STANDARD_MODE_FREQ)370 t_scl_l = clk_cycle * 535 / 1000;371 else if (op_clk <= I2C_MAX_FAST_MODE_FREQ)372 t_scl_l = clk_cycle * 64 / 100;373 else374 t_scl_l = clk_cycle * 62 / 100;375 376 if (t_scl_l > 0xFF)377 t_scl_l = 0xFF;378 t_scl_h = clk_cycle - t_scl_l;379 t_start_su = t_scl_l;380 t_start_hd = t_scl_l;381 t_stop_su = t_scl_l;382 t_data_su = t_scl_l / 2;383 t_data_hd = t_scl_l / 2;384 t_sr_release = clk_cycle;385 386 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;387 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;388 i2c_timing_s3 = div << 16 | t_sr_release << 0;389 i2c_timing_sla = t_data_hd << 0;390 391 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",392 t_start_su, t_start_hd, t_stop_su);393 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",394 t_data_su, t_scl_l, t_scl_h);395 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",396 div, t_sr_release);397 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);398 399 if (hs_timings) {400 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);401 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);402 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);403 } else {404 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);405 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);406 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);407 }408 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);409 410 return 0;411}412 413static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)414{415 /* always set Fast Speed timings */416 int ret = exynos5_i2c_set_timing(i2c, false);417 418 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)419 return ret;420 421 return exynos5_i2c_set_timing(i2c, true);422}423 424/*425 * exynos5_i2c_init: configures the controller for I2C functionality426 * Programs I2C controller for Master mode operation427 */428static void exynos5_i2c_init(struct exynos5_i2c *i2c)429{430 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);431 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);432 433 /* Clear to disable Timeout */434 i2c_timeout &= ~HSI2C_TIMEOUT_EN;435 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);436 437 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),438 i2c->regs + HSI2C_CTL);439 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);440 441 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {442 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),443 i2c->regs + HSI2C_ADDR);444 i2c_conf |= HSI2C_HS_MODE;445 }446 447 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);448}449 450static void exynos5_i2c_reset(struct exynos5_i2c *i2c)451{452 u32 i2c_ctl;453 454 /* Set and clear the bit for reset */455 i2c_ctl = readl(i2c->regs + HSI2C_CTL);456 i2c_ctl |= HSI2C_SW_RST;457 writel(i2c_ctl, i2c->regs + HSI2C_CTL);458 459 i2c_ctl = readl(i2c->regs + HSI2C_CTL);460 i2c_ctl &= ~HSI2C_SW_RST;461 writel(i2c_ctl, i2c->regs + HSI2C_CTL);462 463 /* We don't expect calculations to fail during the run */464 exynos5_hsi2c_clock_setup(i2c);465 /* Initialize the configure registers */466 exynos5_i2c_init(i2c);467}468 469/*470 * exynos5_i2c_irq: top level IRQ servicing routine471 *472 * INT_STATUS registers gives the interrupt details. Further,473 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed474 * state of the bus.475 */476static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)477{478 struct exynos5_i2c *i2c = dev_id;479 u32 fifo_level, int_status, fifo_status, trans_status;480 unsigned char byte;481 int len = 0;482 483 i2c->state = -EINVAL;484 485 spin_lock(&i2c->lock);486 487 int_status = readl(i2c->regs + HSI2C_INT_STATUS);488 writel(int_status, i2c->regs + HSI2C_INT_STATUS);489 490 /* handle interrupt related to the transfer status */491 switch (i2c->variant->hw) {492 case I2C_TYPE_EXYNOSAUTOV9:493 fallthrough;494 case I2C_TYPE_EXYNOS7:495 if (int_status & HSI2C_INT_TRANS_DONE) {496 i2c->trans_done = 1;497 i2c->state = 0;498 } else if (int_status & HSI2C_INT_TRANS_ABORT) {499 dev_dbg(i2c->dev, "Deal with arbitration lose\n");500 i2c->state = -EAGAIN;501 goto stop;502 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {503 dev_dbg(i2c->dev, "No ACK from device\n");504 i2c->state = -ENXIO;505 goto stop;506 } else if (int_status & HSI2C_INT_NO_DEV) {507 dev_dbg(i2c->dev, "No device\n");508 i2c->state = -ENXIO;509 goto stop;510 } else if (int_status & HSI2C_INT_TIMEOUT) {511 dev_dbg(i2c->dev, "Accessing device timed out\n");512 i2c->state = -ETIMEDOUT;513 goto stop;514 }515 516 break;517 case I2C_TYPE_EXYNOS5:518 if (!(int_status & HSI2C_INT_I2C))519 break;520 521 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);522 if (trans_status & HSI2C_NO_DEV_ACK) {523 dev_dbg(i2c->dev, "No ACK from device\n");524 i2c->state = -ENXIO;525 goto stop;526 } else if (trans_status & HSI2C_NO_DEV) {527 dev_dbg(i2c->dev, "No device\n");528 i2c->state = -ENXIO;529 goto stop;530 } else if (trans_status & HSI2C_TRANS_ABORT) {531 dev_dbg(i2c->dev, "Deal with arbitration lose\n");532 i2c->state = -EAGAIN;533 goto stop;534 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {535 dev_dbg(i2c->dev, "Accessing device timed out\n");536 i2c->state = -ETIMEDOUT;537 goto stop;538 } else if (trans_status & HSI2C_TRANS_DONE) {539 i2c->trans_done = 1;540 i2c->state = 0;541 }542 543 break;544 }545 546 if ((i2c->msg->flags & I2C_M_RD) && (int_status &547 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {548 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);549 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);550 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);551 552 while (len > 0) {553 byte = (unsigned char)554 readl(i2c->regs + HSI2C_RX_DATA);555 i2c->msg->buf[i2c->msg_ptr++] = byte;556 len--;557 }558 i2c->state = 0;559 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {560 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);561 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);562 563 len = i2c->variant->fifo_depth - fifo_level;564 if (len > (i2c->msg->len - i2c->msg_ptr)) {565 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);566 567 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;568 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);569 len = i2c->msg->len - i2c->msg_ptr;570 }571 572 while (len > 0) {573 byte = i2c->msg->buf[i2c->msg_ptr++];574 writel(byte, i2c->regs + HSI2C_TX_DATA);575 len--;576 }577 i2c->state = 0;578 }579 580 stop:581 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||582 (i2c->state < 0)) {583 writel(0, i2c->regs + HSI2C_INT_ENABLE);584 exynos5_i2c_clr_pend_irq(i2c);585 complete(&i2c->msg_complete);586 }587 588 spin_unlock(&i2c->lock);589 590 return IRQ_HANDLED;591}592 593/*594 * exynos5_i2c_wait_bus_idle595 *596 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being597 * cleared.598 *599 * Returns -EBUSY if the bus cannot be bought to idle600 */601static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)602{603 unsigned long stop_time;604 u32 trans_status;605 606 /* wait for 100 milli seconds for the bus to be idle */607 stop_time = jiffies + msecs_to_jiffies(100) + 1;608 do {609 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);610 if (!(trans_status & HSI2C_MASTER_BUSY))611 return 0;612 613 usleep_range(50, 200);614 } while (time_before(jiffies, stop_time));615 616 return -EBUSY;617}618 619static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)620{621 u32 val;622 623 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;624 writel(val, i2c->regs + HSI2C_CTL);625 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;626 writel(val, i2c->regs + HSI2C_CONF);627 628 /*629 * Specification says master should send nine clock pulses. It can be630 * emulated by sending manual read command (nine pulses for read eight631 * bits + one pulse for NACK).632 */633 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);634 exynos5_i2c_wait_bus_idle(i2c);635 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);636 exynos5_i2c_wait_bus_idle(i2c);637 638 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;639 writel(val, i2c->regs + HSI2C_CTL);640 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;641 writel(val, i2c->regs + HSI2C_CONF);642}643 644static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)645{646 unsigned long timeout;647 648 if (i2c->variant->hw == I2C_TYPE_EXYNOS5)649 return;650 651 /*652 * HSI2C_MASTER_ST_LOSE state (in Exynos7 and ExynosAutoV9 variants)653 * before transaction indicates that bus is stuck (SDA is low).654 * In such case bus recovery can be performed.655 */656 timeout = jiffies + msecs_to_jiffies(100);657 for (;;) {658 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);659 660 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)661 return;662 663 if (time_is_before_jiffies(timeout))664 return;665 666 exynos5_i2c_bus_recover(i2c);667 }668}669 670/*671 * exynos5_i2c_message_start: Configures the bus and starts the xfer672 * i2c: struct exynos5_i2c pointer for the current bus673 * stop: Enables stop after transfer if set. Set for last transfer of674 * in the list of messages.675 *676 * Configures the bus for read/write function677 * Sets chip address to talk to, message length to be sent.678 * Enables appropriate interrupts and sends start xfer command.679 */680static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)681{682 u32 i2c_ctl;683 u32 int_en = 0;684 u32 i2c_auto_conf = 0;685 u32 i2c_addr = 0;686 u32 fifo_ctl;687 unsigned long flags;688 unsigned short trig_lvl;689 690 if (i2c->variant->hw == I2C_TYPE_EXYNOS5)691 int_en |= HSI2C_INT_I2C;692 else693 int_en |= HSI2C_INT_I2C_TRANS;694 695 i2c_ctl = readl(i2c->regs + HSI2C_CTL);696 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);697 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;698 699 if (i2c->msg->flags & I2C_M_RD) {700 i2c_ctl |= HSI2C_RXCHON;701 702 i2c_auto_conf |= HSI2C_READ_WRITE;703 704 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?705 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;706 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);707 708 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |709 HSI2C_INT_TRAILING_EN);710 } else {711 i2c_ctl |= HSI2C_TXCHON;712 713 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?714 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;715 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);716 717 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;718 }719 720 i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr);721 722 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ)723 i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr));724 725 writel(i2c_addr, i2c->regs + HSI2C_ADDR);726 727 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);728 writel(i2c_ctl, i2c->regs + HSI2C_CTL);729 730 exynos5_i2c_bus_check(i2c);731 732 /*733 * Enable interrupts before starting the transfer so that we don't734 * miss any INT_I2C interrupts.735 */736 spin_lock_irqsave(&i2c->lock, flags);737 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);738 739 if (stop == 1)740 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;741 i2c_auto_conf |= i2c->msg->len;742 i2c_auto_conf |= HSI2C_MASTER_RUN;743 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);744 spin_unlock_irqrestore(&i2c->lock, flags);745}746 747static bool exynos5_i2c_poll_irqs_timeout(struct exynos5_i2c *i2c,748 unsigned long timeout)749{750 unsigned long time_left = jiffies + timeout;751 752 while (time_before(jiffies, time_left) &&753 !((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||754 (i2c->state < 0))) {755 while (readl(i2c->regs + HSI2C_INT_ENABLE) &756 readl(i2c->regs + HSI2C_INT_STATUS))757 exynos5_i2c_irq(i2c->irq, i2c);758 usleep_range(100, 200);759 }760 return time_before(jiffies, time_left);761}762 763static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,764 struct i2c_msg *msgs, int stop)765{766 unsigned long time_left;767 int ret;768 769 i2c->msg = msgs;770 i2c->msg_ptr = 0;771 i2c->trans_done = 0;772 773 reinit_completion(&i2c->msg_complete);774 775 exynos5_i2c_message_start(i2c, stop);776 777 if (!i2c->atomic)778 time_left = wait_for_completion_timeout(&i2c->msg_complete,779 EXYNOS5_I2C_TIMEOUT);780 else781 time_left = exynos5_i2c_poll_irqs_timeout(i2c,782 EXYNOS5_I2C_TIMEOUT);783 784 if (time_left == 0)785 ret = -ETIMEDOUT;786 else787 ret = i2c->state;788 789 /*790 * If this is the last message to be transfered (stop == 1)791 * Then check if the bus can be brought back to idle.792 */793 if (ret == 0 && stop)794 ret = exynos5_i2c_wait_bus_idle(i2c);795 796 if (ret < 0) {797 exynos5_i2c_reset(i2c);798 if (ret == -ETIMEDOUT)799 dev_warn(i2c->dev, "%s timeout\n",800 (msgs->flags & I2C_M_RD) ? "rx" : "tx");801 }802 803 /* Return the state as in interrupt routine */804 return ret;805}806 807static int exynos5_i2c_xfer(struct i2c_adapter *adap,808 struct i2c_msg *msgs, int num)809{810 struct exynos5_i2c *i2c = adap->algo_data;811 int i, ret;812 813 ret = clk_enable(i2c->pclk);814 if (ret)815 return ret;816 817 ret = clk_enable(i2c->clk);818 if (ret)819 goto err_pclk;820 821 for (i = 0; i < num; ++i) {822 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);823 if (ret)824 break;825 }826 827 clk_disable(i2c->clk);828err_pclk:829 clk_disable(i2c->pclk);830 831 return ret ?: num;832}833 834static int exynos5_i2c_xfer_atomic(struct i2c_adapter *adap,835 struct i2c_msg *msgs, int num)836{837 struct exynos5_i2c *i2c = adap->algo_data;838 int ret;839 840 disable_irq(i2c->irq);841 i2c->atomic = true;842 ret = exynos5_i2c_xfer(adap, msgs, num);843 i2c->atomic = false;844 enable_irq(i2c->irq);845 846 return ret;847}848 849static u32 exynos5_i2c_func(struct i2c_adapter *adap)850{851 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);852}853 854static const struct i2c_algorithm exynos5_i2c_algorithm = {855 .master_xfer = exynos5_i2c_xfer,856 .master_xfer_atomic = exynos5_i2c_xfer_atomic,857 .functionality = exynos5_i2c_func,858};859 860static int exynos5_i2c_probe(struct platform_device *pdev)861{862 struct device_node *np = pdev->dev.of_node;863 struct exynos5_i2c *i2c;864 int ret;865 866 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);867 if (!i2c)868 return -ENOMEM;869 870 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))871 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;872 873 strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));874 i2c->adap.owner = THIS_MODULE;875 i2c->adap.algo = &exynos5_i2c_algorithm;876 i2c->adap.retries = 3;877 878 i2c->dev = &pdev->dev;879 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");880 if (IS_ERR(i2c->clk)) {881 dev_err(&pdev->dev, "cannot get clock\n");882 return -ENOENT;883 }884 885 i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk");886 if (IS_ERR(i2c->pclk)) {887 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),888 "cannot get pclk");889 }890 891 ret = clk_prepare_enable(i2c->pclk);892 if (ret)893 return ret;894 895 ret = clk_prepare_enable(i2c->clk);896 if (ret)897 goto err_pclk;898 899 i2c->regs = devm_platform_ioremap_resource(pdev, 0);900 if (IS_ERR(i2c->regs)) {901 ret = PTR_ERR(i2c->regs);902 goto err_clk;903 }904 905 i2c->adap.dev.of_node = np;906 i2c->adap.algo_data = i2c;907 i2c->adap.dev.parent = &pdev->dev;908 909 /* Clear pending interrupts from u-boot or misc causes */910 exynos5_i2c_clr_pend_irq(i2c);911 912 spin_lock_init(&i2c->lock);913 init_completion(&i2c->msg_complete);914 915 i2c->irq = ret = platform_get_irq(pdev, 0);916 if (ret < 0)917 goto err_clk;918 919 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,920 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);921 if (ret != 0) {922 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);923 goto err_clk;924 }925 926 i2c->variant = of_device_get_match_data(&pdev->dev);927 928 ret = exynos5_hsi2c_clock_setup(i2c);929 if (ret)930 goto err_clk;931 932 exynos5_i2c_reset(i2c);933 934 ret = i2c_add_adapter(&i2c->adap);935 if (ret < 0)936 goto err_clk;937 938 platform_set_drvdata(pdev, i2c);939 940 clk_disable(i2c->clk);941 clk_disable(i2c->pclk);942 943 return 0;944 945 err_clk:946 clk_disable_unprepare(i2c->clk);947 948 err_pclk:949 clk_disable_unprepare(i2c->pclk);950 return ret;951}952 953static void exynos5_i2c_remove(struct platform_device *pdev)954{955 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);956 957 i2c_del_adapter(&i2c->adap);958 959 clk_unprepare(i2c->clk);960 clk_unprepare(i2c->pclk);961}962 963static int exynos5_i2c_suspend_noirq(struct device *dev)964{965 struct exynos5_i2c *i2c = dev_get_drvdata(dev);966 967 i2c_mark_adapter_suspended(&i2c->adap);968 clk_unprepare(i2c->clk);969 clk_unprepare(i2c->pclk);970 971 return 0;972}973 974static int exynos5_i2c_resume_noirq(struct device *dev)975{976 struct exynos5_i2c *i2c = dev_get_drvdata(dev);977 int ret = 0;978 979 ret = clk_prepare_enable(i2c->pclk);980 if (ret)981 return ret;982 983 ret = clk_prepare_enable(i2c->clk);984 if (ret)985 goto err_pclk;986 987 ret = exynos5_hsi2c_clock_setup(i2c);988 if (ret)989 goto err_clk;990 991 exynos5_i2c_init(i2c);992 clk_disable(i2c->clk);993 clk_disable(i2c->pclk);994 i2c_mark_adapter_resumed(&i2c->adap);995 996 return 0;997 998err_clk:999 clk_disable_unprepare(i2c->clk);1000err_pclk:1001 clk_disable_unprepare(i2c->pclk);1002 return ret;1003}1004 1005static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {1006 NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,1007 exynos5_i2c_resume_noirq)1008};1009 1010static struct platform_driver exynos5_i2c_driver = {1011 .probe = exynos5_i2c_probe,1012 .remove_new = exynos5_i2c_remove,1013 .driver = {1014 .name = "exynos5-hsi2c",1015 .pm = pm_sleep_ptr(&exynos5_i2c_dev_pm_ops),1016 .of_match_table = exynos5_i2c_match,1017 },1018};1019 1020module_platform_driver(exynos5_i2c_driver);1021 1022MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");1023MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");1024MODULE_AUTHOR("Taekgyun Ko <taeggyun.ko@samsung.com>");1025MODULE_LICENSE("GPL v2");1026