1605 lines · c
1// SPDX-License-Identifier: GPL-2.0+2/*3 * Copyright (C) 2002 Motorola GSG-China4 *5 * Author:6 * Darius Augulis, Teltonika Inc.7 *8 * Desc.:9 * Implementation of I2C Adapter/Algorithm Driver10 * for I2C Bus integrated in Freescale i.MX/MXC processors11 *12 * Derived from Motorola GSG China I2C example driver13 *14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de16 * Copyright (C) 2007 RightHand Technologies, Inc.17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>18 *19 * Copyright 2013 Freescale Semiconductor, Inc.20 * Copyright 2020 NXP21 *22 */23 24#include <linux/acpi.h>25#include <linux/clk.h>26#include <linux/completion.h>27#include <linux/delay.h>28#include <linux/dma-mapping.h>29#include <linux/dmaengine.h>30#include <linux/dmapool.h>31#include <linux/err.h>32#include <linux/errno.h>33#include <linux/gpio/consumer.h>34#include <linux/i2c.h>35#include <linux/init.h>36#include <linux/interrupt.h>37#include <linux/io.h>38#include <linux/iopoll.h>39#include <linux/kernel.h>40#include <linux/spinlock.h>41#include <linux/hrtimer.h>42#include <linux/module.h>43#include <linux/of.h>44#include <linux/of_dma.h>45#include <linux/pinctrl/consumer.h>46#include <linux/platform_data/i2c-imx.h>47#include <linux/platform_device.h>48#include <linux/pm_runtime.h>49#include <linux/sched.h>50#include <linux/slab.h>51 52/* This will be the driver name the kernel reports */53#define DRIVER_NAME "imx-i2c"54 55#define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */56 57/*58 * Enable DMA if transfer byte size is bigger than this threshold.59 * As the hardware request, it must bigger than 4 bytes.\60 * I have set '16' here, maybe it's not the best but I think it's61 * the appropriate.62 */63#define DMA_THRESHOLD 1664#define DMA_TIMEOUT 100065 66/* IMX I2C registers:67 * the I2C register offset is different between SoCs,68 * to provide support for all these chips, split the69 * register offset into a fixed base address and a70 * variable shift value, then the full register offset71 * will be calculated by72 * reg_off = ( reg_base_addr << reg_shift)73 */74#define IMX_I2C_IADR 0x00 /* i2c slave address */75#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */76#define IMX_I2C_I2CR 0x02 /* i2c control */77#define IMX_I2C_I2SR 0x03 /* i2c status */78#define IMX_I2C_I2DR 0x04 /* i2c transfer data */79 80/*81 * All of the layerscape series SoCs support IBIC register.82 */83#define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */84 85#define IMX_I2C_REGSHIFT 286#define VF610_I2C_REGSHIFT 087 88/* Bits of IMX I2C registers */89#define I2SR_RXAK 0x0190#define I2SR_IIF 0x0291#define I2SR_SRW 0x0492#define I2SR_IAL 0x1093#define I2SR_IBB 0x2094#define I2SR_IAAS 0x4095#define I2SR_ICF 0x8096#define I2CR_DMAEN 0x0297#define I2CR_RSTA 0x0498#define I2CR_TXAK 0x0899#define I2CR_MTX 0x10100#define I2CR_MSTA 0x20101#define I2CR_IIEN 0x40102#define I2CR_IEN 0x80103#define IBIC_BIIE 0x80 /* Bus idle interrupt enable */104 105/* register bits different operating codes definition:106 * 1) I2SR: Interrupt flags clear operation differ between SoCs:107 * - write zero to clear(w0c) INT flag on i.MX,108 * - but write one to clear(w1c) INT flag on Vybrid.109 * 2) I2CR: I2C module enable operation also differ between SoCs:110 * - set I2CR_IEN bit enable the module on i.MX,111 * - but clear I2CR_IEN bit enable the module on Vybrid.112 */113#define I2SR_CLR_OPCODE_W0C 0x0114#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)115#define I2CR_IEN_OPCODE_0 0x0116#define I2CR_IEN_OPCODE_1 I2CR_IEN117 118#define I2C_PM_TIMEOUT 10 /* ms */119 120/*121 * sorted list of clock divider, register value pairs122 * taken from table 26-5, p.26-9, Freescale i.MX123 * Integrated Portable System Processor Reference Manual124 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007125 *126 * Duplicated divider values removed from list127 */128struct imx_i2c_clk_pair {129 u16 div;130 u16 val;131};132 133static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {134 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },135 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },136 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },137 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },138 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },139 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },140 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },141 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },142 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },143 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },144 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },145 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },146 { 3072, 0x1E }, { 3840, 0x1F }147};148 149/* Vybrid VF610 clock divider, register value pairs */150static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {151 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },152 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },153 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },154 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },155 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },156 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },157 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },158 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },159 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },160 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },161 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },162 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },163 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },164 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },165 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },166};167 168enum imx_i2c_type {169 IMX1_I2C,170 IMX21_I2C,171 VF610_I2C,172};173 174struct imx_i2c_hwdata {175 enum imx_i2c_type devtype;176 unsigned int regshift;177 struct imx_i2c_clk_pair *clk_div;178 unsigned int ndivs;179 unsigned int i2sr_clr_opcode;180 unsigned int i2cr_ien_opcode;181 /*182 * Errata ERR007805 or e7805:183 * I2C: When the I2C clock speed is configured for 400 kHz,184 * the SCL low period violates the I2C spec of 1.3 uS min.185 */186 bool has_err007805;187};188 189struct imx_i2c_dma {190 struct dma_chan *chan_tx;191 struct dma_chan *chan_rx;192 struct dma_chan *chan_using;193 struct completion cmd_complete;194 dma_addr_t dma_buf;195 unsigned int dma_len;196 enum dma_transfer_direction dma_transfer_dir;197 enum dma_data_direction dma_data_dir;198};199 200struct imx_i2c_struct {201 struct i2c_adapter adapter;202 struct clk *clk;203 struct notifier_block clk_change_nb;204 void __iomem *base;205 wait_queue_head_t queue;206 unsigned long i2csr;207 unsigned int disable_delay;208 int stopped;209 unsigned int ifdr; /* IMX_I2C_IFDR */210 unsigned int cur_clk;211 unsigned int bitrate;212 const struct imx_i2c_hwdata *hwdata;213 struct i2c_bus_recovery_info rinfo;214 215 struct imx_i2c_dma *dma;216 struct i2c_client *slave;217 enum i2c_slave_event last_slave_event;218 219 /* For checking slave events. */220 spinlock_t slave_lock;221 struct hrtimer slave_timer;222};223 224static const struct imx_i2c_hwdata imx1_i2c_hwdata = {225 .devtype = IMX1_I2C,226 .regshift = IMX_I2C_REGSHIFT,227 .clk_div = imx_i2c_clk_div,228 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),229 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,230 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,231 232};233 234static const struct imx_i2c_hwdata imx21_i2c_hwdata = {235 .devtype = IMX21_I2C,236 .regshift = IMX_I2C_REGSHIFT,237 .clk_div = imx_i2c_clk_div,238 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),239 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,240 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,241 242};243 244static const struct imx_i2c_hwdata imx6_i2c_hwdata = {245 .devtype = IMX21_I2C,246 .regshift = IMX_I2C_REGSHIFT,247 .clk_div = imx_i2c_clk_div,248 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),249 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,250 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,251 .has_err007805 = true,252};253 254static struct imx_i2c_hwdata vf610_i2c_hwdata = {255 .devtype = VF610_I2C,256 .regshift = VF610_I2C_REGSHIFT,257 .clk_div = vf610_i2c_clk_div,258 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),259 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,260 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,261 262};263 264static const struct platform_device_id imx_i2c_devtype[] = {265 {266 .name = "imx1-i2c",267 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,268 }, {269 .name = "imx21-i2c",270 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,271 }, {272 /* sentinel */273 }274};275MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);276 277static const struct of_device_id i2c_imx_dt_ids[] = {278 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },279 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },280 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, },281 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, },282 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, },283 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, },284 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, },285 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, },286 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, },287 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, },288 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },289 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },290 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },291 { /* sentinel */ }292};293MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);294 295static const struct acpi_device_id i2c_imx_acpi_ids[] = {296 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},297 { }298};299MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);300 301static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)302{303 return i2c_imx->hwdata->devtype == IMX1_I2C;304}305 306static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)307{308 return i2c_imx->hwdata->devtype == VF610_I2C;309}310 311static inline void imx_i2c_write_reg(unsigned int val,312 struct imx_i2c_struct *i2c_imx, unsigned int reg)313{314 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));315}316 317static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,318 unsigned int reg)319{320 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));321}322 323static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)324{325 unsigned int temp;326 327 /*328 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to329 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>330 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.331 */332 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;333 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);334}335 336/* Set up i2c controller register and i2c status register to default value. */337static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)338{339 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,340 i2c_imx, IMX_I2C_I2CR);341 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);342}343 344/* Functions for DMA support */345static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,346 dma_addr_t phy_addr)347{348 struct imx_i2c_dma *dma;349 struct dma_slave_config dma_sconfig;350 struct device *dev = &i2c_imx->adapter.dev;351 int ret;352 353 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);354 if (!dma)355 return;356 357 dma->chan_tx = dma_request_chan(dev, "tx");358 if (IS_ERR(dma->chan_tx)) {359 ret = PTR_ERR(dma->chan_tx);360 if (ret != -ENODEV && ret != -EPROBE_DEFER)361 dev_err(dev, "can't request DMA tx channel (%d)\n", ret);362 goto fail_al;363 }364 365 dma_sconfig.dst_addr = phy_addr +366 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);367 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;368 dma_sconfig.dst_maxburst = 1;369 dma_sconfig.direction = DMA_MEM_TO_DEV;370 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);371 if (ret < 0) {372 dev_err(dev, "can't configure tx channel (%d)\n", ret);373 goto fail_tx;374 }375 376 dma->chan_rx = dma_request_chan(dev, "rx");377 if (IS_ERR(dma->chan_rx)) {378 ret = PTR_ERR(dma->chan_rx);379 if (ret != -ENODEV && ret != -EPROBE_DEFER)380 dev_err(dev, "can't request DMA rx channel (%d)\n", ret);381 goto fail_tx;382 }383 384 dma_sconfig.src_addr = phy_addr +385 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);386 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;387 dma_sconfig.src_maxburst = 1;388 dma_sconfig.direction = DMA_DEV_TO_MEM;389 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);390 if (ret < 0) {391 dev_err(dev, "can't configure rx channel (%d)\n", ret);392 goto fail_rx;393 }394 395 i2c_imx->dma = dma;396 init_completion(&dma->cmd_complete);397 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",398 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));399 400 return;401 402fail_rx:403 dma_release_channel(dma->chan_rx);404fail_tx:405 dma_release_channel(dma->chan_tx);406fail_al:407 devm_kfree(dev, dma);408}409 410static void i2c_imx_dma_callback(void *arg)411{412 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;413 struct imx_i2c_dma *dma = i2c_imx->dma;414 415 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,416 dma->dma_len, dma->dma_data_dir);417 complete(&dma->cmd_complete);418}419 420static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,421 struct i2c_msg *msgs)422{423 struct imx_i2c_dma *dma = i2c_imx->dma;424 struct dma_async_tx_descriptor *txdesc;425 struct device *dev = &i2c_imx->adapter.dev;426 struct device *chan_dev = dma->chan_using->device->dev;427 428 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,429 dma->dma_len, dma->dma_data_dir);430 if (dma_mapping_error(chan_dev, dma->dma_buf)) {431 dev_err(dev, "DMA mapping failed\n");432 goto err_map;433 }434 435 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,436 dma->dma_len, dma->dma_transfer_dir,437 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);438 if (!txdesc) {439 dev_err(dev, "Not able to get desc for DMA xfer\n");440 goto err_desc;441 }442 443 reinit_completion(&dma->cmd_complete);444 txdesc->callback = i2c_imx_dma_callback;445 txdesc->callback_param = i2c_imx;446 if (dma_submit_error(dmaengine_submit(txdesc))) {447 dev_err(dev, "DMA submit failed\n");448 goto err_submit;449 }450 451 dma_async_issue_pending(dma->chan_using);452 return 0;453 454err_submit:455 dmaengine_terminate_sync(dma->chan_using);456err_desc:457 dma_unmap_single(chan_dev, dma->dma_buf,458 dma->dma_len, dma->dma_data_dir);459err_map:460 return -EINVAL;461}462 463static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)464{465 struct imx_i2c_dma *dma = i2c_imx->dma;466 467 dma->dma_buf = 0;468 dma->dma_len = 0;469 470 dma_release_channel(dma->chan_tx);471 dma->chan_tx = NULL;472 473 dma_release_channel(dma->chan_rx);474 dma->chan_rx = NULL;475 476 dma->chan_using = NULL;477}478 479static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)480{481 unsigned long orig_jiffies = jiffies;482 unsigned int temp;483 484 while (1) {485 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);486 487 /* check for arbitration lost */488 if (temp & I2SR_IAL) {489 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);490 return -EAGAIN;491 }492 493 if (for_busy && (temp & I2SR_IBB)) {494 i2c_imx->stopped = 0;495 break;496 }497 if (!for_busy && !(temp & I2SR_IBB)) {498 i2c_imx->stopped = 1;499 break;500 }501 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {502 dev_dbg(&i2c_imx->adapter.dev,503 "<%s> I2C bus is busy\n", __func__);504 return -ETIMEDOUT;505 }506 if (atomic)507 udelay(100);508 else509 schedule();510 }511 512 return 0;513}514 515static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)516{517 if (atomic) {518 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);519 unsigned int regval;520 521 /*522 * The formula for the poll timeout is documented in the RM523 * Rev.5 on page 1878:524 * T_min = 10/F_scl525 * Set the value hard as it is done for the non-atomic use-case.526 * Use 10 kHz for the calculation since this is the minimum527 * allowed SMBus frequency. Also add an offset of 100us since it528 * turned out that the I2SR_IIF bit isn't set correctly within529 * the minimum timeout in polling mode.530 */531 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);532 i2c_imx->i2csr = regval;533 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);534 } else {535 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);536 }537 538 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {539 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);540 return -ETIMEDOUT;541 }542 543 /* check for arbitration lost */544 if (i2c_imx->i2csr & I2SR_IAL) {545 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);546 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);547 548 i2c_imx->i2csr = 0;549 return -EAGAIN;550 }551 552 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);553 i2c_imx->i2csr = 0;554 return 0;555}556 557static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)558{559 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {560 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);561 return -ENXIO; /* No ACK */562 }563 564 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);565 return 0;566}567 568static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,569 unsigned int i2c_clk_rate)570{571 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;572 unsigned int div;573 int i;574 575 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) {576 dev_dbg(&i2c_imx->adapter.dev,577 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n",578 i2c_imx->bitrate);579 i2c_imx->bitrate = 384000;580 }581 582 /* Divider value calculation */583 if (i2c_imx->cur_clk == i2c_clk_rate)584 return;585 586 i2c_imx->cur_clk = i2c_clk_rate;587 588 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);589 if (div < i2c_clk_div[0].div)590 i = 0;591 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)592 i = i2c_imx->hwdata->ndivs - 1;593 else594 for (i = 0; i2c_clk_div[i].div < div; i++)595 ;596 597 /* Store divider value */598 i2c_imx->ifdr = i2c_clk_div[i].val;599 600 /*601 * There dummy delay is calculated.602 * It should be about one I2C clock period long.603 * This delay is used in I2C bus disable function604 * to fix chip hardware bug.605 */606 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,607 i2c_clk_rate / 2);608 609#ifdef CONFIG_I2C_DEBUG_BUS610 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",611 i2c_clk_rate, div);612 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",613 i2c_clk_div[i].val, i2c_clk_div[i].div);614#endif615}616 617static int i2c_imx_clk_notifier_call(struct notifier_block *nb,618 unsigned long action, void *data)619{620 struct clk_notifier_data *ndata = data;621 struct imx_i2c_struct *i2c_imx = container_of(nb,622 struct imx_i2c_struct,623 clk_change_nb);624 625 if (action & POST_RATE_CHANGE)626 i2c_imx_set_clk(i2c_imx, ndata->new_rate);627 628 return NOTIFY_OK;629}630 631static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)632{633 unsigned int temp = 0;634 int result;635 636 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);637 /* Enable I2C controller */638 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);639 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);640 641 /* Wait controller to be stable */642 if (atomic)643 udelay(50);644 else645 usleep_range(50, 150);646 647 /* Start I2C transaction */648 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);649 temp |= I2CR_MSTA;650 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);651 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);652 if (result)653 return result;654 655 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;656 if (atomic)657 temp &= ~I2CR_IIEN; /* Disable interrupt */658 659 temp &= ~I2CR_DMAEN;660 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);661 return result;662}663 664static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)665{666 unsigned int temp = 0;667 668 if (!i2c_imx->stopped) {669 /* Stop I2C transaction */670 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);671 if (!(temp & I2CR_MSTA))672 i2c_imx->stopped = 1;673 temp &= ~(I2CR_MSTA | I2CR_MTX);674 if (i2c_imx->dma)675 temp &= ~I2CR_DMAEN;676 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);677 }678 if (is_imx1_i2c(i2c_imx)) {679 /*680 * This delay caused by an i.MXL hardware bug.681 * If no (or too short) delay, no "STOP" bit will be generated.682 */683 udelay(i2c_imx->disable_delay);684 }685 686 if (!i2c_imx->stopped)687 i2c_imx_bus_busy(i2c_imx, 0, atomic);688 689 /* Disable I2C controller */690 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN;691 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);692}693 694/*695 * Enable bus idle interrupts696 * Note: IBIC register will be cleared after disabled i2c module.697 * All of layerscape series SoCs support IBIC register.698 */699static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)700{701 if (is_vf610_i2c(i2c_imx)) {702 unsigned int temp;703 704 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);705 temp |= IBIC_BIIE;706 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);707 }708}709 710static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx,711 enum i2c_slave_event event, u8 *val)712{713 i2c_slave_event(i2c_imx->slave, event, val);714 i2c_imx->last_slave_event = event;715}716 717static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx)718{719 u8 val = 0;720 721 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {722 switch (i2c_imx->last_slave_event) {723 case I2C_SLAVE_READ_REQUESTED:724 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED,725 &val);726 break;727 728 case I2C_SLAVE_WRITE_REQUESTED:729 case I2C_SLAVE_READ_PROCESSED:730 case I2C_SLAVE_WRITE_RECEIVED:731 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val);732 break;733 734 case I2C_SLAVE_STOP:735 break;736 }737 }738}739 740/* Returns true if the timer should be restarted, false if not. */741static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx,742 unsigned int status, unsigned int ctl)743{744 u8 value = 0;745 746 if (status & I2SR_IAL) { /* Arbitration lost */747 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);748 if (!(status & I2SR_IAAS))749 return IRQ_HANDLED;750 }751 752 if (!(status & I2SR_IBB)) {753 /* No master on the bus, that could mean a stop condition. */754 i2c_imx_slave_finish_op(i2c_imx);755 return IRQ_HANDLED;756 }757 758 if (!(status & I2SR_ICF))759 /* Data transfer still in progress, ignore this. */760 goto out;761 762 if (status & I2SR_IAAS) { /* Addressed as a slave */763 i2c_imx_slave_finish_op(i2c_imx);764 if (status & I2SR_SRW) { /* Master wants to read from us*/765 dev_dbg(&i2c_imx->adapter.dev, "read requested");766 i2c_imx_slave_event(i2c_imx,767 I2C_SLAVE_READ_REQUESTED, &value);768 769 /* Slave transmit */770 ctl |= I2CR_MTX;771 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);772 773 /* Send data */774 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);775 } else { /* Master wants to write to us */776 dev_dbg(&i2c_imx->adapter.dev, "write requested");777 i2c_imx_slave_event(i2c_imx,778 I2C_SLAVE_WRITE_REQUESTED, &value);779 780 /* Slave receive */781 ctl &= ~I2CR_MTX;782 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);783 /* Dummy read */784 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);785 }786 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */787 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);788 i2c_imx_slave_event(i2c_imx,789 I2C_SLAVE_WRITE_RECEIVED, &value);790 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */791 ctl |= I2CR_MTX;792 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);793 794 i2c_imx_slave_event(i2c_imx,795 I2C_SLAVE_READ_PROCESSED, &value);796 797 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);798 } else { /* Transmit mode received NAK, operation is done */799 ctl &= ~I2CR_MTX;800 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);801 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);802 803 /* flag the last byte as processed */804 i2c_imx_slave_event(i2c_imx,805 I2C_SLAVE_READ_PROCESSED, &value);806 807 i2c_imx_slave_finish_op(i2c_imx);808 return IRQ_HANDLED;809 }810 811out:812 /*813 * No need to check the return value here. If it returns 0 or814 * 1, then everything is fine. If it returns -1, then the815 * timer is running in the handler. This will still work,816 * though it may be redone (or already have been done) by the817 * timer function.818 */819 hrtimer_try_to_cancel(&i2c_imx->slave_timer);820 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);821 hrtimer_restart(&i2c_imx->slave_timer);822 return IRQ_HANDLED;823}824 825static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t)826{827 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct,828 slave_timer);829 unsigned int ctl, status;830 unsigned long flags;831 832 spin_lock_irqsave(&i2c_imx->slave_lock, flags);833 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);834 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);835 i2c_imx_slave_handle(i2c_imx, status, ctl);836 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);837 return HRTIMER_NORESTART;838}839 840static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)841{842 int temp;843 844 /* Set slave addr. */845 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);846 847 i2c_imx_reset_regs(i2c_imx);848 849 /* Enable module */850 temp = i2c_imx->hwdata->i2cr_ien_opcode;851 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);852 853 /* Enable interrupt from i2c module */854 temp |= I2CR_IIEN;855 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);856 857 i2c_imx_enable_bus_idle(i2c_imx);858}859 860static int i2c_imx_reg_slave(struct i2c_client *client)861{862 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);863 int ret;864 865 if (i2c_imx->slave)866 return -EBUSY;867 868 i2c_imx->slave = client;869 i2c_imx->last_slave_event = I2C_SLAVE_STOP;870 871 /* Resume */872 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);873 if (ret < 0) {874 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");875 return ret;876 }877 878 i2c_imx_slave_init(i2c_imx);879 880 return 0;881}882 883static int i2c_imx_unreg_slave(struct i2c_client *client)884{885 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);886 int ret;887 888 if (!i2c_imx->slave)889 return -EINVAL;890 891 /* Reset slave address. */892 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);893 894 i2c_imx_reset_regs(i2c_imx);895 896 i2c_imx->slave = NULL;897 898 /* Suspend */899 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);900 if (ret < 0)901 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");902 903 return ret;904}905 906static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status)907{908 /* save status register */909 i2c_imx->i2csr = status;910 wake_up(&i2c_imx->queue);911 912 return IRQ_HANDLED;913}914 915static irqreturn_t i2c_imx_isr(int irq, void *dev_id)916{917 struct imx_i2c_struct *i2c_imx = dev_id;918 unsigned int ctl, status;919 unsigned long flags;920 921 spin_lock_irqsave(&i2c_imx->slave_lock, flags);922 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);923 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);924 925 if (status & I2SR_IIF) {926 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);927 if (i2c_imx->slave) {928 if (!(ctl & I2CR_MSTA)) {929 irqreturn_t ret;930 931 ret = i2c_imx_slave_handle(i2c_imx,932 status, ctl);933 spin_unlock_irqrestore(&i2c_imx->slave_lock,934 flags);935 return ret;936 }937 i2c_imx_slave_finish_op(i2c_imx);938 }939 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);940 return i2c_imx_master_isr(i2c_imx, status);941 }942 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);943 944 return IRQ_NONE;945}946 947static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,948 struct i2c_msg *msgs)949{950 int result;951 unsigned long time_left;952 unsigned int temp = 0;953 unsigned long orig_jiffies = jiffies;954 struct imx_i2c_dma *dma = i2c_imx->dma;955 struct device *dev = &i2c_imx->adapter.dev;956 957 dma->chan_using = dma->chan_tx;958 dma->dma_transfer_dir = DMA_MEM_TO_DEV;959 dma->dma_data_dir = DMA_TO_DEVICE;960 dma->dma_len = msgs->len - 1;961 result = i2c_imx_dma_xfer(i2c_imx, msgs);962 if (result)963 return result;964 965 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);966 temp |= I2CR_DMAEN;967 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);968 969 /*970 * Write slave address.971 * The first byte must be transmitted by the CPU.972 */973 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);974 time_left = wait_for_completion_timeout(975 &i2c_imx->dma->cmd_complete,976 msecs_to_jiffies(DMA_TIMEOUT));977 if (time_left == 0) {978 dmaengine_terminate_sync(dma->chan_using);979 return -ETIMEDOUT;980 }981 982 /* Waiting for transfer complete. */983 while (1) {984 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);985 if (temp & I2SR_ICF)986 break;987 if (time_after(jiffies, orig_jiffies +988 msecs_to_jiffies(DMA_TIMEOUT))) {989 dev_dbg(dev, "<%s> Timeout\n", __func__);990 return -ETIMEDOUT;991 }992 schedule();993 }994 995 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);996 temp &= ~I2CR_DMAEN;997 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);998 999 /* The last data byte must be transferred by the CPU. */1000 imx_i2c_write_reg(msgs->buf[msgs->len-1],1001 i2c_imx, IMX_I2C_I2DR);1002 result = i2c_imx_trx_complete(i2c_imx, false);1003 if (result)1004 return result;1005 1006 return i2c_imx_acked(i2c_imx);1007}1008 1009static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,1010 struct i2c_msg *msgs, bool is_lastmsg)1011{1012 int result;1013 unsigned long time_left;1014 unsigned int temp;1015 unsigned long orig_jiffies = jiffies;1016 struct imx_i2c_dma *dma = i2c_imx->dma;1017 struct device *dev = &i2c_imx->adapter.dev;1018 1019 1020 dma->chan_using = dma->chan_rx;1021 dma->dma_transfer_dir = DMA_DEV_TO_MEM;1022 dma->dma_data_dir = DMA_FROM_DEVICE;1023 /* The last two data bytes must be transferred by the CPU. */1024 dma->dma_len = msgs->len - 2;1025 result = i2c_imx_dma_xfer(i2c_imx, msgs);1026 if (result)1027 return result;1028 1029 time_left = wait_for_completion_timeout(1030 &i2c_imx->dma->cmd_complete,1031 msecs_to_jiffies(DMA_TIMEOUT));1032 if (time_left == 0) {1033 dmaengine_terminate_sync(dma->chan_using);1034 return -ETIMEDOUT;1035 }1036 1037 /* waiting for transfer complete. */1038 while (1) {1039 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);1040 if (temp & I2SR_ICF)1041 break;1042 if (time_after(jiffies, orig_jiffies +1043 msecs_to_jiffies(DMA_TIMEOUT))) {1044 dev_dbg(dev, "<%s> Timeout\n", __func__);1045 return -ETIMEDOUT;1046 }1047 schedule();1048 }1049 1050 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1051 temp &= ~I2CR_DMAEN;1052 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1053 1054 /* read n-1 byte data */1055 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1056 temp |= I2CR_TXAK;1057 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1058 1059 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);1060 /* read n byte data */1061 result = i2c_imx_trx_complete(i2c_imx, false);1062 if (result)1063 return result;1064 1065 if (is_lastmsg) {1066 /*1067 * It must generate STOP before read I2DR to prevent1068 * controller from generating another clock cycle1069 */1070 dev_dbg(dev, "<%s> clear MSTA\n", __func__);1071 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1072 if (!(temp & I2CR_MSTA))1073 i2c_imx->stopped = 1;1074 temp &= ~(I2CR_MSTA | I2CR_MTX);1075 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1076 if (!i2c_imx->stopped)1077 i2c_imx_bus_busy(i2c_imx, 0, false);1078 } else {1079 /*1080 * For i2c master receiver repeat restart operation like:1081 * read -> repeat MSTA -> read/write1082 * The controller must set MTX before read the last byte in1083 * the first read operation, otherwise the first read cost1084 * one extra clock cycle.1085 */1086 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1087 temp |= I2CR_MTX;1088 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1089 }1090 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);1091 1092 return 0;1093}1094 1095static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,1096 bool atomic)1097{1098 int i, result;1099 1100 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",1101 __func__, i2c_8bit_addr_from_msg(msgs));1102 1103 /* write slave address */1104 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);1105 result = i2c_imx_trx_complete(i2c_imx, atomic);1106 if (result)1107 return result;1108 result = i2c_imx_acked(i2c_imx);1109 if (result)1110 return result;1111 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);1112 1113 /* write data */1114 for (i = 0; i < msgs->len; i++) {1115 dev_dbg(&i2c_imx->adapter.dev,1116 "<%s> write byte: B%d=0x%X\n",1117 __func__, i, msgs->buf[i]);1118 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);1119 result = i2c_imx_trx_complete(i2c_imx, atomic);1120 if (result)1121 return result;1122 result = i2c_imx_acked(i2c_imx);1123 if (result)1124 return result;1125 }1126 return 0;1127}1128 1129static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,1130 bool is_lastmsg, bool atomic)1131{1132 int i, result;1133 unsigned int temp;1134 int block_data = msgs->flags & I2C_M_RECV_LEN;1135 int use_dma = i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE &&1136 msgs->len >= DMA_THRESHOLD && !block_data;1137 1138 dev_dbg(&i2c_imx->adapter.dev,1139 "<%s> write slave address: addr=0x%x\n",1140 __func__, i2c_8bit_addr_from_msg(msgs));1141 1142 /* write slave address */1143 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);1144 result = i2c_imx_trx_complete(i2c_imx, atomic);1145 if (result)1146 return result;1147 result = i2c_imx_acked(i2c_imx);1148 if (result)1149 return result;1150 1151 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);1152 1153 /* setup bus to read data */1154 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1155 temp &= ~I2CR_MTX;1156 1157 /*1158 * Reset the I2CR_TXAK flag initially for SMBus block read since the1159 * length is unknown1160 */1161 if ((msgs->len - 1) || block_data)1162 temp &= ~I2CR_TXAK;1163 if (use_dma)1164 temp |= I2CR_DMAEN;1165 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1166 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */1167 1168 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);1169 1170 if (use_dma)1171 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);1172 1173 /* read data */1174 for (i = 0; i < msgs->len; i++) {1175 u8 len = 0;1176 1177 result = i2c_imx_trx_complete(i2c_imx, atomic);1178 if (result)1179 return result;1180 /*1181 * First byte is the length of remaining packet1182 * in the SMBus block data read. Add it to1183 * msgs->len.1184 */1185 if ((!i) && block_data) {1186 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);1187 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))1188 return -EPROTO;1189 dev_dbg(&i2c_imx->adapter.dev,1190 "<%s> read length: 0x%X\n",1191 __func__, len);1192 msgs->len += len;1193 }1194 if (i == (msgs->len - 1)) {1195 if (is_lastmsg) {1196 /*1197 * It must generate STOP before read I2DR to prevent1198 * controller from generating another clock cycle1199 */1200 dev_dbg(&i2c_imx->adapter.dev,1201 "<%s> clear MSTA\n", __func__);1202 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1203 if (!(temp & I2CR_MSTA))1204 i2c_imx->stopped = 1;1205 temp &= ~(I2CR_MSTA | I2CR_MTX);1206 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1207 if (!i2c_imx->stopped)1208 i2c_imx_bus_busy(i2c_imx, 0, atomic);1209 } else {1210 /*1211 * For i2c master receiver repeat restart operation like:1212 * read -> repeat MSTA -> read/write1213 * The controller must set MTX before read the last byte in1214 * the first read operation, otherwise the first read cost1215 * one extra clock cycle.1216 */1217 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1218 temp |= I2CR_MTX;1219 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1220 }1221 } else if (i == (msgs->len - 2)) {1222 dev_dbg(&i2c_imx->adapter.dev,1223 "<%s> set TXAK\n", __func__);1224 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1225 temp |= I2CR_TXAK;1226 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1227 }1228 if ((!i) && block_data)1229 msgs->buf[0] = len;1230 else1231 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);1232 dev_dbg(&i2c_imx->adapter.dev,1233 "<%s> read byte: B%d=0x%X\n",1234 __func__, i, msgs->buf[i]);1235 }1236 return 0;1237}1238 1239static int i2c_imx_xfer_common(struct i2c_adapter *adapter,1240 struct i2c_msg *msgs, int num, bool atomic)1241{1242 unsigned int i, temp;1243 int result;1244 bool is_lastmsg = false;1245 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);1246 1247 /* Start I2C transfer */1248 result = i2c_imx_start(i2c_imx, atomic);1249 if (result) {1250 /*1251 * Bus recovery uses gpiod_get_value_cansleep() which is not1252 * allowed within atomic context.1253 */1254 if (!atomic && i2c_imx->adapter.bus_recovery_info) {1255 i2c_recover_bus(&i2c_imx->adapter);1256 result = i2c_imx_start(i2c_imx, atomic);1257 }1258 }1259 1260 if (result)1261 goto fail0;1262 1263 /* read/write data */1264 for (i = 0; i < num; i++) {1265 if (i == num - 1)1266 is_lastmsg = true;1267 1268 if (i) {1269 dev_dbg(&i2c_imx->adapter.dev,1270 "<%s> repeated start\n", __func__);1271 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1272 temp |= I2CR_RSTA;1273 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);1274 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);1275 if (result)1276 goto fail0;1277 }1278 dev_dbg(&i2c_imx->adapter.dev,1279 "<%s> transfer message: %d\n", __func__, i);1280 /* write/read data */1281#ifdef CONFIG_I2C_DEBUG_BUS1282 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);1283 dev_dbg(&i2c_imx->adapter.dev,1284 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",1285 __func__,1286 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),1287 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),1288 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));1289 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);1290 dev_dbg(&i2c_imx->adapter.dev,1291 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",1292 __func__,1293 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),1294 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),1295 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),1296 (temp & I2SR_RXAK ? 1 : 0));1297#endif1298 if (msgs[i].flags & I2C_M_RD) {1299 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);1300 } else {1301 if (!atomic &&1302 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&1303 msgs[i].flags & I2C_M_DMA_SAFE)1304 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);1305 else1306 result = i2c_imx_write(i2c_imx, &msgs[i], atomic);1307 }1308 if (result)1309 goto fail0;1310 }1311 1312fail0:1313 /* Stop I2C transfer */1314 i2c_imx_stop(i2c_imx, atomic);1315 1316 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,1317 (result < 0) ? "error" : "success msg",1318 (result < 0) ? result : num);1319 /* After data is transferred, switch to slave mode(as a receiver) */1320 if (i2c_imx->slave)1321 i2c_imx_slave_init(i2c_imx);1322 1323 return (result < 0) ? result : num;1324}1325 1326static int i2c_imx_xfer(struct i2c_adapter *adapter,1327 struct i2c_msg *msgs, int num)1328{1329 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);1330 int result;1331 1332 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);1333 if (result < 0)1334 return result;1335 1336 result = i2c_imx_xfer_common(adapter, msgs, num, false);1337 1338 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);1339 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);1340 1341 return result;1342}1343 1344static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,1345 struct i2c_msg *msgs, int num)1346{1347 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);1348 int result;1349 1350 result = clk_enable(i2c_imx->clk);1351 if (result)1352 return result;1353 1354 result = i2c_imx_xfer_common(adapter, msgs, num, true);1355 1356 clk_disable(i2c_imx->clk);1357 1358 return result;1359}1360 1361/*1362 * We switch SCL and SDA to their GPIO function and do some bitbanging1363 * for bus recovery. These alternative pinmux settings can be1364 * described in the device tree by a separate pinctrl state "gpio". If1365 * this is missing this is not a big problem, the only implication is1366 * that we can't do bus recovery.1367 */1368static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,1369 struct platform_device *pdev)1370{1371 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo;1372 1373 bri->pinctrl = devm_pinctrl_get(&pdev->dev);1374 if (IS_ERR(bri->pinctrl))1375 return PTR_ERR(bri->pinctrl);1376 1377 i2c_imx->adapter.bus_recovery_info = bri;1378 1379 return 0;1380}1381 1382static u32 i2c_imx_func(struct i2c_adapter *adapter)1383{1384 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL1385 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;1386}1387 1388static const struct i2c_algorithm i2c_imx_algo = {1389 .master_xfer = i2c_imx_xfer,1390 .master_xfer_atomic = i2c_imx_xfer_atomic,1391 .functionality = i2c_imx_func,1392 .reg_slave = i2c_imx_reg_slave,1393 .unreg_slave = i2c_imx_unreg_slave,1394};1395 1396static int i2c_imx_probe(struct platform_device *pdev)1397{1398 struct imx_i2c_struct *i2c_imx;1399 struct resource *res;1400 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);1401 void __iomem *base;1402 int irq, ret;1403 dma_addr_t phy_addr;1404 const struct imx_i2c_hwdata *match;1405 1406 irq = platform_get_irq(pdev, 0);1407 if (irq < 0)1408 return irq;1409 1410 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);1411 if (IS_ERR(base))1412 return PTR_ERR(base);1413 1414 phy_addr = (dma_addr_t)res->start;1415 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);1416 if (!i2c_imx)1417 return -ENOMEM;1418 1419 spin_lock_init(&i2c_imx->slave_lock);1420 hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);1421 i2c_imx->slave_timer.function = i2c_imx_slave_timeout;1422 1423 match = device_get_match_data(&pdev->dev);1424 if (match)1425 i2c_imx->hwdata = match;1426 else1427 i2c_imx->hwdata = (struct imx_i2c_hwdata *)1428 platform_get_device_id(pdev)->driver_data;1429 1430 /* Setup i2c_imx driver structure */1431 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));1432 i2c_imx->adapter.owner = THIS_MODULE;1433 i2c_imx->adapter.algo = &i2c_imx_algo;1434 i2c_imx->adapter.dev.parent = &pdev->dev;1435 i2c_imx->adapter.nr = pdev->id;1436 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;1437 i2c_imx->base = base;1438 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));1439 1440 /* Get I2C clock */1441 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL);1442 if (IS_ERR(i2c_imx->clk))1443 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),1444 "can't get I2C clock\n");1445 1446 /* Init queue */1447 init_waitqueue_head(&i2c_imx->queue);1448 1449 /* Set up adapter data */1450 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);1451 1452 /* Set up platform driver data */1453 platform_set_drvdata(pdev, i2c_imx);1454 1455 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);1456 pm_runtime_use_autosuspend(&pdev->dev);1457 pm_runtime_set_active(&pdev->dev);1458 pm_runtime_enable(&pdev->dev);1459 1460 ret = pm_runtime_get_sync(&pdev->dev);1461 if (ret < 0)1462 goto rpm_disable;1463 1464 /* Request IRQ */1465 ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED, pdev->name, i2c_imx);1466 if (ret) {1467 dev_err(&pdev->dev, "can't claim irq %d\n", irq);1468 goto rpm_disable;1469 }1470 1471 /* Set up clock divider */1472 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;1473 ret = of_property_read_u32(pdev->dev.of_node,1474 "clock-frequency", &i2c_imx->bitrate);1475 if (ret < 0 && pdata && pdata->bitrate)1476 i2c_imx->bitrate = pdata->bitrate;1477 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;1478 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);1479 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));1480 1481 i2c_imx_reset_regs(i2c_imx);1482 1483 /* Init optional bus recovery function */1484 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);1485 /* Give it another chance if pinctrl used is not ready yet */1486 if (ret == -EPROBE_DEFER)1487 goto clk_notifier_unregister;1488 1489 /* Add I2C adapter */1490 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);1491 if (ret < 0)1492 goto clk_notifier_unregister;1493 1494 pm_runtime_mark_last_busy(&pdev->dev);1495 pm_runtime_put_autosuspend(&pdev->dev);1496 1497 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);1498 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);1499 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",1500 i2c_imx->adapter.name);1501 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");1502 1503 /* Init DMA config if supported */1504 i2c_imx_dma_request(i2c_imx, phy_addr);1505 1506 return 0; /* Return OK */1507 1508clk_notifier_unregister:1509 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);1510 free_irq(irq, i2c_imx);1511rpm_disable:1512 pm_runtime_put_noidle(&pdev->dev);1513 pm_runtime_disable(&pdev->dev);1514 pm_runtime_set_suspended(&pdev->dev);1515 pm_runtime_dont_use_autosuspend(&pdev->dev);1516 return ret;1517}1518 1519static void i2c_imx_remove(struct platform_device *pdev)1520{1521 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);1522 int irq, ret;1523 1524 ret = pm_runtime_get_sync(&pdev->dev);1525 1526 hrtimer_cancel(&i2c_imx->slave_timer);1527 1528 /* remove adapter */1529 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");1530 i2c_del_adapter(&i2c_imx->adapter);1531 1532 if (i2c_imx->dma)1533 i2c_imx_dma_free(i2c_imx);1534 1535 if (ret >= 0) {1536 /* setup chip registers to defaults */1537 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);1538 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);1539 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);1540 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);1541 }1542 1543 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);1544 irq = platform_get_irq(pdev, 0);1545 if (irq >= 0)1546 free_irq(irq, i2c_imx);1547 1548 pm_runtime_put_noidle(&pdev->dev);1549 pm_runtime_disable(&pdev->dev);1550}1551 1552static int i2c_imx_runtime_suspend(struct device *dev)1553{1554 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);1555 1556 clk_disable(i2c_imx->clk);1557 1558 return 0;1559}1560 1561static int i2c_imx_runtime_resume(struct device *dev)1562{1563 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);1564 int ret;1565 1566 ret = clk_enable(i2c_imx->clk);1567 if (ret)1568 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);1569 1570 return ret;1571}1572 1573static const struct dev_pm_ops i2c_imx_pm_ops = {1574 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL)1575};1576 1577static struct platform_driver i2c_imx_driver = {1578 .probe = i2c_imx_probe,1579 .remove_new = i2c_imx_remove,1580 .driver = {1581 .name = DRIVER_NAME,1582 .pm = pm_ptr(&i2c_imx_pm_ops),1583 .of_match_table = i2c_imx_dt_ids,1584 .acpi_match_table = i2c_imx_acpi_ids,1585 },1586 .id_table = imx_i2c_devtype,1587};1588 1589static int __init i2c_adap_imx_init(void)1590{1591 return platform_driver_register(&i2c_imx_driver);1592}1593subsys_initcall(i2c_adap_imx_init);1594 1595static void __exit i2c_adap_imx_exit(void)1596{1597 platform_driver_unregister(&i2c_imx_driver);1598}1599module_exit(i2c_adap_imx_exit);1600 1601MODULE_LICENSE("GPL");1602MODULE_AUTHOR("Darius Augulis");1603MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");1604MODULE_ALIAS("platform:" DRIVER_NAME);1605