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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Loongson-2K/Loongson LS7A I2C controller mode driver4 *5 * Copyright (C) 2013 Loongson Technology Corporation Limited.6 * Copyright (C) 2014-2017 Lemote, Inc.7 * Copyright (C) 2018-2022 Loongson Technology Corporation Limited.8 *9 * Originally written by liushaozong10 * Rewritten for mainline by Binbin Zhou <zhoubinbin@loongson.cn>11 */12 13#include <linux/bits.h>14#include <linux/completion.h>15#include <linux/device.h>16#include <linux/iopoll.h>17#include <linux/i2c.h>18#include <linux/init.h>19#include <linux/interrupt.h>20#include <linux/io.h>21#include <linux/kernel.h>22#include <linux/module.h>23#include <linux/pm_runtime.h>24#include <linux/platform_device.h>25#include <linux/property.h>26#include <linux/units.h>27 28/* I2C Registers */29#define I2C_LS2X_PRER 0x0 /* Freq Division Register(16 bits) */30#define I2C_LS2X_CTR 0x2 /* Control Register */31#define I2C_LS2X_TXR 0x3 /* Transport Data Register */32#define I2C_LS2X_RXR 0x3 /* Receive Data Register */33#define I2C_LS2X_CR 0x4 /* Command Control Register */34#define I2C_LS2X_SR 0x4 /* State Register */35 36/* Command Control Register Bit */37#define LS2X_CR_START BIT(7) /* Start signal */38#define LS2X_CR_STOP BIT(6) /* Stop signal */39#define LS2X_CR_READ BIT(5) /* Read signal */40#define LS2X_CR_WRITE BIT(4) /* Write signal */41#define LS2X_CR_ACK BIT(3) /* Response signal */42#define LS2X_CR_IACK BIT(0) /* Interrupt response signal */43 44/* State Register Bit */45#define LS2X_SR_NOACK BIT(7) /* Receive NACK */46#define LS2X_SR_BUSY BIT(6) /* Bus busy state */47#define LS2X_SR_AL BIT(5) /* Arbitration lost */48#define LS2X_SR_TIP BIT(1) /* Transmission state */49#define LS2X_SR_IF BIT(0) /* Interrupt flag */50 51/* Control Register Bit */52#define LS2X_CTR_EN BIT(7) /* 0: I2c frequency setting 1: Normal */53#define LS2X_CTR_IEN BIT(6) /* Enable i2c interrupt */54#define LS2X_CTR_MST BIT(5) /* 0: Target mode 1: Controller mode */55#define CTR_FREQ_MASK GENMASK(7, 6)56#define CTR_READY_MASK GENMASK(7, 5)57 58/* The PCLK frequency from LPB */59#define LS2X_I2C_PCLK_FREQ (50 * HZ_PER_MHZ)60 61/* The default bus frequency, which is an empirical value */62#define LS2X_I2C_FREQ_STD (33 * HZ_PER_KHZ)63 64struct ls2x_i2c_priv {65 struct i2c_adapter adapter;66 void __iomem *base;67 struct i2c_timings i2c_t;68 struct completion cmd_complete;69};70 71/*72 * Interrupt service routine.73 * This gets called whenever an I2C interrupt occurs.74 */75static irqreturn_t ls2x_i2c_isr(int this_irq, void *dev_id)76{77 struct ls2x_i2c_priv *priv = dev_id;78 79 if (!(readb(priv->base + I2C_LS2X_SR) & LS2X_SR_IF))80 return IRQ_NONE;81 82 writeb(LS2X_CR_IACK, priv->base + I2C_LS2X_CR);83 complete(&priv->cmd_complete);84 return IRQ_HANDLED;85}86 87/*88 * The ls2x i2c controller supports standard mode and fast mode, so the89 * maximum bus frequency is '400kHz'.90 * The bus frequency is set to the empirical value of '33KHz' by default,91 * but it can also be taken from ACPI or FDT for compatibility with more92 * devices.93 */94static void ls2x_i2c_adjust_bus_speed(struct ls2x_i2c_priv *priv)95{96 struct i2c_timings *t = &priv->i2c_t;97 struct device *dev = priv->adapter.dev.parent;98 u32 acpi_speed = i2c_acpi_find_bus_speed(dev);99 100 i2c_parse_fw_timings(dev, t, false);101 102 if (acpi_speed || t->bus_freq_hz)103 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);104 else105 t->bus_freq_hz = LS2X_I2C_FREQ_STD;106 107 /* Calculate and set i2c frequency. */108 writew(LS2X_I2C_PCLK_FREQ / (5 * t->bus_freq_hz) - 1,109 priv->base + I2C_LS2X_PRER);110}111 112static void ls2x_i2c_init(struct ls2x_i2c_priv *priv)113{114 /* Set i2c frequency setting mode and disable interrupts. */115 writeb(readb(priv->base + I2C_LS2X_CTR) & ~CTR_FREQ_MASK,116 priv->base + I2C_LS2X_CTR);117 118 ls2x_i2c_adjust_bus_speed(priv);119 120 /* Set i2c normal operating mode and enable interrupts. */121 writeb(readb(priv->base + I2C_LS2X_CTR) | CTR_READY_MASK,122 priv->base + I2C_LS2X_CTR);123}124 125static int ls2x_i2c_xfer_byte(struct ls2x_i2c_priv *priv, u8 txdata, u8 *rxdatap)126{127 u8 rxdata;128 unsigned long time_left;129 130 writeb(txdata, priv->base + I2C_LS2X_CR);131 132 time_left = wait_for_completion_timeout(&priv->cmd_complete,133 priv->adapter.timeout);134 if (!time_left)135 return -ETIMEDOUT;136 137 rxdata = readb(priv->base + I2C_LS2X_SR);138 if (rxdatap)139 *rxdatap = rxdata;140 141 return 0;142}143 144static int ls2x_i2c_send_byte(struct ls2x_i2c_priv *priv, u8 txdata)145{146 int ret;147 u8 rxdata;148 149 ret = ls2x_i2c_xfer_byte(priv, txdata, &rxdata);150 if (ret)151 return ret;152 153 if (rxdata & LS2X_SR_AL)154 return -EAGAIN;155 156 if (rxdata & LS2X_SR_NOACK)157 return -ENXIO;158 159 return 0;160}161 162static int ls2x_i2c_stop(struct ls2x_i2c_priv *priv)163{164 u8 value;165 166 writeb(LS2X_CR_STOP, priv->base + I2C_LS2X_CR);167 return readb_poll_timeout(priv->base + I2C_LS2X_SR, value,168 !(value & LS2X_SR_BUSY), 100,169 jiffies_to_usecs(priv->adapter.timeout));170}171 172static int ls2x_i2c_start(struct ls2x_i2c_priv *priv, struct i2c_msg *msgs)173{174 reinit_completion(&priv->cmd_complete);175 176 writeb(i2c_8bit_addr_from_msg(msgs), priv->base + I2C_LS2X_TXR);177 return ls2x_i2c_send_byte(priv, LS2X_CR_START | LS2X_CR_WRITE);178}179 180static int ls2x_i2c_rx(struct ls2x_i2c_priv *priv, struct i2c_msg *msg)181{182 int ret;183 u8 rxdata, *buf = msg->buf;184 u16 len = msg->len;185 186 /* Contains steps to send start condition and address. */187 ret = ls2x_i2c_start(priv, msg);188 if (ret)189 return ret;190 191 while (len--) {192 ret = ls2x_i2c_xfer_byte(priv,193 LS2X_CR_READ | (len ? 0 : LS2X_CR_ACK),194 &rxdata);195 if (ret)196 return ret;197 198 *buf++ = readb(priv->base + I2C_LS2X_RXR);199 }200 201 return 0;202}203 204static int ls2x_i2c_tx(struct ls2x_i2c_priv *priv, struct i2c_msg *msg)205{206 int ret;207 u8 *buf = msg->buf;208 u16 len = msg->len;209 210 /* Contains steps to send start condition and address. */211 ret = ls2x_i2c_start(priv, msg);212 if (ret)213 return ret;214 215 while (len--) {216 writeb(*buf++, priv->base + I2C_LS2X_TXR);217 218 ret = ls2x_i2c_send_byte(priv, LS2X_CR_WRITE);219 if (ret)220 return ret;221 }222 223 return 0;224}225 226static int ls2x_i2c_xfer_one(struct ls2x_i2c_priv *priv,227 struct i2c_msg *msg, bool stop)228{229 int ret;230 231 if (msg->flags & I2C_M_RD)232 ret = ls2x_i2c_rx(priv, msg);233 else234 ret = ls2x_i2c_tx(priv, msg);235 236 if (ret < 0) {237 /* Fatel error. Needs reinit. */238 if (ret == -ETIMEDOUT)239 ls2x_i2c_init(priv);240 241 return ret;242 }243 244 if (stop) {245 /* Failed to issue STOP. Needs reinit. */246 ret = ls2x_i2c_stop(priv);247 if (ret)248 ls2x_i2c_init(priv);249 }250 251 return ret;252}253 254static int ls2x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)255{256 int ret;257 struct i2c_msg *msg, *emsg = msgs + num;258 struct ls2x_i2c_priv *priv = i2c_get_adapdata(adap);259 260 for (msg = msgs; msg < emsg; msg++) {261 ret = ls2x_i2c_xfer_one(priv, msg, msg == emsg - 1);262 if (ret)263 return ret;264 }265 266 return num;267}268 269static unsigned int ls2x_i2c_func(struct i2c_adapter *adap)270{271 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;272}273 274static const struct i2c_algorithm ls2x_i2c_algo = {275 .xfer = ls2x_i2c_xfer,276 .functionality = ls2x_i2c_func,277};278 279static int ls2x_i2c_probe(struct platform_device *pdev)280{281 int ret, irq;282 struct i2c_adapter *adap;283 struct ls2x_i2c_priv *priv;284 struct device *dev = &pdev->dev;285 286 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);287 if (!priv)288 return -ENOMEM;289 290 /* Map hardware registers */291 priv->base = devm_platform_ioremap_resource(pdev, 0);292 if (IS_ERR(priv->base))293 return PTR_ERR(priv->base);294 295 irq = platform_get_irq(pdev, 0);296 if (irq < 0)297 return irq;298 299 /* Add the i2c adapter */300 adap = &priv->adapter;301 adap->retries = 5;302 adap->nr = pdev->id;303 adap->dev.parent = dev;304 adap->owner = THIS_MODULE;305 adap->algo = &ls2x_i2c_algo;306 adap->timeout = msecs_to_jiffies(100);307 device_set_node(&adap->dev, dev_fwnode(dev));308 i2c_set_adapdata(adap, priv);309 strscpy(adap->name, pdev->name, sizeof(adap->name));310 init_completion(&priv->cmd_complete);311 platform_set_drvdata(pdev, priv);312 313 ls2x_i2c_init(priv);314 315 ret = devm_request_irq(dev, irq, ls2x_i2c_isr, IRQF_SHARED, "ls2x-i2c",316 priv);317 if (ret < 0)318 return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);319 320 return devm_i2c_add_adapter(dev, adap);321}322 323static int ls2x_i2c_suspend(struct device *dev)324{325 struct ls2x_i2c_priv *priv = dev_get_drvdata(dev);326 327 /* Disable interrupts */328 writeb(readb(priv->base + I2C_LS2X_CTR) & ~LS2X_CTR_IEN,329 priv->base + I2C_LS2X_CTR);330 331 return 0;332}333 334static int ls2x_i2c_resume(struct device *dev)335{336 ls2x_i2c_init(dev_get_drvdata(dev));337 return 0;338}339 340static DEFINE_RUNTIME_DEV_PM_OPS(ls2x_i2c_pm_ops,341 ls2x_i2c_suspend, ls2x_i2c_resume, NULL);342 343static const struct of_device_id ls2x_i2c_id_table[] = {344 { .compatible = "loongson,ls2k-i2c" },345 { .compatible = "loongson,ls7a-i2c" },346 { /* sentinel */ }347};348MODULE_DEVICE_TABLE(of, ls2x_i2c_id_table);349 350static const struct acpi_device_id ls2x_i2c_acpi_match[] = {351 { "LOON0004" }, /* Loongson LS7A */352 { }353};354MODULE_DEVICE_TABLE(acpi, ls2x_i2c_acpi_match);355 356static struct platform_driver ls2x_i2c_driver = {357 .probe = ls2x_i2c_probe,358 .driver = {359 .name = "ls2x-i2c",360 .pm = pm_sleep_ptr(&ls2x_i2c_pm_ops),361 .of_match_table = ls2x_i2c_id_table,362 .acpi_match_table = ls2x_i2c_acpi_match,363 },364};365module_platform_driver(ls2x_i2c_driver);366 367MODULE_DESCRIPTION("Loongson LS2X I2C Bus driver");368MODULE_AUTHOR("Loongson Technology Corporation Limited");369MODULE_LICENSE("GPL");370