2494 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Mellanox BlueField I2C bus driver4 *5 * Copyright (C) 2020 Mellanox Technologies, Ltd.6 */7 8#include <linux/acpi.h>9#include <linux/bitfield.h>10#include <linux/delay.h>11#include <linux/err.h>12#include <linux/interrupt.h>13#include <linux/i2c.h>14#include <linux/io.h>15#include <linux/kernel.h>16#include <linux/module.h>17#include <linux/mutex.h>18#include <linux/of.h>19#include <linux/platform_device.h>20#include <linux/string.h>21 22/* Defines what functionality is present. */23#define MLXBF_I2C_FUNC_SMBUS_BLOCK \24 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL)25 26#define MLXBF_I2C_FUNC_SMBUS_DEFAULT \27 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \28 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \29 I2C_FUNC_SMBUS_PROC_CALL)30 31#define MLXBF_I2C_FUNC_ALL \32 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \33 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE)34 35/* Shared resources info in BlueField platforms. */36 37#define MLXBF_I2C_COALESCE_TYU_ADDR 0x0280130038#define MLXBF_I2C_COALESCE_TYU_SIZE 0x01039 40#define MLXBF_I2C_GPIO_TYU_ADDR 0x0280200041#define MLXBF_I2C_GPIO_TYU_SIZE 0x10042 43#define MLXBF_I2C_COREPLL_TYU_ADDR 0x0280035844#define MLXBF_I2C_COREPLL_TYU_SIZE 0x00845 46#define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c3047#define MLXBF_I2C_COREPLL_YU_SIZE 0x00c48 49#define MLXBF_I2C_COREPLL_RSH_YU_ADDR 0x1340982450#define MLXBF_I2C_COREPLL_RSH_YU_SIZE 0x00c51 52#define MLXBF_I2C_SHARED_RES_MAX 353 54/*55 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses56 * refer to their respective offsets relative to the corresponding57 * memory-mapped region whose addresses are specified in either the DT or58 * the ACPI tables or above.59 */60 61/*62 * SMBus Master core clock frequency. Timing configurations are63 * strongly dependent on the core clock frequency of the SMBus64 * Master. Default value is set to 400MHz.65 */66#define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000)67/* Reference clock for Bluefield - 156 MHz. */68#define MLXBF_I2C_PLL_IN_FREQ 156250000ULL69 70/* Constant used to determine the PLL frequency. */71#define MLNXBF_I2C_COREPLL_CONST 16384ULL72 73#define MLXBF_I2C_FREQUENCY_1GHZ 1000000000ULL74 75/* PLL registers. */76#define MLXBF_I2C_CORE_PLL_REG1 0x477#define MLXBF_I2C_CORE_PLL_REG2 0x878 79/* OR cause register. */80#define MLXBF_I2C_CAUSE_OR_EVTEN0 0x1481#define MLXBF_I2C_CAUSE_OR_CLEAR 0x1882 83/* Arbiter Cause Register. */84#define MLXBF_I2C_CAUSE_ARBITER 0x1c85 86/*87 * Cause Status flags. Note that those bits might be considered88 * as interrupt enabled bits.89 */90 91/* Transaction ended with STOP. */92#define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0)93/* Master arbitration lost. */94#define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1)95/* Unexpected start detected. */96#define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2)97/* Unexpected stop detected. */98#define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3)99/* Wait for transfer continuation. */100#define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4)101/* Failed to generate STOP. */102#define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5)103/* Failed to generate START. */104#define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6)105/* Clock toggle completed. */106#define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7)107/* Transfer timeout occurred. */108#define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8)109/* Master busy bit reset. */110#define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9)111 112#define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0)113 114#define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \115 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \116 MLXBF_I2C_CAUSE_UNEXPECTED_START | \117 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \118 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \119 MLXBF_I2C_CAUSE_PUT_START_FAILED | \120 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \121 MLXBF_I2C_CAUSE_M_FW_TIMEOUT)122 123/*124 * Slave cause status flags. Note that those bits might be considered125 * as interrupt enabled bits.126 */127 128/* Write transaction received successfully. */129#define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0)130/* Read transaction received, waiting for response. */131#define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13)132/* Slave busy bit reset. */133#define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18)134 135/* Cause coalesce registers. */136#define MLXBF_I2C_CAUSE_COALESCE_0 0x00137 138#define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT 3139#define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1140 141/* Functional enable register. */142#define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28143/* Force OE enable register. */144#define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30145/*146 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control147 * SDA/SCL lines:148 *149 * SMBUS GW0 -> bits[26:25]150 * SMBUS GW1 -> bits[28:27]151 * SMBUS GW2 -> bits[30:29]152 */153#define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1))154 155/* Note that gw_id can be 0,1 or 2. */156#define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \157 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))))158 159#define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \160 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num))161 162#define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \163 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))164 165/*166 * Defines SMBus operating frequency and core clock frequency.167 * According to ADB files, default values are compliant to 100KHz SMBus168 * @ 400MHz core clock. The driver should be able to calculate core169 * frequency based on PLL parameters.170 */171#define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ172 173/* Core PLL TYU configuration. */174#define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3)175#define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16)176#define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20)177 178/* Core PLL YU configuration. */179#define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0)180#define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0)181#define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26)182 183/* SMBus timing parameters. */184#define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00185#define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04186#define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08187#define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c188#define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10189#define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14190#define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18191 192#define MLXBF_I2C_SHIFT_0 0193#define MLXBF_I2C_SHIFT_8 8194#define MLXBF_I2C_SHIFT_16 16195#define MLXBF_I2C_SHIFT_24 24196 197#define MLXBF_I2C_MASK_8 GENMASK(7, 0)198#define MLXBF_I2C_MASK_16 GENMASK(15, 0)199 200#define MLXBF_I2C_MST_ADDR_OFFSET 0x200201 202/* SMBus Master GW. */203#define MLXBF_I2C_SMBUS_MASTER_GW 0x0204/* Number of bytes received and sent. */205#define MLXBF_I2C_YU_SMBUS_RS_BYTES 0x100206#define MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES 0x10c207/* Packet error check (PEC) value. */208#define MLXBF_I2C_SMBUS_MASTER_PEC 0x104209/* Status bits (ACK/NACK/FW Timeout). */210#define MLXBF_I2C_SMBUS_MASTER_STATUS 0x108211/* SMbus Master Finite State Machine. */212#define MLXBF_I2C_YU_SMBUS_MASTER_FSM 0x110213#define MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM 0x100214 215/* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */216#define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */217#define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */218#define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */219#define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */220#define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */221#define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */222 223#define MLXBF_I2C_MASTER_ENABLE \224 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \225 MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT)226 227#define MLXBF_I2C_MASTER_ENABLE_WRITE \228 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT)229 230#define MLXBF_I2C_MASTER_ENABLE_READ \231 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT)232 233#define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes */234#define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte when set to 1 */235#define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Control parse expected bytes */236#define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address */237#define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes */238 239/* SMBus master GW Data descriptor. */240#define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x80241#define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */242 243/* Maximum bytes to read/write per SMBus transaction. */244#define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE245#define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1)246 247/* All bytes were transmitted. */248#define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0)249/* NACK received. */250#define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1)251/* Slave's byte count >128 bytes. */252#define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2)253/* Timeout occurred. */254#define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3)255 256#define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0)257 258#define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \259 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \260 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \261 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT)262 263#define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31)264#define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15)265 266#define MLXBF_I2C_SLV_ADDR_OFFSET 0x400267 268/* SMBus slave GW. */269#define MLXBF_I2C_SMBUS_SLAVE_GW 0x0270/* Number of bytes received and sent from/to master. */271#define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x100272/* Packet error check (PEC) value. */273#define MLXBF_I2C_SMBUS_SLAVE_PEC 0x104274/* SMBus slave Finite State Machine (FSM). */275#define MLXBF_I2C_SMBUS_SLAVE_FSM 0x110276/*277 * Should be set when all raised causes handled, and cleared by HW on278 * every new cause.279 */280#define MLXBF_I2C_SMBUS_SLAVE_READY 0x12c281 282/* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */283#define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */284#define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */285 286#define MLXBF_I2C_SLAVE_ENABLE \287 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT)288 289#define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */290#define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */291 292/* SMBus slave GW Data descriptor. */293#define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x80294#define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */295 296/* SMbus slave configuration registers. */297#define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x114298#define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16299#define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT BIT(7)300#define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0)301 302/*303 * Timeout is given in microsends. Note also that timeout handling is not304 * exact.305 */306#define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */307#define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */308 309/* Polling frequency in microseconds. */310#define MLXBF_I2C_POLL_FREQ_IN_USEC 200311 312#define MLXBF_I2C_SMBUS_OP_CNT_1 1313#define MLXBF_I2C_SMBUS_OP_CNT_2 2314#define MLXBF_I2C_SMBUS_OP_CNT_3 3315#define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3316 317/* Helper macro to define an I2C resource parameters. */318#define MLXBF_I2C_RES_PARAMS(addr, size, str) \319 { \320 .start = (addr), \321 .end = (addr) + (size) - 1, \322 .name = (str) \323 }324 325enum {326 MLXBF_I2C_TIMING_100KHZ = 100000,327 MLXBF_I2C_TIMING_400KHZ = 400000,328 MLXBF_I2C_TIMING_1000KHZ = 1000000,329};330 331enum {332 MLXBF_I2C_F_READ = BIT(0),333 MLXBF_I2C_F_WRITE = BIT(1),334 MLXBF_I2C_F_NORESTART = BIT(3),335 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4),336 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5),337 MLXBF_I2C_F_SMBUS_PEC = BIT(6),338 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7),339};340 341/* Mellanox BlueField chip type. */342enum mlxbf_i2c_chip_type {343 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */344 MLXBF_I2C_CHIP_TYPE_2, /* Mellanox BlueField-2 chip. */345 MLXBF_I2C_CHIP_TYPE_3 /* Mellanox BlueField-3 chip. */346};347 348/* List of chip resources that are being accessed by the driver. */349enum {350 MLXBF_I2C_SMBUS_RES,351 MLXBF_I2C_MST_CAUSE_RES,352 MLXBF_I2C_SLV_CAUSE_RES,353 MLXBF_I2C_COALESCE_RES,354 MLXBF_I2C_SMBUS_TIMER_RES,355 MLXBF_I2C_SMBUS_MST_RES,356 MLXBF_I2C_SMBUS_SLV_RES,357 MLXBF_I2C_COREPLL_RES,358 MLXBF_I2C_GPIO_RES,359 MLXBF_I2C_END_RES360};361 362/* Encapsulates timing parameters. */363struct mlxbf_i2c_timings {364 u16 scl_high; /* Clock high period. */365 u16 scl_low; /* Clock low period. */366 u8 sda_rise; /* Data rise time. */367 u8 sda_fall; /* Data fall time. */368 u8 scl_rise; /* Clock rise time. */369 u8 scl_fall; /* Clock fall time. */370 u16 hold_start; /* Hold time after (REPEATED) START. */371 u16 hold_data; /* Data hold time. */372 u16 setup_start; /* REPEATED START condition setup time. */373 u16 setup_stop; /* STOP condition setup time. */374 u16 setup_data; /* Data setup time. */375 u16 pad; /* Padding. */376 u16 buf; /* Bus free time between STOP and START. */377 u16 thigh_max; /* Thigh max. */378 u32 timeout; /* Detect clock low timeout. */379};380 381struct mlxbf_i2c_smbus_operation {382 u32 flags;383 u32 length; /* Buffer length in bytes. */384 u8 *buffer;385};386 387struct mlxbf_i2c_smbus_request {388 u8 slave;389 u8 operation_cnt;390 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT];391};392 393struct mlxbf_i2c_resource {394 void __iomem *io;395 struct resource *params;396 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */397 u8 type;398};399 400struct mlxbf_i2c_chip_info {401 enum mlxbf_i2c_chip_type type;402 /* Chip shared resources that are being used by the I2C controller. */403 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX];404 405 /* Callback to calculate the core PLL frequency. */406 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res);407 408 /* Registers' address offset */409 u32 smbus_master_rs_bytes_off;410 u32 smbus_master_fsm_off;411};412 413struct mlxbf_i2c_priv {414 const struct mlxbf_i2c_chip_info *chip;415 struct i2c_adapter adap;416 struct mlxbf_i2c_resource *smbus;417 struct mlxbf_i2c_resource *timer;418 struct mlxbf_i2c_resource *mst;419 struct mlxbf_i2c_resource *slv;420 struct mlxbf_i2c_resource *mst_cause;421 struct mlxbf_i2c_resource *slv_cause;422 struct mlxbf_i2c_resource *coalesce;423 u64 frequency; /* Core frequency in Hz. */424 int bus; /* Physical bus identifier. */425 int irq;426 struct i2c_client *slave[MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT];427 u32 resource_version;428};429 430/* Core PLL frequency. */431static u64 mlxbf_i2c_corepll_frequency;432 433static struct resource mlxbf_i2c_coalesce_tyu_params =434 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR,435 MLXBF_I2C_COALESCE_TYU_SIZE,436 "COALESCE_MEM");437static struct resource mlxbf_i2c_corepll_tyu_params =438 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR,439 MLXBF_I2C_COREPLL_TYU_SIZE,440 "COREPLL_MEM");441static struct resource mlxbf_i2c_corepll_yu_params =442 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR,443 MLXBF_I2C_COREPLL_YU_SIZE,444 "COREPLL_MEM");445static struct resource mlxbf_i2c_corepll_rsh_yu_params =446 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_RSH_YU_ADDR,447 MLXBF_I2C_COREPLL_RSH_YU_SIZE,448 "COREPLL_MEM");449static struct resource mlxbf_i2c_gpio_tyu_params =450 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR,451 MLXBF_I2C_GPIO_TYU_SIZE,452 "GPIO_MEM");453 454static struct mutex mlxbf_i2c_coalesce_lock;455static struct mutex mlxbf_i2c_corepll_lock;456static struct mutex mlxbf_i2c_gpio_lock;457 458static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = {459 [MLXBF_I2C_CHIP_TYPE_1] = {460 .params = &mlxbf_i2c_coalesce_tyu_params,461 .lock = &mlxbf_i2c_coalesce_lock,462 .type = MLXBF_I2C_COALESCE_RES463 },464 {}465};466 467static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = {468 [MLXBF_I2C_CHIP_TYPE_1] = {469 .params = &mlxbf_i2c_corepll_tyu_params,470 .lock = &mlxbf_i2c_corepll_lock,471 .type = MLXBF_I2C_COREPLL_RES472 },473 [MLXBF_I2C_CHIP_TYPE_2] = {474 .params = &mlxbf_i2c_corepll_yu_params,475 .lock = &mlxbf_i2c_corepll_lock,476 .type = MLXBF_I2C_COREPLL_RES,477 },478 [MLXBF_I2C_CHIP_TYPE_3] = {479 .params = &mlxbf_i2c_corepll_rsh_yu_params,480 .lock = &mlxbf_i2c_corepll_lock,481 .type = MLXBF_I2C_COREPLL_RES,482 }483};484 485static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = {486 [MLXBF_I2C_CHIP_TYPE_1] = {487 .params = &mlxbf_i2c_gpio_tyu_params,488 .lock = &mlxbf_i2c_gpio_lock,489 .type = MLXBF_I2C_GPIO_RES490 },491 {}492};493 494static u8 mlxbf_i2c_bus_count;495 496static struct mutex mlxbf_i2c_bus_lock;497 498/*499 * Function to poll a set of bits at a specific address; it checks whether500 * the bits are equal to zero when eq_zero is set to 'true', and not equal501 * to zero when eq_zero is set to 'false'.502 * Note that the timeout is given in microseconds.503 */504static u32 mlxbf_i2c_poll(void __iomem *io, u32 addr, u32 mask,505 bool eq_zero, u32 timeout)506{507 u32 bits;508 509 timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1;510 511 do {512 bits = readl(io + addr) & mask;513 if (eq_zero ? bits == 0 : bits != 0)514 return eq_zero ? 1 : bits;515 udelay(MLXBF_I2C_POLL_FREQ_IN_USEC);516 } while (timeout-- != 0);517 518 return 0;519}520 521/*522 * SW must make sure that the SMBus Master GW is idle before starting523 * a transaction. Accordingly, this function polls the Master FSM stop524 * bit; it returns false when the bit is asserted, true if not.525 */526static bool mlxbf_i2c_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv)527{528 u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK;529 u32 addr = priv->chip->smbus_master_fsm_off;530 u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT;531 532 if (mlxbf_i2c_poll(priv->mst->io, addr, mask, true, timeout))533 return true;534 535 return false;536}537 538/*539 * wait for the lock to be released before acquiring it.540 */541static bool mlxbf_i2c_smbus_master_lock(struct mlxbf_i2c_priv *priv)542{543 if (mlxbf_i2c_poll(priv->mst->io, MLXBF_I2C_SMBUS_MASTER_GW,544 MLXBF_I2C_MASTER_LOCK_BIT, true,545 MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT))546 return true;547 548 return false;549}550 551static void mlxbf_i2c_smbus_master_unlock(struct mlxbf_i2c_priv *priv)552{553 /* Clear the gw to clear the lock */554 writel(0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW);555}556 557static bool mlxbf_i2c_smbus_transaction_success(u32 master_status,558 u32 cause_status)559{560 /*561 * When transaction ended with STOP, all bytes were transmitted,562 * and no NACK received, then the transaction ended successfully.563 * On the other hand, when the GW is configured with the stop bit564 * de-asserted then the SMBus expects the following GW configuration565 * for transfer continuation.566 */567 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) ||568 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) &&569 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) &&570 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV)))571 return true;572 573 return false;574}575 576/*577 * Poll SMBus master status and return transaction status,578 * i.e. whether succeeded or failed. I2C and SMBus fault codes579 * are returned as negative numbers from most calls, with zero580 * or some positive number indicating a non-fault return.581 */582static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv)583{584 u32 master_status_bits;585 u32 cause_status_bits;586 587 /*588 * GW busy bit is raised by the driver and cleared by the HW589 * when the transaction is completed. The busy bit is a good590 * indicator of transaction status. So poll the busy bit, and591 * then read the cause and master status bits to determine if592 * errors occurred during the transaction.593 */594 mlxbf_i2c_poll(priv->mst->io, MLXBF_I2C_SMBUS_MASTER_GW,595 MLXBF_I2C_MASTER_BUSY_BIT, true,596 MLXBF_I2C_SMBUS_TIMEOUT);597 598 /* Read cause status bits. */599 cause_status_bits = readl(priv->mst_cause->io +600 MLXBF_I2C_CAUSE_ARBITER);601 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK;602 603 /*604 * Parse both Cause and Master GW bits, then return transaction status.605 */606 607 master_status_bits = readl(priv->mst->io +608 MLXBF_I2C_SMBUS_MASTER_STATUS);609 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK;610 611 if (mlxbf_i2c_smbus_transaction_success(master_status_bits,612 cause_status_bits))613 return 0;614 615 /*616 * In case of timeout on GW busy, the ISR will clear busy bit but617 * transaction ended bits cause will not be set so the transaction618 * fails. Then, we must check Master GW status bits.619 */620 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) &&621 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED |622 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL)))623 return -EIO;624 625 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR)626 return -EAGAIN;627 628 return -ETIMEDOUT;629}630 631static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv,632 const u8 *data, u8 length, u32 addr,633 bool is_master)634{635 u8 offset, aligned_length;636 u32 data32;637 638 aligned_length = round_up(length, 4);639 640 /*641 * Copy data bytes from 4-byte aligned source buffer.642 * Data copied to the Master GW Data Descriptor MUST be shifted643 * left so the data starts at the MSB of the descriptor registers644 * as required by the underlying hardware. Enable byte swapping645 * when writing data bytes to the 32 * 32-bit HW Data registers646 * a.k.a Master GW Data Descriptor.647 */648 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) {649 data32 = *((u32 *)(data + offset));650 if (is_master)651 iowrite32be(data32, priv->mst->io + addr + offset);652 else653 iowrite32be(data32, priv->slv->io + addr + offset);654 }655}656 657static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv,658 u8 *data, u8 length, u32 addr,659 bool is_master)660{661 u32 data32, mask;662 u8 byte, offset;663 664 mask = sizeof(u32) - 1;665 666 /*667 * Data bytes in the Master GW Data Descriptor are shifted left668 * so the data starts at the MSB of the descriptor registers as669 * set by the underlying hardware. Enable byte swapping while670 * reading data bytes from the 32 * 32-bit HW Data registers671 * a.k.a Master GW Data Descriptor.672 */673 674 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) {675 if (is_master)676 data32 = ioread32be(priv->mst->io + addr + offset);677 else678 data32 = ioread32be(priv->slv->io + addr + offset);679 *((u32 *)(data + offset)) = data32;680 }681 682 if (!(length & mask))683 return;684 685 if (is_master)686 data32 = ioread32be(priv->mst->io + addr + offset);687 else688 data32 = ioread32be(priv->slv->io + addr + offset);689 690 for (byte = 0; byte < (length & mask); byte++) {691 data[offset + byte] = data32 & GENMASK(7, 0);692 data32 = ror32(data32, MLXBF_I2C_SHIFT_8);693 }694}695 696static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,697 u8 len, u8 block_en, u8 pec_en, bool read)698{699 u32 command;700 701 /* Set Master GW control word. */702 if (read) {703 command = MLXBF_I2C_MASTER_ENABLE_READ;704 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT);705 } else {706 command = MLXBF_I2C_MASTER_ENABLE_WRITE;707 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT);708 }709 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT);710 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT);711 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);712 713 /* Clear status bits. */714 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_STATUS);715 /* Set the cause data. */716 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);717 /* Zero PEC byte. */718 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_PEC);719 /* Zero byte count. */720 writel(0x0, priv->mst->io + priv->chip->smbus_master_rs_bytes_off);721 722 /* GW activation. */723 writel(command, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW);724 725 /*726 * Poll master status and check status bits. An ACK is sent when727 * completing writing data to the bus (Master 'byte_count_done' bit728 * is set to 1).729 */730 return mlxbf_i2c_smbus_check_status(priv);731}732 733static int734mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,735 struct mlxbf_i2c_smbus_request *request)736{737 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 };738 u8 op_idx, data_idx, data_len, write_len, read_len;739 struct mlxbf_i2c_smbus_operation *operation;740 u8 read_en, write_en, block_en, pec_en;741 u8 slave, flags, addr;742 u8 *read_buf;743 int ret = 0;744 745 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT)746 return -EINVAL;747 748 read_buf = NULL;749 data_idx = 0;750 read_en = 0;751 write_en = 0;752 write_len = 0;753 read_len = 0;754 block_en = 0;755 pec_en = 0;756 slave = request->slave & GENMASK(6, 0);757 addr = slave << 1;758 759 /*760 * Try to acquire the smbus gw lock before any reads of the GW register since761 * a read sets the lock.762 */763 if (WARN_ON(!mlxbf_i2c_smbus_master_lock(priv)))764 return -EBUSY;765 766 /* Check whether the HW is idle */767 if (WARN_ON(!mlxbf_i2c_smbus_master_wait_for_idle(priv))) {768 ret = -EBUSY;769 goto out_unlock;770 }771 772 /* Set first byte. */773 data_desc[data_idx++] = addr;774 775 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) {776 operation = &request->operation[op_idx];777 flags = operation->flags;778 779 /*780 * Note that read and write operations might be handled by a781 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set782 * then write command byte and set the optional SMBus specific783 * bits such as block_en and pec_en. These bits MUST be784 * submitted by the first operation only.785 */786 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) {787 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK;788 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC;789 }790 791 if (flags & MLXBF_I2C_F_WRITE) {792 write_en = 1;793 write_len += operation->length;794 if (data_idx + operation->length >795 MLXBF_I2C_MASTER_DATA_DESC_SIZE) {796 ret = -ENOBUFS;797 goto out_unlock;798 }799 memcpy(data_desc + data_idx,800 operation->buffer, operation->length);801 data_idx += operation->length;802 }803 /*804 * We assume that read operations are performed only once per805 * SMBus transaction. *TBD* protect this statement so it won't806 * be executed twice? or return an error if we try to read more807 * than once?808 */809 if (flags & MLXBF_I2C_F_READ) {810 read_en = 1;811 /* Subtract 1 as required by HW. */812 read_len = operation->length - 1;813 read_buf = operation->buffer;814 }815 }816 817 /* Set Master GW data descriptor. */818 data_len = write_len + 1; /* Add one byte of the slave address. */819 /*820 * Note that data_len cannot be 0. Indeed, the slave address byte821 * must be written to the data registers.822 */823 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len,824 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true);825 826 if (write_en) {827 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en,828 pec_en, 0);829 if (ret)830 goto out_unlock;831 }832 833 if (read_en) {834 /* Write slave address to Master GW data descriptor. */835 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1,836 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true);837 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en,838 pec_en, 1);839 if (!ret) {840 /* Get Master GW data descriptor. */841 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1,842 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true);843 844 /* Get data from Master GW data descriptor. */845 memcpy(read_buf, data_desc, read_len + 1);846 }847 848 /*849 * After a read operation the SMBus FSM ps (present state)850 * needs to be 'manually' reset. This should be removed in851 * next tag integration.852 */853 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,854 priv->mst->io + priv->chip->smbus_master_fsm_off);855 }856 857out_unlock:858 mlxbf_i2c_smbus_master_unlock(priv);859 860 return ret;861}862 863/* I2C SMBus protocols. */864 865static void866mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request,867 u8 read)868{869 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;870 871 request->operation[0].length = 0;872 request->operation[0].flags = MLXBF_I2C_F_WRITE;873 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0;874}875 876static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request,877 u8 *data, bool read, bool pec_check)878{879 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;880 881 request->operation[0].length = 1;882 request->operation[0].length += pec_check;883 884 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION;885 request->operation[0].flags |= read ?886 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;887 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;888 889 request->operation[0].buffer = data;890}891 892static void893mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request,894 u8 *command, u8 *data, bool read, bool pec_check)895{896 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;897 898 request->operation[0].length = 1;899 request->operation[0].flags =900 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;901 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;902 request->operation[0].buffer = command;903 904 request->operation[1].length = 1;905 request->operation[1].length += pec_check;906 request->operation[1].flags = read ?907 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;908 request->operation[1].buffer = data;909}910 911static void912mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request,913 u8 *command, u8 *data, bool read, bool pec_check)914{915 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;916 917 request->operation[0].length = 1;918 request->operation[0].flags =919 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;920 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;921 request->operation[0].buffer = command;922 923 request->operation[1].length = 2;924 request->operation[1].length += pec_check;925 request->operation[1].flags = read ?926 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;927 request->operation[1].buffer = data;928}929 930static void931mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request,932 u8 *command, u8 *data, u8 *data_len, bool read,933 bool pec_check)934{935 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;936 937 request->operation[0].length = 1;938 request->operation[0].flags =939 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;940 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;941 request->operation[0].buffer = command;942 943 /*944 * As specified in the standard, the max number of bytes to read/write945 * per block operation is 32 bytes. In Golan code, the controller can946 * read up to 128 bytes and write up to 127 bytes.947 */948 request->operation[1].length =949 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?950 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;951 request->operation[1].flags = read ?952 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;953 /*954 * Skip the first data byte, which corresponds to the number of bytes955 * to read/write.956 */957 request->operation[1].buffer = data + 1;958 959 *data_len = request->operation[1].length;960 961 /* Set the number of byte to read. This will be used by userspace. */962 if (read)963 data[0] = *data_len;964}965 966static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request,967 u8 *command, u8 *data, u8 *data_len,968 bool read, bool pec_check)969{970 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;971 972 request->operation[0].length = 1;973 request->operation[0].flags =974 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;975 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;976 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;977 request->operation[0].buffer = command;978 979 request->operation[1].length =980 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?981 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;982 request->operation[1].flags = read ?983 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;984 request->operation[1].buffer = data + 1;985 986 *data_len = request->operation[1].length;987 988 /* Set the number of bytes to read. This will be used by userspace. */989 if (read)990 data[0] = *data_len;991}992 993static void994mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request,995 u8 *command, u8 *data, bool pec_check)996{997 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;998 999 request->operation[0].length = 1;1000 request->operation[0].flags =1001 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;1002 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;1003 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;1004 request->operation[0].buffer = command;1005 1006 request->operation[1].length = 2;1007 request->operation[1].flags = MLXBF_I2C_F_WRITE;1008 request->operation[1].buffer = data;1009 1010 request->operation[2].length = 3;1011 request->operation[2].flags = MLXBF_I2C_F_READ;1012 request->operation[2].buffer = data;1013}1014 1015static void1016mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request,1017 u8 *command, u8 *data, u8 *data_len,1018 bool pec_check)1019{1020 u32 length;1021 1022 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;1023 1024 request->operation[0].length = 1;1025 request->operation[0].flags =1026 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;1027 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;1028 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0;1029 request->operation[0].buffer = command;1030 1031 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?1032 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;1033 1034 request->operation[1].length = length - pec_check;1035 request->operation[1].flags = MLXBF_I2C_F_WRITE;1036 request->operation[1].buffer = data;1037 1038 request->operation[2].length = length;1039 request->operation[2].flags = MLXBF_I2C_F_READ;1040 request->operation[2].buffer = data;1041 1042 *data_len = length; /* including PEC byte. */1043}1044 1045/* Initialization functions. */1046 1047static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type)1048{1049 return priv->chip->type == type;1050}1051 1052static struct mlxbf_i2c_resource *1053mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type)1054{1055 const struct mlxbf_i2c_chip_info *chip = priv->chip;1056 struct mlxbf_i2c_resource *res;1057 u8 res_idx = 0;1058 1059 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) {1060 res = chip->shared_res[res_idx];1061 if (res && res->type == type)1062 return res;1063 }1064 1065 return NULL;1066}1067 1068static int mlxbf_i2c_init_resource(struct platform_device *pdev,1069 struct mlxbf_i2c_resource **res,1070 u8 type)1071{1072 struct mlxbf_i2c_resource *tmp_res;1073 struct device *dev = &pdev->dev;1074 1075 if (!res || *res || type >= MLXBF_I2C_END_RES)1076 return -EINVAL;1077 1078 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource),1079 GFP_KERNEL);1080 if (!tmp_res)1081 return -ENOMEM;1082 1083 tmp_res->io = devm_platform_get_and_ioremap_resource(pdev, type, &tmp_res->params);1084 if (IS_ERR(tmp_res->io)) {1085 devm_kfree(dev, tmp_res);1086 return PTR_ERR(tmp_res->io);1087 }1088 1089 tmp_res->type = type;1090 1091 *res = tmp_res;1092 1093 return 0;1094}1095 1096static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds,1097 bool minimum)1098{1099 u64 frequency;1100 u32 ticks;1101 1102 /*1103 * Compute ticks as follow:1104 *1105 * Ticks1106 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-91107 * Frequency1108 */1109 frequency = priv->frequency;1110 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ;1111 /*1112 * The number of ticks is rounded down and if minimum is equal to 11113 * then add one tick.1114 */1115 if (minimum)1116 ticks++;1117 1118 return ticks;1119}1120 1121static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt,1122 u32 mask, u8 shift)1123{1124 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift;1125 1126 return val;1127}1128 1129static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,1130 const struct mlxbf_i2c_timings *timings)1131{1132 u32 timer;1133 1134 timer = mlxbf_i2c_set_timer(priv, timings->scl_high,1135 false, MLXBF_I2C_MASK_16,1136 MLXBF_I2C_SHIFT_0);1137 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low,1138 false, MLXBF_I2C_MASK_16,1139 MLXBF_I2C_SHIFT_16);1140 writel(timer, priv->timer->io +1141 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH);1142 1143 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false,1144 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0);1145 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false,1146 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8);1147 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false,1148 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16);1149 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false,1150 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24);1151 writel(timer, priv->timer->io +1152 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE);1153 1154 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true,1155 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);1156 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true,1157 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);1158 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_THOLD);1159 1160 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true,1161 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);1162 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true,1163 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);1164 writel(timer, priv->timer->io +1165 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP);1166 1167 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true,1168 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);1169 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);1170 1171 timer = mlxbf_i2c_set_timer(priv, timings->buf, false,1172 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);1173 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false,1174 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);1175 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);1176 1177 timer = timings->timeout;1178 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);1179}1180 1181enum mlxbf_i2c_timings_config {1182 MLXBF_I2C_TIMING_CONFIG_100KHZ,1183 MLXBF_I2C_TIMING_CONFIG_400KHZ,1184 MLXBF_I2C_TIMING_CONFIG_1000KHZ,1185};1186 1187/*1188 * Note that the mlxbf_i2c_timings->timeout value is not related to the1189 * bus frequency, it is impacted by the time it takes the driver to1190 * complete data transmission before transaction abort.1191 */1192static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = {1193 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = {1194 .scl_high = 4810,1195 .scl_low = 5000,1196 .hold_start = 4000,1197 .setup_start = 4800,1198 .setup_stop = 4000,1199 .setup_data = 250,1200 .sda_rise = 50,1201 .sda_fall = 50,1202 .scl_rise = 50,1203 .scl_fall = 50,1204 .hold_data = 300,1205 .buf = 20000,1206 .thigh_max = 5000,1207 .timeout = 1065001208 },1209 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = {1210 .scl_high = 1011,1211 .scl_low = 1300,1212 .hold_start = 600,1213 .setup_start = 700,1214 .setup_stop = 600,1215 .setup_data = 100,1216 .sda_rise = 50,1217 .sda_fall = 50,1218 .scl_rise = 50,1219 .scl_fall = 50,1220 .hold_data = 300,1221 .buf = 20000,1222 .thigh_max = 5000,1223 .timeout = 1065001224 },1225 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = {1226 .scl_high = 600,1227 .scl_low = 1300,1228 .hold_start = 600,1229 .setup_start = 600,1230 .setup_stop = 600,1231 .setup_data = 100,1232 .sda_rise = 50,1233 .sda_fall = 50,1234 .scl_rise = 50,1235 .scl_fall = 50,1236 .hold_data = 300,1237 .buf = 20000,1238 .thigh_max = 5000,1239 .timeout = 1065001240 }1241};1242 1243static int mlxbf_i2c_init_timings(struct platform_device *pdev,1244 struct mlxbf_i2c_priv *priv)1245{1246 enum mlxbf_i2c_timings_config config_idx;1247 struct device *dev = &pdev->dev;1248 u32 config_khz;1249 1250 int ret;1251 1252 ret = device_property_read_u32(dev, "clock-frequency", &config_khz);1253 if (ret < 0)1254 config_khz = I2C_MAX_STANDARD_MODE_FREQ;1255 1256 switch (config_khz) {1257 default:1258 /* Default settings is 100 KHz. */1259 pr_warn("Illegal value %d: defaulting to 100 KHz\n",1260 config_khz);1261 fallthrough;1262 case I2C_MAX_STANDARD_MODE_FREQ:1263 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ;1264 break;1265 1266 case I2C_MAX_FAST_MODE_FREQ:1267 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ;1268 break;1269 1270 case I2C_MAX_FAST_MODE_PLUS_FREQ:1271 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ;1272 break;1273 }1274 1275 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]);1276 1277 return 0;1278}1279 1280static int mlxbf_i2c_get_gpio(struct platform_device *pdev,1281 struct mlxbf_i2c_priv *priv)1282{1283 struct mlxbf_i2c_resource *gpio_res;1284 struct device *dev = &pdev->dev;1285 struct resource *params;1286 resource_size_t size;1287 1288 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);1289 if (!gpio_res)1290 return -EPERM;1291 1292 /*1293 * The GPIO region in TYU space is shared among I2C busses.1294 * This function MUST be serialized to avoid racing when1295 * claiming the memory region and/or setting up the GPIO.1296 */1297 lockdep_assert_held(gpio_res->lock);1298 1299 /* Check whether the memory map exist. */1300 if (gpio_res->io)1301 return 0;1302 1303 params = gpio_res->params;1304 size = resource_size(params);1305 1306 if (!devm_request_mem_region(dev, params->start, size, params->name))1307 return -EFAULT;1308 1309 gpio_res->io = devm_ioremap(dev, params->start, size);1310 if (!gpio_res->io) {1311 devm_release_mem_region(dev, params->start, size);1312 return -ENOMEM;1313 }1314 1315 return 0;1316}1317 1318static int mlxbf_i2c_release_gpio(struct platform_device *pdev,1319 struct mlxbf_i2c_priv *priv)1320{1321 struct mlxbf_i2c_resource *gpio_res;1322 struct device *dev = &pdev->dev;1323 struct resource *params;1324 1325 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);1326 if (!gpio_res)1327 return 0;1328 1329 mutex_lock(gpio_res->lock);1330 1331 if (gpio_res->io) {1332 /* Release the GPIO resource. */1333 params = gpio_res->params;1334 devm_iounmap(dev, gpio_res->io);1335 devm_release_mem_region(dev, params->start,1336 resource_size(params));1337 }1338 1339 mutex_unlock(gpio_res->lock);1340 1341 return 0;1342}1343 1344static int mlxbf_i2c_get_corepll(struct platform_device *pdev,1345 struct mlxbf_i2c_priv *priv)1346{1347 struct mlxbf_i2c_resource *corepll_res;1348 struct device *dev = &pdev->dev;1349 struct resource *params;1350 resource_size_t size;1351 1352 corepll_res = mlxbf_i2c_get_shared_resource(priv,1353 MLXBF_I2C_COREPLL_RES);1354 if (!corepll_res)1355 return -EPERM;1356 1357 /*1358 * The COREPLL region in TYU space is shared among I2C busses.1359 * This function MUST be serialized to avoid racing when1360 * claiming the memory region.1361 */1362 lockdep_assert_held(corepll_res->lock);1363 1364 /* Check whether the memory map exist. */1365 if (corepll_res->io)1366 return 0;1367 1368 params = corepll_res->params;1369 size = resource_size(params);1370 1371 if (!devm_request_mem_region(dev, params->start, size, params->name))1372 return -EFAULT;1373 1374 corepll_res->io = devm_ioremap(dev, params->start, size);1375 if (!corepll_res->io) {1376 devm_release_mem_region(dev, params->start, size);1377 return -ENOMEM;1378 }1379 1380 return 0;1381}1382 1383static int mlxbf_i2c_release_corepll(struct platform_device *pdev,1384 struct mlxbf_i2c_priv *priv)1385{1386 struct mlxbf_i2c_resource *corepll_res;1387 struct device *dev = &pdev->dev;1388 struct resource *params;1389 1390 corepll_res = mlxbf_i2c_get_shared_resource(priv,1391 MLXBF_I2C_COREPLL_RES);1392 1393 mutex_lock(corepll_res->lock);1394 1395 if (corepll_res->io) {1396 /* Release the CorePLL resource. */1397 params = corepll_res->params;1398 devm_iounmap(dev, corepll_res->io);1399 devm_release_mem_region(dev, params->start,1400 resource_size(params));1401 }1402 1403 mutex_unlock(corepll_res->lock);1404 1405 return 0;1406}1407 1408static int mlxbf_i2c_init_master(struct platform_device *pdev,1409 struct mlxbf_i2c_priv *priv)1410{1411 struct mlxbf_i2c_resource *gpio_res;1412 struct device *dev = &pdev->dev;1413 u32 config_reg;1414 int ret;1415 1416 /* This configuration is only needed for BlueField 1. */1417 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1))1418 return 0;1419 1420 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);1421 if (!gpio_res)1422 return -EPERM;1423 1424 /*1425 * The GPIO region in TYU space is shared among I2C busses.1426 * This function MUST be serialized to avoid racing when1427 * claiming the memory region and/or setting up the GPIO.1428 */1429 1430 mutex_lock(gpio_res->lock);1431 1432 ret = mlxbf_i2c_get_gpio(pdev, priv);1433 if (ret < 0) {1434 dev_err(dev, "Failed to get gpio resource");1435 mutex_unlock(gpio_res->lock);1436 return ret;1437 }1438 1439 /*1440 * TYU - Configuration for GPIO pins. Those pins must be asserted in1441 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must1442 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven1443 * instead of HW_OE.1444 * For now, we do not reset the GPIO state when the driver is removed.1445 * First, it is not necessary to disable the bus since we are using1446 * the same busses. Then, some busses might be shared among Linux and1447 * platform firmware; disabling the bus might compromise the system1448 * functionality.1449 */1450 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);1451 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus,1452 config_reg);1453 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);1454 1455 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);1456 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus,1457 config_reg);1458 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);1459 1460 mutex_unlock(gpio_res->lock);1461 1462 return 0;1463}1464 1465static u64 mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)1466{1467 u64 core_frequency;1468 u8 core_od, core_r;1469 u32 corepll_val;1470 u16 core_f;1471 1472 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);1473 1474 /* Get Core PLL configuration bits. */1475 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_TYU_MASK, corepll_val);1476 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK, corepll_val);1477 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_TYU_MASK, corepll_val);1478 1479 /*1480 * Compute PLL output frequency as follow:1481 *1482 * CORE_F + 11483 * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------1484 * (CORE_R + 1) * (CORE_OD + 1)1485 *1486 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency1487 * and PadFrequency, respectively.1488 */1489 core_frequency = MLXBF_I2C_PLL_IN_FREQ * (++core_f);1490 core_frequency /= (++core_r) * (++core_od);1491 1492 return core_frequency;1493}1494 1495static u64 mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)1496{1497 u32 corepll_reg1_val, corepll_reg2_val;1498 u64 corepll_frequency;1499 u8 core_od, core_r;1500 u32 core_f;1501 1502 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);1503 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);1504 1505 /* Get Core PLL configuration bits */1506 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_YU_MASK, corepll_reg1_val);1507 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_YU_MASK, corepll_reg1_val);1508 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_YU_MASK, corepll_reg2_val);1509 1510 /*1511 * Compute PLL output frequency as follow:1512 *1513 * CORE_F / 163841514 * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------1515 * (CORE_R + 1) * (CORE_OD + 1)1516 *1517 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency1518 * and PadFrequency, respectively.1519 */1520 corepll_frequency = (MLXBF_I2C_PLL_IN_FREQ * core_f) / MLNXBF_I2C_COREPLL_CONST;1521 corepll_frequency /= (++core_r) * (++core_od);1522 1523 return corepll_frequency;1524}1525 1526static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev,1527 struct mlxbf_i2c_priv *priv)1528{1529 const struct mlxbf_i2c_chip_info *chip = priv->chip;1530 struct mlxbf_i2c_resource *corepll_res;1531 struct device *dev = &pdev->dev;1532 u64 *freq = &priv->frequency;1533 int ret;1534 1535 corepll_res = mlxbf_i2c_get_shared_resource(priv,1536 MLXBF_I2C_COREPLL_RES);1537 if (!corepll_res)1538 return -EPERM;1539 1540 /*1541 * First, check whether the TYU core Clock frequency is set.1542 * The TYU core frequency is the same for all I2C busses; when1543 * the first device gets probed the frequency is determined and1544 * stored into a globally visible variable. So, first of all,1545 * check whether the frequency is already set. Here, we assume1546 * that the frequency is expected to be greater than 0.1547 */1548 mutex_lock(corepll_res->lock);1549 if (!mlxbf_i2c_corepll_frequency) {1550 if (!chip->calculate_freq) {1551 mutex_unlock(corepll_res->lock);1552 return -EPERM;1553 }1554 1555 ret = mlxbf_i2c_get_corepll(pdev, priv);1556 if (ret < 0) {1557 dev_err(dev, "Failed to get corePLL resource");1558 mutex_unlock(corepll_res->lock);1559 return ret;1560 }1561 1562 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res);1563 }1564 mutex_unlock(corepll_res->lock);1565 1566 *freq = mlxbf_i2c_corepll_frequency;1567 1568 return 0;1569}1570 1571static int mlxbf_i2c_slave_enable(struct mlxbf_i2c_priv *priv,1572 struct i2c_client *slave)1573{1574 u8 reg, reg_cnt, byte, addr_tmp;1575 u32 slave_reg, slave_reg_tmp;1576 1577 if (!priv)1578 return -EPERM;1579 1580 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;1581 1582 /*1583 * Read the slave registers. There are 4 * 32-bit slave registers.1584 * Each slave register can hold up to 4 * 8-bit slave configuration:1585 * 1) A 7-bit address1586 * 2) And a status bit (1 if enabled, 0 if not).1587 * Look for the next available slave register slot.1588 */1589 for (reg = 0; reg < reg_cnt; reg++) {1590 slave_reg = readl(priv->slv->io +1591 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);1592 /*1593 * Each register holds 4 slave addresses. So, we have to keep1594 * the byte order consistent with the value read in order to1595 * update the register correctly, if needed.1596 */1597 slave_reg_tmp = slave_reg;1598 for (byte = 0; byte < 4; byte++) {1599 addr_tmp = slave_reg_tmp & GENMASK(7, 0);1600 1601 /*1602 * If an enable bit is not set in the1603 * MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG register, then the1604 * slave address slot associated with that bit is1605 * free. So set the enable bit and write the1606 * slave address bits.1607 */1608 if (!(addr_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) {1609 slave_reg &= ~(MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK << (byte * 8));1610 slave_reg |= (slave->addr << (byte * 8));1611 slave_reg |= MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT << (byte * 8);1612 writel(slave_reg, priv->slv->io +1613 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +1614 (reg * 0x4));1615 1616 /*1617 * Set the slave at the corresponding index.1618 */1619 priv->slave[(reg * 4) + byte] = slave;1620 1621 return 0;1622 }1623 1624 /* Parse next byte. */1625 slave_reg_tmp >>= 8;1626 }1627 }1628 1629 return -EBUSY;1630}1631 1632static int mlxbf_i2c_slave_disable(struct mlxbf_i2c_priv *priv, u8 addr)1633{1634 u8 addr_tmp, reg, reg_cnt, byte;1635 u32 slave_reg, slave_reg_tmp;1636 1637 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;1638 1639 /*1640 * Read the slave registers. There are 4 * 32-bit slave registers.1641 * Each slave register can hold up to 4 * 8-bit slave configuration:1642 * 1) A 7-bit address1643 * 2) And a status bit (1 if enabled, 0 if not).1644 * Check if addr is present in the registers.1645 */1646 for (reg = 0; reg < reg_cnt; reg++) {1647 slave_reg = readl(priv->slv->io +1648 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);1649 1650 /* Check whether the address slots are empty. */1651 if (!slave_reg)1652 continue;1653 1654 /*1655 * Check if addr matches any of the 4 slave addresses1656 * in the register.1657 */1658 slave_reg_tmp = slave_reg;1659 for (byte = 0; byte < 4; byte++) {1660 addr_tmp = slave_reg_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;1661 /*1662 * Parse slave address bytes and check whether the1663 * slave address already exists.1664 */1665 if (addr_tmp == addr) {1666 /* Clear the slave address slot. */1667 slave_reg &= ~(GENMASK(7, 0) << (byte * 8));1668 writel(slave_reg, priv->slv->io +1669 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +1670 (reg * 0x4));1671 /* Free slave at the corresponding index */1672 priv->slave[(reg * 4) + byte] = NULL;1673 1674 return 0;1675 }1676 1677 /* Parse next byte. */1678 slave_reg_tmp >>= 8;1679 }1680 }1681 1682 return -ENXIO;1683}1684 1685static int mlxbf_i2c_init_coalesce(struct platform_device *pdev,1686 struct mlxbf_i2c_priv *priv)1687{1688 struct mlxbf_i2c_resource *coalesce_res;1689 struct resource *params;1690 resource_size_t size;1691 int ret = 0;1692 1693 /*1694 * Unlike BlueField-1 platform, the coalesce registers is a dedicated1695 * resource in the next generations of BlueField.1696 */1697 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {1698 coalesce_res = mlxbf_i2c_get_shared_resource(priv,1699 MLXBF_I2C_COALESCE_RES);1700 if (!coalesce_res)1701 return -EPERM;1702 1703 /*1704 * The Cause Coalesce group in TYU space is shared among1705 * I2C busses. This function MUST be serialized to avoid1706 * racing when claiming the memory region.1707 */1708 lockdep_assert_held(mlxbf_i2c_gpio_res->lock);1709 1710 /* Check whether the memory map exist. */1711 if (coalesce_res->io) {1712 priv->coalesce = coalesce_res;1713 return 0;1714 }1715 1716 params = coalesce_res->params;1717 size = resource_size(params);1718 1719 if (!request_mem_region(params->start, size, params->name))1720 return -EFAULT;1721 1722 coalesce_res->io = ioremap(params->start, size);1723 if (!coalesce_res->io) {1724 release_mem_region(params->start, size);1725 return -ENOMEM;1726 }1727 1728 priv->coalesce = coalesce_res;1729 1730 } else {1731 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce,1732 MLXBF_I2C_COALESCE_RES);1733 }1734 1735 return ret;1736}1737 1738static int mlxbf_i2c_release_coalesce(struct platform_device *pdev,1739 struct mlxbf_i2c_priv *priv)1740{1741 struct mlxbf_i2c_resource *coalesce_res;1742 struct device *dev = &pdev->dev;1743 struct resource *params;1744 resource_size_t size;1745 1746 coalesce_res = priv->coalesce;1747 1748 if (coalesce_res->io) {1749 params = coalesce_res->params;1750 size = resource_size(params);1751 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {1752 mutex_lock(coalesce_res->lock);1753 iounmap(coalesce_res->io);1754 release_mem_region(params->start, size);1755 mutex_unlock(coalesce_res->lock);1756 } else {1757 devm_release_mem_region(dev, params->start, size);1758 }1759 }1760 1761 return 0;1762}1763 1764static int mlxbf_i2c_init_slave(struct platform_device *pdev,1765 struct mlxbf_i2c_priv *priv)1766{1767 struct device *dev = &pdev->dev;1768 u32 int_reg;1769 int ret;1770 1771 /* Reset FSM. */1772 writel(0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_FSM);1773 1774 /*1775 * Enable slave cause interrupt bits. Drive1776 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and1777 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external1778 * masters issue a Read and Write, respectively. But, clear all1779 * interrupts first.1780 */1781 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);1782 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE;1783 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS;1784 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);1785 1786 /* Finally, set the 'ready' bit to start handling transactions. */1787 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);1788 1789 /* Initialize the cause coalesce resource. */1790 ret = mlxbf_i2c_init_coalesce(pdev, priv);1791 if (ret < 0) {1792 dev_err(dev, "failed to initialize cause coalesce\n");1793 return ret;1794 }1795 1796 return 0;1797}1798 1799static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read,1800 bool *write)1801{1802 const struct mlxbf_i2c_chip_info *chip = priv->chip;1803 u32 coalesce0_reg, cause_reg;1804 u8 slave_shift, is_set;1805 1806 *write = false;1807 *read = false;1808 1809 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ?1810 MLXBF_I2C_CAUSE_YU_SLAVE_BIT :1811 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT;1812 1813 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0);1814 is_set = coalesce0_reg & (1 << slave_shift);1815 1816 if (!is_set)1817 return false;1818 1819 /* Check the source of the interrupt, i.e. whether a Read or Write. */1820 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER);1821 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE)1822 *read = true;1823 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS)1824 *write = true;1825 1826 /* Clear cause bits. */1827 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);1828 1829 return true;1830}1831 1832static bool mlxbf_i2c_slave_wait_for_idle(struct mlxbf_i2c_priv *priv,1833 u32 timeout)1834{1835 u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL;1836 u32 addr = MLXBF_I2C_CAUSE_ARBITER;1837 1838 if (mlxbf_i2c_poll(priv->slv_cause->io, addr, mask, false, timeout))1839 return true;1840 1841 return false;1842}1843 1844static struct i2c_client *mlxbf_i2c_get_slave_from_addr(1845 struct mlxbf_i2c_priv *priv, u8 addr)1846{1847 int i;1848 1849 for (i = 0; i < MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT; i++) {1850 if (!priv->slave[i])1851 continue;1852 1853 if (priv->slave[i]->addr == addr)1854 return priv->slave[i];1855 }1856 1857 return NULL;1858}1859 1860/*1861 * Send byte to 'external' smbus master. This function is executed when1862 * an external smbus master wants to read data from the BlueField.1863 */1864static int mlxbf_i2c_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)1865{1866 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };1867 u8 write_size, pec_en, addr, value, byte_cnt;1868 struct i2c_client *slave;1869 u32 control32, data32;1870 int ret = 0;1871 1872 /*1873 * Read the first byte received from the external master to1874 * determine the slave address. This byte is located in the1875 * first data descriptor register of the slave GW.1876 */1877 data32 = ioread32be(priv->slv->io +1878 MLXBF_I2C_SLAVE_DATA_DESC_ADDR);1879 addr = (data32 & GENMASK(7, 0)) >> 1;1880 1881 /*1882 * Check if the slave address received in the data descriptor register1883 * matches any of the slave addresses registered. If there is a match,1884 * set the slave.1885 */1886 slave = mlxbf_i2c_get_slave_from_addr(priv, addr);1887 if (!slave) {1888 ret = -ENXIO;1889 goto clear_csr;1890 }1891 1892 /*1893 * An I2C read can consist of a WRITE bit transaction followed by1894 * a READ bit transaction. Indeed, slave devices often expect1895 * the slave address to be followed by the internal address.1896 * So, write the internal address byte first, and then, send the1897 * requested data to the master.1898 */1899 if (recv_bytes > 1) {1900 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);1901 value = (data32 >> 8) & GENMASK(7, 0);1902 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,1903 &value);1904 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);1905 1906 if (ret < 0)1907 goto clear_csr;1908 }1909 1910 /*1911 * Send data to the master. Currently, the driver supports1912 * READ_BYTE, READ_WORD and BLOCK READ protocols. The1913 * hardware can send up to 128 bytes per transfer which is1914 * the total size of the data registers.1915 */1916 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);1917 1918 for (byte_cnt = 0; byte_cnt < MLXBF_I2C_SLAVE_DATA_DESC_SIZE; byte_cnt++) {1919 data_desc[byte_cnt] = value;1920 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);1921 }1922 1923 /* Send a stop condition to the backend. */1924 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);1925 1926 /* Set the number of bytes to write to master. */1927 write_size = (byte_cnt - 1) & 0x7f;1928 1929 /* Write data to Slave GW data descriptor. */1930 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt,1931 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false);1932 1933 pec_en = 0; /* Disable PEC since it is not supported. */1934 1935 /* Prepare control word. */1936 control32 = MLXBF_I2C_SLAVE_ENABLE;1937 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);1938 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);1939 1940 writel(control32, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_GW);1941 1942 /*1943 * Wait until the transfer is completed; the driver will wait1944 * until the GW is idle, a cause will rise on fall of GW busy.1945 */1946 mlxbf_i2c_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);1947 1948clear_csr:1949 /* Release the Slave GW. */1950 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);1951 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC);1952 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);1953 1954 return ret;1955}1956 1957/*1958 * Receive bytes from 'external' smbus master. This function is executed when1959 * an external smbus master wants to write data to the BlueField.1960 */1961static int mlxbf_i2c_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)1962{1963 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };1964 struct i2c_client *slave;1965 u8 value, byte, addr;1966 int ret = 0;1967 1968 /* Read data from Slave GW data descriptor. */1969 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes,1970 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false);1971 addr = data_desc[0] >> 1;1972 1973 /*1974 * Check if the slave address received in the data descriptor register1975 * matches any of the slave addresses registered.1976 */1977 slave = mlxbf_i2c_get_slave_from_addr(priv, addr);1978 if (!slave) {1979 ret = -EINVAL;1980 goto clear_csr;1981 }1982 1983 /*1984 * Notify the slave backend that an smbus master wants to write data1985 * to the BlueField.1986 */1987 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);1988 1989 /* Send the received data to the slave backend. */1990 for (byte = 1; byte < recv_bytes; byte++) {1991 value = data_desc[byte];1992 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,1993 &value);1994 if (ret < 0)1995 break;1996 }1997 1998 /*1999 * Send a stop event to the slave backend, to signal2000 * the end of the write transactions.2001 */2002 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);2003 2004clear_csr:2005 /* Release the Slave GW. */2006 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);2007 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC);2008 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);2009 2010 return ret;2011}2012 2013static irqreturn_t mlxbf_i2c_irq(int irq, void *ptr)2014{2015 struct mlxbf_i2c_priv *priv = ptr;2016 bool read, write, irq_is_set;2017 u32 rw_bytes_reg;2018 u8 recv_bytes;2019 2020 /*2021 * Read TYU interrupt register and determine the source of the2022 * interrupt. Based on the source of the interrupt one of the2023 * following actions are performed:2024 * - Receive data and send response to master.2025 * - Send data and release slave GW.2026 *2027 * Handle read/write transaction only. CRmaster and Iarp requests2028 * are ignored for now.2029 */2030 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write);2031 if (!irq_is_set || (!read && !write)) {2032 /* Nothing to do here, interrupt was not from this device. */2033 return IRQ_NONE;2034 }2035 2036 /*2037 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of2038 * bytes from/to master. These are defined by 8-bits each. If the lower2039 * 8 bits are set, then the master expect to read N bytes from the2040 * slave, if the higher 8 bits are sent then the slave expect N bytes2041 * from the master.2042 */2043 rw_bytes_reg = readl(priv->slv->io +2044 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);2045 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);2046 2047 /*2048 * For now, the slave supports 128 bytes transfer. Discard remaining2049 * data bytes if the master wrote more than2050 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave2051 * data descriptor.2052 *2053 * Note that we will never expect to transfer more than 128 bytes; as2054 * specified in the SMBus standard, block transactions cannot exceed2055 * 32 bytes.2056 */2057 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ?2058 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes;2059 2060 if (read)2061 mlxbf_i2c_irq_send(priv, recv_bytes);2062 else2063 mlxbf_i2c_irq_recv(priv, recv_bytes);2064 2065 return IRQ_HANDLED;2066}2067 2068/* Return negative errno on error. */2069static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,2070 unsigned short flags, char read_write,2071 u8 command, int size,2072 union i2c_smbus_data *data)2073{2074 struct mlxbf_i2c_smbus_request request = { 0 };2075 struct mlxbf_i2c_priv *priv;2076 bool read, pec;2077 u8 byte_cnt;2078 2079 request.slave = addr;2080 2081 read = (read_write == I2C_SMBUS_READ);2082 pec = flags & I2C_FUNC_SMBUS_PEC;2083 2084 switch (size) {2085 case I2C_SMBUS_QUICK:2086 mlxbf_i2c_smbus_quick_command(&request, read);2087 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr);2088 break;2089 2090 case I2C_SMBUS_BYTE:2091 mlxbf_i2c_smbus_byte_func(&request,2092 read ? &data->byte : &command, read,2093 pec);2094 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n",2095 read ? "read" : "write", addr);2096 break;2097 2098 case I2C_SMBUS_BYTE_DATA:2099 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte,2100 read, pec);2101 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n",2102 read ? "read" : "write", command, addr);2103 break;2104 2105 case I2C_SMBUS_WORD_DATA:2106 mlxbf_i2c_smbus_data_word_func(&request, &command,2107 (u8 *)&data->word, read, pec);2108 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n",2109 read ? "read" : "write", command, addr);2110 break;2111 2112 case I2C_SMBUS_I2C_BLOCK_DATA:2113 byte_cnt = data->block[0];2114 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block,2115 &byte_cnt, read, pec);2116 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",2117 read ? "read" : "write", byte_cnt, command, addr);2118 break;2119 2120 case I2C_SMBUS_BLOCK_DATA:2121 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0];2122 mlxbf_i2c_smbus_block_func(&request, &command, data->block,2123 &byte_cnt, read, pec);2124 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",2125 read ? "read" : "write", byte_cnt, command, addr);2126 break;2127 2128 case I2C_FUNC_SMBUS_PROC_CALL:2129 mlxbf_i2c_smbus_process_call_func(&request, &command,2130 (u8 *)&data->word, pec);2131 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n",2132 command, addr);2133 break;2134 2135 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL:2136 byte_cnt = data->block[0];2137 mlxbf_i2c_smbus_blk_process_call_func(&request, &command,2138 data->block, &byte_cnt,2139 pec);2140 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n",2141 byte_cnt, addr);2142 break;2143 2144 default:2145 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n",2146 size);2147 return -EOPNOTSUPP;2148 }2149 2150 priv = i2c_get_adapdata(adap);2151 2152 return mlxbf_i2c_smbus_start_transaction(priv, &request);2153}2154 2155static int mlxbf_i2c_reg_slave(struct i2c_client *slave)2156{2157 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);2158 struct device *dev = &slave->dev;2159 int ret;2160 2161 /*2162 * Do not support ten bit chip address and do not use Packet Error2163 * Checking (PEC).2164 */2165 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) {2166 dev_err(dev, "SMBus PEC and 10 bit address not supported\n");2167 return -EAFNOSUPPORT;2168 }2169 2170 ret = mlxbf_i2c_slave_enable(priv, slave);2171 if (ret)2172 dev_err(dev, "Surpassed max number of registered slaves allowed\n");2173 2174 return 0;2175}2176 2177static int mlxbf_i2c_unreg_slave(struct i2c_client *slave)2178{2179 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);2180 struct device *dev = &slave->dev;2181 int ret;2182 2183 /*2184 * Unregister slave by:2185 * 1) Disabling the slave address in hardware2186 * 2) Freeing priv->slave at the corresponding index2187 */2188 ret = mlxbf_i2c_slave_disable(priv, slave->addr);2189 if (ret)2190 dev_err(dev, "Unable to find slave 0x%x\n", slave->addr);2191 2192 return ret;2193}2194 2195static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap)2196{2197 return MLXBF_I2C_FUNC_ALL;2198}2199 2200static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = {2201 [MLXBF_I2C_CHIP_TYPE_1] = {2202 .type = MLXBF_I2C_CHIP_TYPE_1,2203 .shared_res = {2204 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1],2205 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1],2206 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1]2207 },2208 .calculate_freq = mlxbf_i2c_calculate_freq_from_tyu,2209 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES,2210 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM2211 },2212 [MLXBF_I2C_CHIP_TYPE_2] = {2213 .type = MLXBF_I2C_CHIP_TYPE_2,2214 .shared_res = {2215 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2]2216 },2217 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu,2218 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES,2219 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM2220 },2221 [MLXBF_I2C_CHIP_TYPE_3] = {2222 .type = MLXBF_I2C_CHIP_TYPE_3,2223 .shared_res = {2224 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_3]2225 },2226 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu,2227 .smbus_master_rs_bytes_off = MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES,2228 .smbus_master_fsm_off = MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM2229 }2230};2231 2232static const struct i2c_algorithm mlxbf_i2c_algo = {2233 .smbus_xfer = mlxbf_i2c_smbus_xfer,2234 .functionality = mlxbf_i2c_functionality,2235 .reg_slave = mlxbf_i2c_reg_slave,2236 .unreg_slave = mlxbf_i2c_unreg_slave,2237};2238 2239static struct i2c_adapter_quirks mlxbf_i2c_quirks = {2240 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH,2241 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH,2242};2243 2244static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = {2245 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] },2246 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] },2247 { "MLNXBF31", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_3] },2248 {},2249};2250 2251MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids);2252 2253static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)2254{2255 const struct acpi_device_id *aid;2256 u64 bus_id;2257 int ret;2258 2259 if (acpi_disabled)2260 return -ENOENT;2261 2262 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev);2263 if (!aid)2264 return -ENODEV;2265 2266 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data;2267 2268 ret = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &bus_id);2269 if (ret) {2270 dev_err(dev, "Cannot retrieve UID\n");2271 return ret;2272 }2273 2274 priv->bus = bus_id;2275 2276 return 0;2277}2278 2279static int mlxbf_i2c_probe(struct platform_device *pdev)2280{2281 struct device *dev = &pdev->dev;2282 struct mlxbf_i2c_priv *priv;2283 struct i2c_adapter *adap;2284 u32 resource_version;2285 int irq, ret;2286 2287 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL);2288 if (!priv)2289 return -ENOMEM;2290 2291 ret = mlxbf_i2c_acpi_probe(dev, priv);2292 if (ret < 0)2293 return ret;2294 2295 /* This property allows the driver to stay backward compatible with older2296 * ACPI tables.2297 * Starting BlueField-3 SoC, the "smbus" resource was broken down into 32298 * separate resources "timer", "master" and "slave".2299 */2300 if (device_property_read_u32(dev, "resource_version", &resource_version))2301 resource_version = 0;2302 2303 priv->resource_version = resource_version;2304 2305 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && resource_version == 0) {2306 priv->timer = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL);2307 if (!priv->timer)2308 return -ENOMEM;2309 2310 priv->mst = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL);2311 if (!priv->mst)2312 return -ENOMEM;2313 2314 priv->slv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL);2315 if (!priv->slv)2316 return -ENOMEM;2317 2318 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus,2319 MLXBF_I2C_SMBUS_RES);2320 if (ret < 0)2321 return dev_err_probe(dev, ret, "Cannot fetch smbus resource info");2322 2323 priv->timer->io = priv->smbus->io;2324 priv->mst->io = priv->smbus->io + MLXBF_I2C_MST_ADDR_OFFSET;2325 priv->slv->io = priv->smbus->io + MLXBF_I2C_SLV_ADDR_OFFSET;2326 } else {2327 ret = mlxbf_i2c_init_resource(pdev, &priv->timer,2328 MLXBF_I2C_SMBUS_TIMER_RES);2329 if (ret < 0)2330 return dev_err_probe(dev, ret, "Cannot fetch timer resource info");2331 2332 ret = mlxbf_i2c_init_resource(pdev, &priv->mst,2333 MLXBF_I2C_SMBUS_MST_RES);2334 if (ret < 0)2335 return dev_err_probe(dev, ret, "Cannot fetch master resource info");2336 2337 ret = mlxbf_i2c_init_resource(pdev, &priv->slv,2338 MLXBF_I2C_SMBUS_SLV_RES);2339 if (ret < 0)2340 return dev_err_probe(dev, ret, "Cannot fetch slave resource info");2341 }2342 2343 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause,2344 MLXBF_I2C_MST_CAUSE_RES);2345 if (ret < 0)2346 return dev_err_probe(dev, ret, "Cannot fetch cause master resource info");2347 2348 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause,2349 MLXBF_I2C_SLV_CAUSE_RES);2350 if (ret < 0)2351 return dev_err_probe(dev, ret, "Cannot fetch cause slave resource info");2352 2353 adap = &priv->adap;2354 adap->owner = THIS_MODULE;2355 adap->class = I2C_CLASS_HWMON;2356 adap->algo = &mlxbf_i2c_algo;2357 adap->quirks = &mlxbf_i2c_quirks;2358 adap->dev.parent = dev;2359 adap->dev.of_node = dev->of_node;2360 adap->nr = priv->bus;2361 2362 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr);2363 i2c_set_adapdata(adap, priv);2364 2365 /* Read Core PLL frequency. */2366 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv);2367 if (ret < 0) {2368 dev_err(dev, "cannot get core clock frequency\n");2369 /* Set to default value. */2370 priv->frequency = MLXBF_I2C_COREPLL_FREQ;2371 }2372 2373 /*2374 * Initialize master.2375 * Note that a physical bus might be shared among Linux and firmware2376 * (e.g., ATF). Thus, the bus should be initialized and ready and2377 * bus initialization would be unnecessary. This requires additional2378 * knowledge about physical busses. But, since an extra initialization2379 * does not really hurt, then keep the code as is.2380 */2381 ret = mlxbf_i2c_init_master(pdev, priv);2382 if (ret < 0)2383 return dev_err_probe(dev, ret, "failed to initialize smbus master %d",2384 priv->bus);2385 2386 mlxbf_i2c_init_timings(pdev, priv);2387 2388 mlxbf_i2c_init_slave(pdev, priv);2389 2390 irq = platform_get_irq(pdev, 0);2391 if (irq < 0)2392 return irq;2393 ret = devm_request_irq(dev, irq, mlxbf_i2c_irq,2394 IRQF_SHARED | IRQF_PROBE_SHARED,2395 dev_name(dev), priv);2396 if (ret < 0)2397 return dev_err_probe(dev, ret, "Cannot get irq %d\n", irq);2398 2399 priv->irq = irq;2400 2401 platform_set_drvdata(pdev, priv);2402 2403 ret = i2c_add_numbered_adapter(adap);2404 if (ret < 0)2405 return ret;2406 2407 mutex_lock(&mlxbf_i2c_bus_lock);2408 mlxbf_i2c_bus_count++;2409 mutex_unlock(&mlxbf_i2c_bus_lock);2410 2411 return 0;2412}2413 2414static void mlxbf_i2c_remove(struct platform_device *pdev)2415{2416 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev);2417 struct device *dev = &pdev->dev;2418 struct resource *params;2419 2420 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && priv->resource_version == 0) {2421 params = priv->smbus->params;2422 devm_release_mem_region(dev, params->start, resource_size(params));2423 } else {2424 params = priv->timer->params;2425 devm_release_mem_region(dev, params->start, resource_size(params));2426 2427 params = priv->mst->params;2428 devm_release_mem_region(dev, params->start, resource_size(params));2429 2430 params = priv->slv->params;2431 devm_release_mem_region(dev, params->start, resource_size(params));2432 }2433 2434 params = priv->mst_cause->params;2435 devm_release_mem_region(dev, params->start, resource_size(params));2436 2437 params = priv->slv_cause->params;2438 devm_release_mem_region(dev, params->start, resource_size(params));2439 2440 /*2441 * Release shared resources. This should be done when releasing2442 * the I2C controller.2443 */2444 mutex_lock(&mlxbf_i2c_bus_lock);2445 if (--mlxbf_i2c_bus_count == 0) {2446 mlxbf_i2c_release_coalesce(pdev, priv);2447 mlxbf_i2c_release_corepll(pdev, priv);2448 mlxbf_i2c_release_gpio(pdev, priv);2449 }2450 mutex_unlock(&mlxbf_i2c_bus_lock);2451 2452 devm_free_irq(dev, priv->irq, priv);2453 2454 i2c_del_adapter(&priv->adap);2455}2456 2457static struct platform_driver mlxbf_i2c_driver = {2458 .probe = mlxbf_i2c_probe,2459 .remove_new = mlxbf_i2c_remove,2460 .driver = {2461 .name = "i2c-mlxbf",2462 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids),2463 },2464};2465 2466static int __init mlxbf_i2c_init(void)2467{2468 mutex_init(&mlxbf_i2c_coalesce_lock);2469 mutex_init(&mlxbf_i2c_corepll_lock);2470 mutex_init(&mlxbf_i2c_gpio_lock);2471 2472 mutex_init(&mlxbf_i2c_bus_lock);2473 2474 return platform_driver_register(&mlxbf_i2c_driver);2475}2476module_init(mlxbf_i2c_init);2477 2478static void __exit mlxbf_i2c_exit(void)2479{2480 platform_driver_unregister(&mlxbf_i2c_driver);2481 2482 mutex_destroy(&mlxbf_i2c_bus_lock);2483 2484 mutex_destroy(&mlxbf_i2c_gpio_lock);2485 mutex_destroy(&mlxbf_i2c_corepll_lock);2486 mutex_destroy(&mlxbf_i2c_coalesce_lock);2487}2488module_exit(mlxbf_i2c_exit);2489 2490MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver");2491MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>");2492MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");2493MODULE_LICENSE("GPL v2");2494