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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Freescale MXS I2C bus driver4 *5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.7 *8 * based on a (non-working) driver which was:9 *10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.11 */12 13#include <linux/slab.h>14#include <linux/device.h>15#include <linux/module.h>16#include <linux/i2c.h>17#include <linux/err.h>18#include <linux/interrupt.h>19#include <linux/completion.h>20#include <linux/platform_device.h>21#include <linux/jiffies.h>22#include <linux/io.h>23#include <linux/stmp_device.h>24#include <linux/of.h>25#include <linux/dma-mapping.h>26#include <linux/dmaengine.h>27#include <linux/dma/mxs-dma.h>28 29#define DRIVER_NAME "mxs-i2c"30 31#define MXS_I2C_CTRL0 (0x00)32#define MXS_I2C_CTRL0_SET (0x04)33#define MXS_I2C_CTRL0_CLR (0x08)34 35#define MXS_I2C_CTRL0_SFTRST 0x8000000036#define MXS_I2C_CTRL0_RUN 0x2000000037#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x0200000038#define MXS_I2C_CTRL0_PIO_MODE 0x0100000039#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x0020000040#define MXS_I2C_CTRL0_POST_SEND_STOP 0x0010000041#define MXS_I2C_CTRL0_PRE_SEND_START 0x0008000042#define MXS_I2C_CTRL0_MASTER_MODE 0x0002000043#define MXS_I2C_CTRL0_DIRECTION 0x0001000044#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)45 46#define MXS_I2C_TIMING0 (0x10)47#define MXS_I2C_TIMING1 (0x20)48#define MXS_I2C_TIMING2 (0x30)49 50#define MXS_I2C_CTRL1 (0x40)51#define MXS_I2C_CTRL1_SET (0x44)52#define MXS_I2C_CTRL1_CLR (0x48)53 54#define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x1000000055#define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x8056#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x4057#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x2058#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x1059#define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x0860#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x0461#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x0262#define MXS_I2C_CTRL1_SLAVE_IRQ 0x0163 64#define MXS_I2C_STAT (0x50)65#define MXS_I2C_STAT_GOT_A_NAK 0x1000000066#define MXS_I2C_STAT_BUS_BUSY 0x0000080067#define MXS_I2C_STAT_CLK_GEN_BUSY 0x0000040068 69#define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)70 71#define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)72 73#define MXS_I2C_DEBUG0_DMAREQ 0x8000000074 75#define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \76 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \77 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \78 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \79 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \80 MXS_I2C_CTRL1_SLAVE_IRQ)81 82 83#define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \84 MXS_I2C_CTRL0_PRE_SEND_START | \85 MXS_I2C_CTRL0_MASTER_MODE | \86 MXS_I2C_CTRL0_DIRECTION | \87 MXS_I2C_CTRL0_XFER_COUNT(1))88 89#define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \90 MXS_I2C_CTRL0_MASTER_MODE | \91 MXS_I2C_CTRL0_DIRECTION)92 93#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \94 MXS_I2C_CTRL0_MASTER_MODE)95 96enum mxs_i2c_devtype {97 MXS_I2C_UNKNOWN = 0,98 MXS_I2C_V1,99 MXS_I2C_V2,100};101 102/**103 * struct mxs_i2c_dev - per device, private MXS-I2C data104 *105 * @dev: driver model device node106 * @dev_type: distinguish i.MX23/i.MX28 features107 * @regs: IO registers pointer108 * @cmd_complete: completion object for transaction wait109 * @cmd_err: error code for last transaction110 * @adapter: i2c subsystem adapter node111 */112struct mxs_i2c_dev {113 struct device *dev;114 enum mxs_i2c_devtype dev_type;115 void __iomem *regs;116 struct completion cmd_complete;117 int cmd_err;118 struct i2c_adapter adapter;119 120 uint32_t timing0;121 uint32_t timing1;122 uint32_t timing2;123 124 /* DMA support components */125 struct dma_chan *dmach;126 uint32_t pio_data[2];127 uint32_t addr_data;128 struct scatterlist sg_io[2];129 bool dma_read;130};131 132static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)133{134 int ret = stmp_reset_block(i2c->regs);135 if (ret)136 return ret;137 138 /*139 * Configure timing for the I2C block. The I2C TIMING2 register has to140 * be programmed with this particular magic number. The rest is derived141 * from the XTAL speed and requested I2C speed.142 *143 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].144 */145 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);146 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);147 writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);148 149 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);150 151 return 0;152}153 154static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)155{156 if (i2c->dma_read) {157 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);158 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);159 } else {160 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);161 }162}163 164static void mxs_i2c_dma_irq_callback(void *param)165{166 struct mxs_i2c_dev *i2c = param;167 168 complete(&i2c->cmd_complete);169 mxs_i2c_dma_finish(i2c);170}171 172static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,173 struct i2c_msg *msg, u8 *buf, uint32_t flags)174{175 struct dma_async_tx_descriptor *desc;176 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);177 178 i2c->addr_data = i2c_8bit_addr_from_msg(msg);179 180 if (msg->flags & I2C_M_RD) {181 i2c->dma_read = true;182 183 /*184 * SELECT command.185 */186 187 /* Queue the PIO register write transfer. */188 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;189 desc = dmaengine_prep_slave_sg(i2c->dmach,190 (struct scatterlist *)&i2c->pio_data[0],191 1, DMA_TRANS_NONE, 0);192 if (!desc) {193 dev_err(i2c->dev,194 "Failed to get PIO reg. write descriptor.\n");195 goto select_init_pio_fail;196 }197 198 /* Queue the DMA data transfer. */199 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);200 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);201 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,202 DMA_MEM_TO_DEV,203 DMA_PREP_INTERRUPT |204 MXS_DMA_CTRL_WAIT4END);205 if (!desc) {206 dev_err(i2c->dev,207 "Failed to get DMA data write descriptor.\n");208 goto select_init_dma_fail;209 }210 211 /*212 * READ command.213 */214 215 /* Queue the PIO register write transfer. */216 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |217 MXS_I2C_CTRL0_XFER_COUNT(msg->len);218 desc = dmaengine_prep_slave_sg(i2c->dmach,219 (struct scatterlist *)&i2c->pio_data[1],220 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);221 if (!desc) {222 dev_err(i2c->dev,223 "Failed to get PIO reg. write descriptor.\n");224 goto select_init_dma_fail;225 }226 227 /* Queue the DMA data transfer. */228 sg_init_one(&i2c->sg_io[1], buf, msg->len);229 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);230 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,231 DMA_DEV_TO_MEM,232 DMA_PREP_INTERRUPT |233 MXS_DMA_CTRL_WAIT4END);234 if (!desc) {235 dev_err(i2c->dev,236 "Failed to get DMA data write descriptor.\n");237 goto read_init_dma_fail;238 }239 } else {240 i2c->dma_read = false;241 242 /*243 * WRITE command.244 */245 246 /* Queue the PIO register write transfer. */247 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |248 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);249 desc = dmaengine_prep_slave_sg(i2c->dmach,250 (struct scatterlist *)&i2c->pio_data[0],251 1, DMA_TRANS_NONE, 0);252 if (!desc) {253 dev_err(i2c->dev,254 "Failed to get PIO reg. write descriptor.\n");255 goto write_init_pio_fail;256 }257 258 /* Queue the DMA data transfer. */259 sg_init_table(i2c->sg_io, 2);260 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);261 sg_set_buf(&i2c->sg_io[1], buf, msg->len);262 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);263 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,264 DMA_MEM_TO_DEV,265 DMA_PREP_INTERRUPT |266 MXS_DMA_CTRL_WAIT4END);267 if (!desc) {268 dev_err(i2c->dev,269 "Failed to get DMA data write descriptor.\n");270 goto write_init_dma_fail;271 }272 }273 274 /*275 * The last descriptor must have this callback,276 * to finish the DMA transaction.277 */278 desc->callback = mxs_i2c_dma_irq_callback;279 desc->callback_param = i2c;280 281 /* Start the transfer. */282 dmaengine_submit(desc);283 dma_async_issue_pending(i2c->dmach);284 return 0;285 286/* Read failpath. */287read_init_dma_fail:288 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);289select_init_dma_fail:290 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);291select_init_pio_fail:292 dmaengine_terminate_sync(i2c->dmach);293 return -EINVAL;294 295/* Write failpath. */296write_init_dma_fail:297 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);298write_init_pio_fail:299 dmaengine_terminate_sync(i2c->dmach);300 return -EINVAL;301}302 303static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)304{305 unsigned long timeout = jiffies + msecs_to_jiffies(1000);306 307 while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {308 if (readl(i2c->regs + MXS_I2C_CTRL1) &309 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)310 return -ENXIO;311 if (time_after(jiffies, timeout))312 return -ETIMEDOUT;313 cond_resched();314 }315 316 return 0;317}318 319static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)320{321 u32 state;322 323 state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;324 325 if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)326 i2c->cmd_err = -ENXIO;327 else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |328 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |329 MXS_I2C_CTRL1_SLAVE_STOP_IRQ |330 MXS_I2C_CTRL1_SLAVE_IRQ))331 i2c->cmd_err = -EIO;332 333 return i2c->cmd_err;334}335 336static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)337{338 u32 reg;339 340 writel(cmd, i2c->regs + MXS_I2C_CTRL0);341 342 /* readback makes sure the write is latched into hardware */343 reg = readl(i2c->regs + MXS_I2C_CTRL0);344 reg |= MXS_I2C_CTRL0_RUN;345 writel(reg, i2c->regs + MXS_I2C_CTRL0);346}347 348/*349 * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,350 * CTRL0::PIO_MODE bit description clarifies the order in which the registers351 * must be written during PIO mode operation. First, the CTRL0 register has352 * to be programmed with all the necessary bits but the RUN bit. Then the353 * payload has to be written into the DATA register. Finally, the transmission354 * is executed by setting the RUN bit in CTRL0.355 */356static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,357 u32 data)358{359 writel(cmd, i2c->regs + MXS_I2C_CTRL0);360 361 if (i2c->dev_type == MXS_I2C_V1)362 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);363 364 writel(data, i2c->regs + MXS_I2C_DATA(i2c));365 writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);366}367 368static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,369 struct i2c_msg *msg, uint32_t flags)370{371 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);372 uint32_t addr_data = i2c_8bit_addr_from_msg(msg);373 uint32_t data = 0;374 int i, ret, xlen = 0, xmit = 0;375 uint32_t start;376 377 /* Mute IRQs coming from this block. */378 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);379 380 /*381 * MX23 idea:382 * - Enable CTRL0::PIO_MODE (1 << 24)383 * - Enable CTRL1::ACK_MODE (1 << 27)384 *385 * WARNING! The MX23 is broken in some way, even if it claims386 * to support PIO, when we try to transfer any amount of data387 * that is not aligned to 4 bytes, the DMA engine will have388 * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the389 * transfer. This in turn will mess up the next transfer as390 * the block it emit one byte write onto the bus terminated391 * with a NAK+STOP. A possible workaround is to reset the IP392 * block after every PIO transmission, which might just work.393 *394 * NOTE: The CTRL0::PIO_MODE description is important, since395 * it outlines how the PIO mode is really supposed to work.396 */397 if (msg->flags & I2C_M_RD) {398 /*399 * PIO READ transfer:400 *401 * This transfer MUST be limited to 4 bytes maximum. It is not402 * possible to transfer more than four bytes via PIO, since we403 * can not in any way make sure we can read the data from the404 * DATA register fast enough. Besides, the RX FIFO is only four405 * bytes deep, thus we can only really read up to four bytes at406 * time. Finally, there is no bit indicating us that new data407 * arrived at the FIFO and can thus be fetched from the DATA408 * register.409 */410 BUG_ON(msg->len > 4);411 412 /* SELECT command. */413 mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,414 addr_data);415 416 ret = mxs_i2c_pio_wait_xfer_end(i2c);417 if (ret) {418 dev_dbg(i2c->dev,419 "PIO: Failed to send SELECT command!\n");420 goto cleanup;421 }422 423 /* READ command. */424 mxs_i2c_pio_trigger_cmd(i2c,425 MXS_CMD_I2C_READ | flags |426 MXS_I2C_CTRL0_XFER_COUNT(msg->len));427 428 ret = mxs_i2c_pio_wait_xfer_end(i2c);429 if (ret) {430 dev_dbg(i2c->dev,431 "PIO: Failed to send READ command!\n");432 goto cleanup;433 }434 435 data = readl(i2c->regs + MXS_I2C_DATA(i2c));436 for (i = 0; i < msg->len; i++) {437 msg->buf[i] = data & 0xff;438 data >>= 8;439 }440 } else {441 /*442 * PIO WRITE transfer:443 *444 * The code below implements clock stretching to circumvent445 * the possibility of kernel not being able to supply data446 * fast enough. It is possible to transfer arbitrary amount447 * of data using PIO write.448 */449 450 /*451 * The LSB of data buffer is the first byte blasted across452 * the bus. Higher order bytes follow. Thus the following453 * filling schematic.454 */455 456 data = addr_data << 24;457 458 /* Start the transfer with START condition. */459 start = MXS_I2C_CTRL0_PRE_SEND_START;460 461 /* If the transfer is long, use clock stretching. */462 if (msg->len > 3)463 start |= MXS_I2C_CTRL0_RETAIN_CLOCK;464 465 for (i = 0; i < msg->len; i++) {466 data >>= 8;467 data |= (msg->buf[i] << 24);468 469 xmit = 0;470 471 /* This is the last transfer of the message. */472 if (i + 1 == msg->len) {473 /* Add optional STOP flag. */474 start |= flags;475 /* Remove RETAIN_CLOCK bit. */476 start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;477 xmit = 1;478 }479 480 /* Four bytes are ready in the "data" variable. */481 if ((i & 3) == 2)482 xmit = 1;483 484 /* Nothing interesting happened, continue stuffing. */485 if (!xmit)486 continue;487 488 /*489 * Compute the size of the transfer and shift the490 * data accordingly.491 *492 * i = (4k + 0) .... xlen = 2493 * i = (4k + 1) .... xlen = 3494 * i = (4k + 2) .... xlen = 4495 * i = (4k + 3) .... xlen = 1496 */497 498 if ((i % 4) == 3)499 xlen = 1;500 else501 xlen = (i % 4) + 2;502 503 data >>= (4 - xlen) * 8;504 505 dev_dbg(i2c->dev,506 "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",507 xlen, i, msg->len,508 start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",509 start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",510 start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");511 512 writel(MXS_I2C_DEBUG0_DMAREQ,513 i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));514 515 mxs_i2c_pio_trigger_write_cmd(i2c,516 start | MXS_I2C_CTRL0_MASTER_MODE |517 MXS_I2C_CTRL0_DIRECTION |518 MXS_I2C_CTRL0_XFER_COUNT(xlen), data);519 520 /* The START condition is sent only once. */521 start &= ~MXS_I2C_CTRL0_PRE_SEND_START;522 523 /* Wait for the end of the transfer. */524 ret = mxs_i2c_pio_wait_xfer_end(i2c);525 if (ret) {526 dev_dbg(i2c->dev,527 "PIO: Failed to finish WRITE cmd!\n");528 break;529 }530 531 /* Check NAK here. */532 ret = readl(i2c->regs + MXS_I2C_STAT) &533 MXS_I2C_STAT_GOT_A_NAK;534 if (ret) {535 ret = -ENXIO;536 goto cleanup;537 }538 }539 }540 541 /* make sure we capture any occurred error into cmd_err */542 ret = mxs_i2c_pio_check_error_state(i2c);543 544cleanup:545 /* Clear any dangling IRQs and re-enable interrupts. */546 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);547 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);548 549 /* Clear the PIO_MODE on i.MX23 */550 if (i2c->dev_type == MXS_I2C_V1)551 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);552 553 return ret;554}555 556/*557 * Low level master read/write transaction.558 */559static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,560 int stop)561{562 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);563 int ret;564 int flags;565 u8 *dma_buf;566 int use_pio = 0;567 unsigned long time_left;568 569 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;570 571 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",572 msg->addr, msg->len, msg->flags, stop);573 574 /*575 * The MX28 I2C IP block can only do PIO READ for transfer of to up576 * 4 bytes of length. The write transfer is not limited as it can use577 * clock stretching to avoid FIFO underruns.578 */579 if ((msg->flags & I2C_M_RD) && (msg->len <= 4))580 use_pio = 1;581 if (!(msg->flags & I2C_M_RD) && (msg->len < 7))582 use_pio = 1;583 584 i2c->cmd_err = 0;585 if (use_pio) {586 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);587 /* No need to reset the block if NAK was received. */588 if (ret && (ret != -ENXIO))589 mxs_i2c_reset(i2c);590 } else {591 dma_buf = i2c_get_dma_safe_msg_buf(msg, 1);592 if (!dma_buf)593 return -ENOMEM;594 595 reinit_completion(&i2c->cmd_complete);596 ret = mxs_i2c_dma_setup_xfer(adap, msg, dma_buf, flags);597 if (ret) {598 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);599 return ret;600 }601 602 time_left = wait_for_completion_timeout(&i2c->cmd_complete,603 msecs_to_jiffies(1000));604 i2c_put_dma_safe_msg_buf(dma_buf, msg, true);605 if (!time_left)606 goto timeout;607 608 ret = i2c->cmd_err;609 }610 611 if (ret == -ENXIO) {612 /*613 * If the transfer fails with a NAK from the slave the614 * controller halts until it gets told to return to idle state.615 */616 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,617 i2c->regs + MXS_I2C_CTRL1_SET);618 }619 620 /*621 * WARNING!622 * The i.MX23 is strange. After each and every operation, it's I2C IP623 * block must be reset, otherwise the IP block will misbehave. This can624 * be observed on the bus by the block sending out one single byte onto625 * the bus. In case such an error happens, bit 27 will be set in the626 * DEBUG0 register. This bit is not documented in the i.MX23 datasheet627 * and is marked as "TBD" instead. To reset this bit to a correct state,628 * reset the whole block. Since the block reset does not take long, do629 * reset the block after every transfer to play safe.630 */631 if (i2c->dev_type == MXS_I2C_V1)632 mxs_i2c_reset(i2c);633 634 dev_dbg(i2c->dev, "Done with err=%d\n", ret);635 636 return ret;637 638timeout:639 dev_dbg(i2c->dev, "Timeout!\n");640 mxs_i2c_dma_finish(i2c);641 ret = mxs_i2c_reset(i2c);642 if (ret)643 return ret;644 645 return -ETIMEDOUT;646}647 648static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],649 int num)650{651 int i;652 int err;653 654 for (i = 0; i < num; i++) {655 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));656 if (err)657 return err;658 }659 660 return num;661}662 663static u32 mxs_i2c_func(struct i2c_adapter *adap)664{665 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;666}667 668static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)669{670 struct mxs_i2c_dev *i2c = dev_id;671 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;672 673 if (!stat)674 return IRQ_NONE;675 676 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)677 i2c->cmd_err = -ENXIO;678 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |679 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |680 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))681 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */682 i2c->cmd_err = -EIO;683 684 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);685 686 return IRQ_HANDLED;687}688 689static const struct i2c_algorithm mxs_i2c_algo = {690 .master_xfer = mxs_i2c_xfer,691 .functionality = mxs_i2c_func,692};693 694static const struct i2c_adapter_quirks mxs_i2c_quirks = {695 .flags = I2C_AQ_NO_ZERO_LEN,696};697 698static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)699{700 /* The I2C block clock runs at 24MHz */701 const uint32_t clk = 24000000;702 uint32_t divider;703 uint16_t high_count, low_count, rcv_count, xmit_count;704 uint32_t bus_free, leadin;705 struct device *dev = i2c->dev;706 707 divider = DIV_ROUND_UP(clk, speed);708 709 if (divider < 25) {710 /*711 * limit the divider, so that min(low_count, high_count)712 * is >= 1713 */714 divider = 25;715 dev_warn(dev,716 "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",717 speed / 1000, speed % 1000,718 clk / divider / 1000, clk / divider % 1000);719 } else if (divider > 1897) {720 /*721 * limit the divider, so that max(low_count, high_count)722 * cannot exceed 1023723 */724 divider = 1897;725 dev_warn(dev,726 "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",727 speed / 1000, speed % 1000,728 clk / divider / 1000, clk / divider % 1000);729 }730 731 /*732 * The I2C spec specifies the following timing data:733 * standard mode fast mode Bitfield name734 * tLOW (SCL LOW period) 4700 ns 1300 ns735 * tHIGH (SCL HIGH period) 4000 ns 600 ns736 * tSU;DAT (data setup time) 250 ns 100 ns737 * tHD;STA (START hold time) 4000 ns 600 ns738 * tBUF (bus free time) 4700 ns 1300 ns739 *740 * The hardware (of the i.MX28 at least) seems to add 2 additional741 * clock cycles to the low_count and 7 cycles to the high_count.742 * This is compensated for by subtracting the respective constants743 * from the values written to the timing registers.744 */745 if (speed > I2C_MAX_STANDARD_MODE_FREQ) {746 /* fast mode */747 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));748 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));749 leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);750 bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);751 } else {752 /* normal mode */753 low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));754 high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));755 leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);756 bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);757 }758 rcv_count = high_count * 3 / 8;759 xmit_count = low_count * 3 / 8;760 761 dev_dbg(dev,762 "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",763 speed, clk / divider, divider, low_count, high_count,764 xmit_count, rcv_count, leadin, bus_free);765 766 low_count -= 2;767 high_count -= 7;768 i2c->timing0 = (high_count << 16) | rcv_count;769 i2c->timing1 = (low_count << 16) | xmit_count;770 i2c->timing2 = (bus_free << 16 | leadin);771}772 773static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)774{775 uint32_t speed;776 struct device *dev = i2c->dev;777 struct device_node *node = dev->of_node;778 int ret;779 780 ret = of_property_read_u32(node, "clock-frequency", &speed);781 if (ret) {782 dev_warn(dev, "No I2C speed selected, using 100kHz\n");783 speed = I2C_MAX_STANDARD_MODE_FREQ;784 }785 786 mxs_i2c_derive_timing(i2c, speed);787 788 return 0;789}790 791static const struct of_device_id mxs_i2c_dt_ids[] = {792 { .compatible = "fsl,imx23-i2c", .data = (void *)MXS_I2C_V1, },793 { .compatible = "fsl,imx28-i2c", .data = (void *)MXS_I2C_V2, },794 { /* sentinel */ }795};796MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);797 798static int mxs_i2c_probe(struct platform_device *pdev)799{800 struct device *dev = &pdev->dev;801 struct mxs_i2c_dev *i2c;802 struct i2c_adapter *adap;803 int err, irq;804 805 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);806 if (!i2c)807 return -ENOMEM;808 809 i2c->dev_type = (uintptr_t)of_device_get_match_data(&pdev->dev);810 811 i2c->regs = devm_platform_ioremap_resource(pdev, 0);812 if (IS_ERR(i2c->regs))813 return PTR_ERR(i2c->regs);814 815 irq = platform_get_irq(pdev, 0);816 if (irq < 0)817 return irq;818 819 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);820 if (err)821 return err;822 823 i2c->dev = dev;824 825 init_completion(&i2c->cmd_complete);826 827 if (dev->of_node) {828 err = mxs_i2c_get_ofdata(i2c);829 if (err)830 return err;831 }832 833 /* Setup the DMA */834 i2c->dmach = dma_request_chan(dev, "rx-tx");835 if (IS_ERR(i2c->dmach)) {836 return dev_err_probe(dev, PTR_ERR(i2c->dmach),837 "Failed to request dma\n");838 }839 840 platform_set_drvdata(pdev, i2c);841 842 /* Do reset to enforce correct startup after pinmuxing */843 err = mxs_i2c_reset(i2c);844 if (err)845 return err;846 847 adap = &i2c->adapter;848 strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));849 adap->owner = THIS_MODULE;850 adap->algo = &mxs_i2c_algo;851 adap->quirks = &mxs_i2c_quirks;852 adap->dev.parent = dev;853 adap->nr = pdev->id;854 adap->dev.of_node = pdev->dev.of_node;855 i2c_set_adapdata(adap, i2c);856 err = i2c_add_numbered_adapter(adap);857 if (err) {858 writel(MXS_I2C_CTRL0_SFTRST,859 i2c->regs + MXS_I2C_CTRL0_SET);860 return err;861 }862 863 return 0;864}865 866static void mxs_i2c_remove(struct platform_device *pdev)867{868 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);869 870 i2c_del_adapter(&i2c->adapter);871 872 if (i2c->dmach)873 dma_release_channel(i2c->dmach);874 875 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);876}877 878static struct platform_driver mxs_i2c_driver = {879 .driver = {880 .name = DRIVER_NAME,881 .of_match_table = mxs_i2c_dt_ids,882 },883 .probe = mxs_i2c_probe,884 .remove_new = mxs_i2c_remove,885};886 887static int __init mxs_i2c_init(void)888{889 return platform_driver_register(&mxs_i2c_driver);890}891subsys_initcall(mxs_i2c_init);892 893static void __exit mxs_i2c_exit(void)894{895 platform_driver_unregister(&mxs_i2c_driver);896}897module_exit(mxs_i2c_exit);898 899MODULE_AUTHOR("Marek Vasut <marex@denx.de>");900MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");901MODULE_DESCRIPTION("MXS I2C Bus Driver");902MODULE_LICENSE("GPL");903MODULE_ALIAS("platform:" DRIVER_NAME);904