1219 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) 2009 ST-Ericsson SA4 * Copyright (C) 2009 STMicroelectronics5 *6 * I2C master mode controller driver, used in Nomadik 88157 * and Ux500 platforms.8 *9 * The Mobileye EyeQ5 platform is also supported; it uses10 * the same Ux500/DB8500 IP block with two quirks:11 * - The memory bus only supports 32-bit accesses.12 * - A register must be configured for the I2C speed mode;13 * it is located in a shared register region called OLB.14 *15 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>16 * Author: Sachin Verma <sachin.verma@st.com>17 */18#include <linux/amba/bus.h>19#include <linux/bitfield.h>20#include <linux/clk.h>21#include <linux/err.h>22#include <linux/i2c.h>23#include <linux/init.h>24#include <linux/interrupt.h>25#include <linux/io.h>26#include <linux/mfd/syscon.h>27#include <linux/module.h>28#include <linux/of.h>29#include <linux/pinctrl/consumer.h>30#include <linux/pm_runtime.h>31#include <linux/regmap.h>32#include <linux/slab.h>33 34#define DRIVER_NAME "nmk-i2c"35 36/* I2C Controller register offsets */37#define I2C_CR (0x000)38#define I2C_SCR (0x004)39#define I2C_HSMCR (0x008)40#define I2C_MCR (0x00C)41#define I2C_TFR (0x010)42#define I2C_SR (0x014)43#define I2C_RFR (0x018)44#define I2C_TFTR (0x01C)45#define I2C_RFTR (0x020)46#define I2C_DMAR (0x024)47#define I2C_BRCR (0x028)48#define I2C_IMSCR (0x02C)49#define I2C_RISR (0x030)50#define I2C_MISR (0x034)51#define I2C_ICR (0x038)52 53/* Control registers */54#define I2C_CR_PE BIT(0) /* Peripheral Enable */55#define I2C_CR_OM GENMASK(2, 1) /* Operating mode */56#define I2C_CR_SAM BIT(3) /* Slave addressing mode */57#define I2C_CR_SM GENMASK(5, 4) /* Speed mode */58#define I2C_CR_SGCM BIT(6) /* Slave general call mode */59#define I2C_CR_FTX BIT(7) /* Flush Transmit */60#define I2C_CR_FRX BIT(8) /* Flush Receive */61#define I2C_CR_DMA_TX_EN BIT(9) /* DMA Tx enable */62#define I2C_CR_DMA_RX_EN BIT(10) /* DMA Rx Enable */63#define I2C_CR_DMA_SLE BIT(11) /* DMA sync. logic enable */64#define I2C_CR_LM BIT(12) /* Loopback mode */65#define I2C_CR_FON GENMASK(14, 13) /* Filtering on */66#define I2C_CR_FS GENMASK(16, 15) /* Force stop enable */67 68/* Slave control register (SCR) */69#define I2C_SCR_SLSU GENMASK(31, 16) /* Slave data setup time */70 71/* Master controller (MCR) register */72#define I2C_MCR_OP BIT(0) /* Operation */73#define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */74#define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */75#define I2C_MCR_SB BIT(11) /* Extended address */76#define I2C_MCR_AM GENMASK(13, 12) /* Address type */77#define I2C_MCR_STOP BIT(14) /* Stop condition */78#define I2C_MCR_LENGTH GENMASK(25, 15) /* Transaction length */79 80/* Status register (SR) */81#define I2C_SR_OP GENMASK(1, 0) /* Operation */82#define I2C_SR_STATUS GENMASK(3, 2) /* controller status */83#define I2C_SR_CAUSE GENMASK(6, 4) /* Abort cause */84#define I2C_SR_TYPE GENMASK(8, 7) /* Receive type */85#define I2C_SR_LENGTH GENMASK(19, 9) /* Transfer length */86 87/* Baud-rate counter register (BRCR) */88#define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */89#define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */90 91/* Interrupt mask set/clear (IMSCR) bits */92#define I2C_IT_TXFE BIT(0)93#define I2C_IT_TXFNE BIT(1)94#define I2C_IT_TXFF BIT(2)95#define I2C_IT_TXFOVR BIT(3)96#define I2C_IT_RXFE BIT(4)97#define I2C_IT_RXFNF BIT(5)98#define I2C_IT_RXFF BIT(6)99#define I2C_IT_RFSR BIT(16)100#define I2C_IT_RFSE BIT(17)101#define I2C_IT_WTSR BIT(18)102#define I2C_IT_MTD BIT(19)103#define I2C_IT_STD BIT(20)104#define I2C_IT_MAL BIT(24)105#define I2C_IT_BERR BIT(25)106#define I2C_IT_MTDWS BIT(28)107 108/* some bits in ICR are reserved */109#define I2C_CLEAR_ALL_INTS 0x131f007f110 111/* maximum threshold value */112#define MAX_I2C_FIFO_THRESHOLD 15113 114enum i2c_freq_mode {115 I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */116 I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */117 I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */118 I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */119};120 121/* Mobileye EyeQ5 offset into a shared register region (called OLB) */122#define NMK_I2C_EYEQ5_OLB_IOCR2 0x0B8123 124enum i2c_eyeq5_speed {125 I2C_EYEQ5_SPEED_FAST,126 I2C_EYEQ5_SPEED_FAST_PLUS,127 I2C_EYEQ5_SPEED_HIGH_SPEED,128};129 130/**131 * struct i2c_vendor_data - per-vendor variations132 * @has_mtdws: variant has the MTDWS bit133 * @fifodepth: variant FIFO depth134 */135struct i2c_vendor_data {136 bool has_mtdws;137 u32 fifodepth;138};139 140enum i2c_status {141 I2C_NOP,142 I2C_ON_GOING,143 I2C_OK,144 I2C_ABORT145};146 147/* operation */148enum i2c_operation {149 I2C_NO_OPERATION = 0xff,150 I2C_WRITE = 0x00,151 I2C_READ = 0x01152};153 154enum i2c_operating_mode {155 I2C_OM_SLAVE,156 I2C_OM_MASTER,157 I2C_OM_MASTER_OR_SLAVE,158};159 160/**161 * struct i2c_nmk_client - client specific data162 * @slave_adr: 7-bit slave address163 * @count: no. bytes to be transferred164 * @buffer: client data buffer165 * @xfer_bytes: bytes transferred till now166 * @operation: current I2C operation167 */168struct i2c_nmk_client {169 unsigned short slave_adr;170 unsigned long count;171 unsigned char *buffer;172 unsigned long xfer_bytes;173 enum i2c_operation operation;174};175 176/**177 * struct nmk_i2c_dev - private data structure of the controller.178 * @vendor: vendor data for this variant.179 * @adev: parent amba device.180 * @adap: corresponding I2C adapter.181 * @irq: interrupt line for the controller.182 * @virtbase: virtual io memory area.183 * @clk: hardware i2c block clock.184 * @cli: holder of client specific data.185 * @clk_freq: clock frequency for the operation mode186 * @tft: Tx FIFO Threshold in bytes187 * @rft: Rx FIFO Threshold in bytes188 * @timeout_usecs: Slave response timeout189 * @sm: speed mode190 * @stop: stop condition.191 * @xfer_wq: xfer done wait queue.192 * @xfer_done: xfer done boolean.193 * @result: controller propogated result.194 * @has_32b_bus: controller is on a bus that only supports 32-bit accesses.195 */196struct nmk_i2c_dev {197 struct i2c_vendor_data *vendor;198 struct amba_device *adev;199 struct i2c_adapter adap;200 int irq;201 void __iomem *virtbase;202 struct clk *clk;203 struct i2c_nmk_client cli;204 u32 clk_freq;205 unsigned char tft;206 unsigned char rft;207 u32 timeout_usecs;208 enum i2c_freq_mode sm;209 int stop;210 struct wait_queue_head xfer_wq;211 bool xfer_done;212 int result;213 bool has_32b_bus;214};215 216/* controller's abort causes */217static const char *abort_causes[] = {218 "no ack received after address transmission",219 "no ack received during data phase",220 "ack received after xmission of master code",221 "master lost arbitration",222 "slave restarts",223 "slave reset",224 "overflow, maxsize is 2047 bytes",225};226 227static inline void i2c_set_bit(void __iomem *reg, u32 mask)228{229 writel(readl(reg) | mask, reg);230}231 232static inline void i2c_clr_bit(void __iomem *reg, u32 mask)233{234 writel(readl(reg) & ~mask, reg);235}236 237static inline u8 nmk_i2c_readb(const struct nmk_i2c_dev *priv,238 unsigned long reg)239{240 if (priv->has_32b_bus)241 return readl(priv->virtbase + reg);242 else243 return readb(priv->virtbase + reg);244}245 246static inline void nmk_i2c_writeb(const struct nmk_i2c_dev *priv, u32 val,247 unsigned long reg)248{249 if (priv->has_32b_bus)250 writel(val, priv->virtbase + reg);251 else252 writeb(val, priv->virtbase + reg);253}254 255/**256 * flush_i2c_fifo() - This function flushes the I2C FIFO257 * @priv: private data of I2C Driver258 *259 * This function flushes the I2C Tx and Rx FIFOs. It returns260 * 0 on successful flushing of FIFO261 */262static int flush_i2c_fifo(struct nmk_i2c_dev *priv)263{264#define LOOP_ATTEMPTS 10265 ktime_t timeout;266 int i;267 268 /*269 * flush the transmit and receive FIFO. The flushing270 * operation takes several cycles before to be completed.271 * On the completion, the I2C internal logic clears these272 * bits, until then no one must access Tx, Rx FIFO and273 * should poll on these bits waiting for the completion.274 */275 writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR);276 277 for (i = 0; i < LOOP_ATTEMPTS; i++) {278 timeout = ktime_add_us(ktime_get(), priv->timeout_usecs);279 280 while (ktime_after(timeout, ktime_get())) {281 if ((readl(priv->virtbase + I2C_CR) &282 (I2C_CR_FTX | I2C_CR_FRX)) == 0)283 return 0;284 }285 }286 287 dev_err(&priv->adev->dev,288 "flushing operation timed out giving up after %d attempts",289 LOOP_ATTEMPTS);290 291 return -ETIMEDOUT;292}293 294/**295 * disable_all_interrupts() - Disable all interrupts of this I2c Bus296 * @priv: private data of I2C Driver297 */298static void disable_all_interrupts(struct nmk_i2c_dev *priv)299{300 writel(0, priv->virtbase + I2C_IMSCR);301}302 303/**304 * clear_all_interrupts() - Clear all interrupts of I2C Controller305 * @priv: private data of I2C Driver306 */307static void clear_all_interrupts(struct nmk_i2c_dev *priv)308{309 writel(I2C_CLEAR_ALL_INTS, priv->virtbase + I2C_ICR);310}311 312/**313 * init_hw() - initialize the I2C hardware314 * @priv: private data of I2C Driver315 */316static int init_hw(struct nmk_i2c_dev *priv)317{318 int stat;319 320 stat = flush_i2c_fifo(priv);321 if (stat)322 goto exit;323 324 /* disable the controller */325 i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE);326 327 disable_all_interrupts(priv);328 329 clear_all_interrupts(priv);330 331 priv->cli.operation = I2C_NO_OPERATION;332 333exit:334 return stat;335}336 337/* enable peripheral, master mode operation */338#define DEFAULT_I2C_REG_CR (FIELD_PREP(I2C_CR_OM, I2C_OM_MASTER) | I2C_CR_PE)339 340/* grab top three bits from extended I2C addresses */341#define ADR_3MSB_BITS GENMASK(9, 7)342 343/**344 * load_i2c_mcr_reg() - load the MCR register345 * @priv: private data of controller346 * @flags: message flags347 */348static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *priv, u16 flags)349{350 u32 mcr = 0;351 unsigned short slave_adr_3msb_bits;352 353 mcr |= FIELD_PREP(I2C_MCR_A7, priv->cli.slave_adr);354 355 if (unlikely(flags & I2C_M_TEN)) {356 /* 10-bit address transaction */357 mcr |= FIELD_PREP(I2C_MCR_AM, 2);358 /*359 * Get the top 3 bits.360 * EA10 represents extended address in MCR. This includes361 * the extension (MSB bits) of the 7 bit address loaded362 * in A7363 */364 slave_adr_3msb_bits = FIELD_GET(ADR_3MSB_BITS,365 priv->cli.slave_adr);366 367 mcr |= FIELD_PREP(I2C_MCR_EA10, slave_adr_3msb_bits);368 } else {369 /* 7-bit address transaction */370 mcr |= FIELD_PREP(I2C_MCR_AM, 1);371 }372 373 /* start byte procedure not applied */374 mcr |= FIELD_PREP(I2C_MCR_SB, 0);375 376 /* check the operation, master read/write? */377 if (priv->cli.operation == I2C_WRITE)378 mcr |= FIELD_PREP(I2C_MCR_OP, I2C_WRITE);379 else380 mcr |= FIELD_PREP(I2C_MCR_OP, I2C_READ);381 382 /* stop or repeated start? */383 if (priv->stop)384 mcr |= FIELD_PREP(I2C_MCR_STOP, 1);385 else386 mcr &= ~FIELD_PREP(I2C_MCR_STOP, 1);387 388 mcr |= FIELD_PREP(I2C_MCR_LENGTH, priv->cli.count);389 390 return mcr;391}392 393/**394 * setup_i2c_controller() - setup the controller395 * @priv: private data of controller396 */397static void setup_i2c_controller(struct nmk_i2c_dev *priv)398{399 u32 brcr1, brcr2;400 u32 i2c_clk, div;401 u32 ns;402 u16 slsu;403 404 writel(0x0, priv->virtbase + I2C_CR);405 writel(0x0, priv->virtbase + I2C_HSMCR);406 writel(0x0, priv->virtbase + I2C_TFTR);407 writel(0x0, priv->virtbase + I2C_RFTR);408 writel(0x0, priv->virtbase + I2C_DMAR);409 410 i2c_clk = clk_get_rate(priv->clk);411 412 /*413 * set the slsu:414 *415 * slsu defines the data setup time after SCL clock416 * stretching in terms of i2c clk cycles + 1 (zero means417 * "wait one cycle"), the needed setup time for the three418 * modes are 250ns, 100ns, 10ns respectively.419 *420 * As the time for one cycle T in nanoseconds is421 * T = (1/f) * 1000000000 =>422 * slsu = cycles / (1000000000 / f) + 1423 */424 ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);425 switch (priv->sm) {426 case I2C_FREQ_MODE_FAST:427 case I2C_FREQ_MODE_FAST_PLUS:428 slsu = DIV_ROUND_UP(100, ns); /* Fast */429 break;430 case I2C_FREQ_MODE_HIGH_SPEED:431 slsu = DIV_ROUND_UP(10, ns); /* High */432 break;433 case I2C_FREQ_MODE_STANDARD:434 default:435 slsu = DIV_ROUND_UP(250, ns); /* Standard */436 break;437 }438 slsu += 1;439 440 dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n", slsu);441 writel(FIELD_PREP(I2C_SCR_SLSU, slsu), priv->virtbase + I2C_SCR);442 443 /*444 * The spec says, in case of std. mode the divider is445 * 2 whereas it is 3 for fast and fastplus mode of446 * operation. TODO - high speed support.447 */448 div = (priv->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;449 450 /*451 * generate the mask for baud rate counters. The controller452 * has two baud rate counters. One is used for High speed453 * operation, and the other is for std, fast mode, fast mode454 * plus operation. Currently we do not supprt high speed mode455 * so set brcr1 to 0.456 */457 brcr1 = FIELD_PREP(I2C_BRCR_BRCNT1, 0);458 brcr2 = FIELD_PREP(I2C_BRCR_BRCNT2, i2c_clk / (priv->clk_freq * div));459 460 /* set the baud rate counter register */461 writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR);462 463 /*464 * set the speed mode. Currently we support465 * only standard and fast mode of operation466 * TODO - support for fast mode plus (up to 1Mb/s)467 * and high speed (up to 3.4 Mb/s)468 */469 if (priv->sm > I2C_FREQ_MODE_FAST) {470 dev_err(&priv->adev->dev,471 "do not support this mode defaulting to std. mode\n");472 brcr2 = FIELD_PREP(I2C_BRCR_BRCNT2,473 i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2));474 writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR);475 writel(FIELD_PREP(I2C_CR_SM, I2C_FREQ_MODE_STANDARD),476 priv->virtbase + I2C_CR);477 }478 writel(FIELD_PREP(I2C_CR_SM, priv->sm), priv->virtbase + I2C_CR);479 480 /* set the Tx and Rx FIFO threshold */481 writel(priv->tft, priv->virtbase + I2C_TFTR);482 writel(priv->rft, priv->virtbase + I2C_RFTR);483}484 485static bool nmk_i2c_wait_xfer_done(struct nmk_i2c_dev *priv)486{487 if (priv->timeout_usecs < jiffies_to_usecs(1)) {488 unsigned long timeout_usecs = priv->timeout_usecs;489 ktime_t timeout = ktime_set(0, timeout_usecs * NSEC_PER_USEC);490 491 wait_event_hrtimeout(priv->xfer_wq, priv->xfer_done, timeout);492 } else {493 unsigned long timeout = usecs_to_jiffies(priv->timeout_usecs);494 495 wait_event_timeout(priv->xfer_wq, priv->xfer_done, timeout);496 }497 498 return priv->xfer_done;499}500 501/**502 * read_i2c() - Read from I2C client device503 * @priv: private data of I2C Driver504 * @flags: message flags505 *506 * This function reads from i2c client device when controller is in507 * master mode. There is a completion timeout. If there is no transfer508 * before timeout error is returned.509 */510static int read_i2c(struct nmk_i2c_dev *priv, u16 flags)511{512 u32 mcr, irq_mask;513 int status = 0;514 bool xfer_done;515 516 mcr = load_i2c_mcr_reg(priv, flags);517 writel(mcr, priv->virtbase + I2C_MCR);518 519 /* load the current CR value */520 writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,521 priv->virtbase + I2C_CR);522 523 /* enable the controller */524 i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE);525 526 init_waitqueue_head(&priv->xfer_wq);527 priv->xfer_done = false;528 529 /* enable interrupts by setting the mask */530 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |531 I2C_IT_MAL | I2C_IT_BERR);532 533 if (priv->stop || !priv->vendor->has_mtdws)534 irq_mask |= I2C_IT_MTD;535 else536 irq_mask |= I2C_IT_MTDWS;537 538 irq_mask &= I2C_CLEAR_ALL_INTS;539 540 writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,541 priv->virtbase + I2C_IMSCR);542 543 xfer_done = nmk_i2c_wait_xfer_done(priv);544 545 if (!xfer_done)546 status = -ETIMEDOUT;547 548 return status;549}550 551static void fill_tx_fifo(struct nmk_i2c_dev *priv, int no_bytes)552{553 int count;554 555 for (count = (no_bytes - 2);556 (count > 0) &&557 (priv->cli.count != 0);558 count--) {559 /* write to the Tx FIFO */560 nmk_i2c_writeb(priv, *priv->cli.buffer, I2C_TFR);561 priv->cli.buffer++;562 priv->cli.count--;563 priv->cli.xfer_bytes++;564 }565 566}567 568/**569 * write_i2c() - Write data to I2C client.570 * @priv: private data of I2C Driver571 * @flags: message flags572 *573 * This function writes data to I2C client574 */575static int write_i2c(struct nmk_i2c_dev *priv, u16 flags)576{577 u32 mcr, irq_mask;578 u32 status = 0;579 bool xfer_done;580 581 mcr = load_i2c_mcr_reg(priv, flags);582 583 writel(mcr, priv->virtbase + I2C_MCR);584 585 /* load the current CR value */586 writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,587 priv->virtbase + I2C_CR);588 589 /* enable the controller */590 i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE);591 592 init_waitqueue_head(&priv->xfer_wq);593 priv->xfer_done = false;594 595 /* enable interrupts by settings the masks */596 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);597 598 /* Fill the TX FIFO with transmit data */599 fill_tx_fifo(priv, MAX_I2C_FIFO_THRESHOLD);600 601 if (priv->cli.count != 0)602 irq_mask |= I2C_IT_TXFNE;603 604 /*605 * check if we want to transfer a single or multiple bytes, if so606 * set the MTDWS bit (Master Transaction Done Without Stop)607 * to start repeated start operation608 */609 if (priv->stop || !priv->vendor->has_mtdws)610 irq_mask |= I2C_IT_MTD;611 else612 irq_mask |= I2C_IT_MTDWS;613 614 irq_mask &= I2C_CLEAR_ALL_INTS;615 616 writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,617 priv->virtbase + I2C_IMSCR);618 619 xfer_done = nmk_i2c_wait_xfer_done(priv);620 621 if (!xfer_done) {622 /* Controller timed out */623 dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n",624 priv->cli.slave_adr);625 status = -ETIMEDOUT;626 }627 628 return status;629}630 631/**632 * nmk_i2c_xfer_one() - transmit a single I2C message633 * @priv: device with a message encoded into it634 * @flags: message flags635 */636static int nmk_i2c_xfer_one(struct nmk_i2c_dev *priv, u16 flags)637{638 int status;639 640 if (flags & I2C_M_RD) {641 /* read operation */642 priv->cli.operation = I2C_READ;643 status = read_i2c(priv, flags);644 } else {645 /* write operation */646 priv->cli.operation = I2C_WRITE;647 status = write_i2c(priv, flags);648 }649 650 if (status || priv->result) {651 u32 i2c_sr;652 u32 cause;653 654 i2c_sr = readl(priv->virtbase + I2C_SR);655 if (FIELD_GET(I2C_SR_STATUS, i2c_sr) == I2C_ABORT) {656 cause = FIELD_GET(I2C_SR_CAUSE, i2c_sr);657 dev_err(&priv->adev->dev, "%s\n",658 cause >= ARRAY_SIZE(abort_causes) ?659 "unknown reason" :660 abort_causes[cause]);661 }662 663 init_hw(priv);664 665 status = status ? status : priv->result;666 }667 668 return status;669}670 671/**672 * nmk_i2c_xfer() - I2C transfer function used by kernel framework673 * @i2c_adap: Adapter pointer to the controller674 * @msgs: Pointer to data to be written.675 * @num_msgs: Number of messages to be executed676 *677 * This is the function called by the generic kernel i2c_transfer()678 * or i2c_smbus...() API calls. Note that this code is protected by the679 * semaphore set in the kernel i2c_transfer() function.680 *681 * NOTE:682 * READ TRANSFER : We impose a restriction of the first message to be the683 * index message for any read transaction.684 * - a no index is coded as '0',685 * - 2byte big endian index is coded as '3'686 * !!! msg[0].buf holds the actual index.687 * This is compatible with generic messages of smbus emulator688 * that send a one byte index.689 * eg. a I2C transation to read 2 bytes from index 0690 * idx = 0;691 * msg[0].addr = client->addr;692 * msg[0].flags = 0x0;693 * msg[0].len = 1;694 * msg[0].buf = &idx;695 *696 * msg[1].addr = client->addr;697 * msg[1].flags = I2C_M_RD;698 * msg[1].len = 2;699 * msg[1].buf = rd_buff700 * i2c_transfer(adap, msg, 2);701 *702 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.703 * If you want to emulate an SMBUS write transaction put the704 * index as first byte(or first and second) in the payload.705 * eg. a I2C transation to write 2 bytes from index 1706 * wr_buff[0] = 0x1;707 * wr_buff[1] = 0x23;708 * wr_buff[2] = 0x46;709 * msg[0].flags = 0x0;710 * msg[0].len = 3;711 * msg[0].buf = wr_buff;712 * i2c_transfer(adap, msg, 1);713 *714 * To read or write a block of data (multiple bytes) using SMBUS emulation715 * please use the i2c_smbus_read_i2c_block_data()716 * or i2c_smbus_write_i2c_block_data() API717 */718static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,719 struct i2c_msg msgs[], int num_msgs)720{721 int status = 0;722 int i;723 struct nmk_i2c_dev *priv = i2c_get_adapdata(i2c_adap);724 int j;725 726 pm_runtime_get_sync(&priv->adev->dev);727 728 /* Attempt three times to send the message queue */729 for (j = 0; j < 3; j++) {730 /* setup the i2c controller */731 setup_i2c_controller(priv);732 733 for (i = 0; i < num_msgs; i++) {734 priv->cli.slave_adr = msgs[i].addr;735 priv->cli.buffer = msgs[i].buf;736 priv->cli.count = msgs[i].len;737 priv->stop = (i < (num_msgs - 1)) ? 0 : 1;738 priv->result = 0;739 740 status = nmk_i2c_xfer_one(priv, msgs[i].flags);741 if (status != 0)742 break;743 }744 if (status == 0)745 break;746 }747 748 pm_runtime_put_sync(&priv->adev->dev);749 750 /* return the no. messages processed */751 if (status)752 return status;753 else754 return num_msgs;755}756 757/**758 * disable_interrupts() - disable the interrupts759 * @priv: private data of controller760 * @irq: interrupt number761 */762static int disable_interrupts(struct nmk_i2c_dev *priv, u32 irq)763{764 irq &= I2C_CLEAR_ALL_INTS;765 writel(readl(priv->virtbase + I2C_IMSCR) & ~irq,766 priv->virtbase + I2C_IMSCR);767 return 0;768}769 770/**771 * i2c_irq_handler() - interrupt routine772 * @irq: interrupt number773 * @arg: data passed to the handler774 *775 * This is the interrupt handler for the i2c driver. Currently776 * it handles the major interrupts like Rx & Tx FIFO management777 * interrupts, master transaction interrupts, arbitration and778 * bus error interrupts. The rest of the interrupts are treated as779 * unhandled.780 */781static irqreturn_t i2c_irq_handler(int irq, void *arg)782{783 struct nmk_i2c_dev *priv = arg;784 struct device *dev = &priv->adev->dev;785 u32 tft, rft;786 u32 count;787 u32 misr, src;788 789 /* load Tx FIFO and Rx FIFO threshold values */790 tft = readl(priv->virtbase + I2C_TFTR);791 rft = readl(priv->virtbase + I2C_RFTR);792 793 /* read interrupt status register */794 misr = readl(priv->virtbase + I2C_MISR);795 796 src = __ffs(misr);797 switch (BIT(src)) {798 799 /* Transmit FIFO nearly empty interrupt */800 case I2C_IT_TXFNE:801 {802 if (priv->cli.operation == I2C_READ) {803 /*804 * in read operation why do we care for writing?805 * so disable the Transmit FIFO interrupt806 */807 disable_interrupts(priv, I2C_IT_TXFNE);808 } else {809 fill_tx_fifo(priv, (MAX_I2C_FIFO_THRESHOLD - tft));810 /*811 * if done, close the transfer by disabling the812 * corresponding TXFNE interrupt813 */814 if (priv->cli.count == 0)815 disable_interrupts(priv, I2C_IT_TXFNE);816 }817 }818 break;819 820 /*821 * Rx FIFO nearly full interrupt.822 * This is set when the numer of entries in Rx FIFO is823 * greater or equal than the threshold value programmed824 * in RFT825 */826 case I2C_IT_RXFNF:827 for (count = rft; count > 0; count--) {828 /* Read the Rx FIFO */829 *priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR);830 priv->cli.buffer++;831 }832 priv->cli.count -= rft;833 priv->cli.xfer_bytes += rft;834 break;835 836 /* Rx FIFO full */837 case I2C_IT_RXFF:838 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {839 *priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR);840 priv->cli.buffer++;841 }842 priv->cli.count -= MAX_I2C_FIFO_THRESHOLD;843 priv->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;844 break;845 846 /* Master Transaction Done with/without stop */847 case I2C_IT_MTD:848 case I2C_IT_MTDWS:849 if (priv->cli.operation == I2C_READ) {850 while (!(readl(priv->virtbase + I2C_RISR)851 & I2C_IT_RXFE)) {852 if (priv->cli.count == 0)853 break;854 *priv->cli.buffer =855 nmk_i2c_readb(priv, I2C_RFR);856 priv->cli.buffer++;857 priv->cli.count--;858 priv->cli.xfer_bytes++;859 }860 }861 862 disable_all_interrupts(priv);863 clear_all_interrupts(priv);864 865 if (priv->cli.count) {866 priv->result = -EIO;867 dev_err(dev, "%lu bytes still remain to be xfered\n",868 priv->cli.count);869 init_hw(priv);870 }871 priv->xfer_done = true;872 wake_up(&priv->xfer_wq);873 874 875 break;876 877 /* Master Arbitration lost interrupt */878 case I2C_IT_MAL:879 priv->result = -EIO;880 init_hw(priv);881 882 i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_MAL);883 priv->xfer_done = true;884 wake_up(&priv->xfer_wq);885 886 887 break;888 889 /*890 * Bus Error interrupt.891 * This happens when an unexpected start/stop condition occurs892 * during the transaction.893 */894 case I2C_IT_BERR:895 {896 u32 sr;897 898 sr = readl(priv->virtbase + I2C_SR);899 priv->result = -EIO;900 if (FIELD_GET(I2C_SR_STATUS, sr) == I2C_ABORT)901 init_hw(priv);902 903 i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR);904 priv->xfer_done = true;905 wake_up(&priv->xfer_wq);906 907 }908 break;909 910 /*911 * Tx FIFO overrun interrupt.912 * This is set when a write operation in Tx FIFO is performed and913 * the Tx FIFO is full.914 */915 case I2C_IT_TXFOVR:916 priv->result = -EIO;917 init_hw(priv);918 919 dev_err(dev, "Tx Fifo Over run\n");920 priv->xfer_done = true;921 wake_up(&priv->xfer_wq);922 923 924 break;925 926 /* unhandled interrupts by this driver - TODO*/927 case I2C_IT_TXFE:928 case I2C_IT_TXFF:929 case I2C_IT_RXFE:930 case I2C_IT_RFSR:931 case I2C_IT_RFSE:932 case I2C_IT_WTSR:933 case I2C_IT_STD:934 dev_err(dev, "unhandled Interrupt\n");935 break;936 default:937 dev_err(dev, "spurious Interrupt..\n");938 break;939 }940 941 return IRQ_HANDLED;942}943 944static int nmk_i2c_suspend_late(struct device *dev)945{946 int ret;947 948 ret = pm_runtime_force_suspend(dev);949 if (ret)950 return ret;951 952 pinctrl_pm_select_sleep_state(dev);953 return 0;954}955 956static int nmk_i2c_resume_early(struct device *dev)957{958 return pm_runtime_force_resume(dev);959}960 961static int nmk_i2c_runtime_suspend(struct device *dev)962{963 struct amba_device *adev = to_amba_device(dev);964 struct nmk_i2c_dev *priv = amba_get_drvdata(adev);965 966 clk_disable_unprepare(priv->clk);967 pinctrl_pm_select_idle_state(dev);968 return 0;969}970 971static int nmk_i2c_runtime_resume(struct device *dev)972{973 struct amba_device *adev = to_amba_device(dev);974 struct nmk_i2c_dev *priv = amba_get_drvdata(adev);975 int ret;976 977 ret = clk_prepare_enable(priv->clk);978 if (ret) {979 dev_err(dev, "can't prepare_enable clock\n");980 return ret;981 }982 983 pinctrl_pm_select_default_state(dev);984 985 ret = init_hw(priv);986 if (ret) {987 clk_disable_unprepare(priv->clk);988 pinctrl_pm_select_idle_state(dev);989 }990 991 return ret;992}993 994static const struct dev_pm_ops nmk_i2c_pm = {995 LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early)996 RUNTIME_PM_OPS(nmk_i2c_runtime_suspend, nmk_i2c_runtime_resume, NULL)997};998 999static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)1000{1001 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;1002}1003 1004static const struct i2c_algorithm nmk_i2c_algo = {1005 .master_xfer = nmk_i2c_xfer,1006 .functionality = nmk_i2c_functionality1007};1008 1009static void nmk_i2c_of_probe(struct device_node *np,1010 struct nmk_i2c_dev *priv)1011{1012 u32 timeout_usecs;1013 1014 /* Default to 100 kHz if no frequency is given in the node */1015 if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))1016 priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;1017 1018 /* This driver only supports 'standard' and 'fast' modes of operation. */1019 if (priv->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)1020 priv->sm = I2C_FREQ_MODE_STANDARD;1021 else1022 priv->sm = I2C_FREQ_MODE_FAST;1023 priv->tft = 1; /* Tx FIFO threshold */1024 priv->rft = 8; /* Rx FIFO threshold */1025 1026 /* Slave response timeout */1027 if (!of_property_read_u32(np, "i2c-transfer-timeout-us", &timeout_usecs))1028 priv->timeout_usecs = timeout_usecs;1029 else1030 priv->timeout_usecs = 200 * USEC_PER_MSEC;1031}1032 1033static const unsigned int nmk_i2c_eyeq5_masks[] = {1034 GENMASK(5, 4),1035 GENMASK(7, 6),1036 GENMASK(9, 8),1037 GENMASK(11, 10),1038 GENMASK(13, 12),1039};1040 1041static int nmk_i2c_eyeq5_probe(struct nmk_i2c_dev *priv)1042{1043 struct device *dev = &priv->adev->dev;1044 struct device_node *np = dev->of_node;1045 unsigned int mask, speed_mode;1046 struct regmap *olb;1047 unsigned int id;1048 1049 priv->has_32b_bus = true;1050 1051 olb = syscon_regmap_lookup_by_phandle_args(np, "mobileye,olb", 1, &id);1052 if (IS_ERR(olb))1053 return PTR_ERR(olb);1054 if (id >= ARRAY_SIZE(nmk_i2c_eyeq5_masks))1055 return -ENOENT;1056 1057 if (priv->clk_freq <= 400000)1058 speed_mode = I2C_EYEQ5_SPEED_FAST;1059 else if (priv->clk_freq <= 1000000)1060 speed_mode = I2C_EYEQ5_SPEED_FAST_PLUS;1061 else1062 speed_mode = I2C_EYEQ5_SPEED_HIGH_SPEED;1063 1064 mask = nmk_i2c_eyeq5_masks[id];1065 regmap_update_bits(olb, NMK_I2C_EYEQ5_OLB_IOCR2,1066 mask, speed_mode << __fls(mask));1067 1068 return 0;1069}1070 1071static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)1072{1073 int ret = 0;1074 struct nmk_i2c_dev *priv;1075 struct device_node *np = adev->dev.of_node;1076 struct device *dev = &adev->dev;1077 struct i2c_adapter *adap;1078 struct i2c_vendor_data *vendor = id->data;1079 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;1080 1081 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);1082 if (!priv)1083 return -ENOMEM;1084 1085 priv->vendor = vendor;1086 priv->adev = adev;1087 priv->has_32b_bus = false;1088 nmk_i2c_of_probe(np, priv);1089 1090 if (of_device_is_compatible(np, "mobileye,eyeq5-i2c")) {1091 ret = nmk_i2c_eyeq5_probe(priv);1092 if (ret)1093 return dev_err_probe(dev, ret, "failed OLB lookup\n");1094 }1095 1096 if (priv->tft > max_fifo_threshold) {1097 dev_warn(dev, "requested TX FIFO threshold %u, adjusted down to %u\n",1098 priv->tft, max_fifo_threshold);1099 priv->tft = max_fifo_threshold;1100 }1101 1102 if (priv->rft > max_fifo_threshold) {1103 dev_warn(dev, "requested RX FIFO threshold %u, adjusted down to %u\n",1104 priv->rft, max_fifo_threshold);1105 priv->rft = max_fifo_threshold;1106 }1107 1108 amba_set_drvdata(adev, priv);1109 1110 priv->virtbase = devm_ioremap(dev, adev->res.start,1111 resource_size(&adev->res));1112 if (!priv->virtbase)1113 return -ENOMEM;1114 1115 priv->irq = adev->irq[0];1116 ret = devm_request_irq(dev, priv->irq, i2c_irq_handler, 0,1117 DRIVER_NAME, priv);1118 if (ret)1119 return dev_err_probe(dev, ret,1120 "cannot claim the irq %d\n", priv->irq);1121 1122 priv->clk = devm_clk_get_enabled(dev, NULL);1123 if (IS_ERR(priv->clk))1124 return dev_err_probe(dev, PTR_ERR(priv->clk),1125 "could enable i2c clock\n");1126 1127 init_hw(priv);1128 1129 adap = &priv->adap;1130 adap->dev.of_node = np;1131 adap->dev.parent = dev;1132 adap->owner = THIS_MODULE;1133 adap->class = I2C_CLASS_DEPRECATED;1134 adap->algo = &nmk_i2c_algo;1135 adap->timeout = usecs_to_jiffies(priv->timeout_usecs);1136 snprintf(adap->name, sizeof(adap->name),1137 "Nomadik I2C at %pR", &adev->res);1138 1139 i2c_set_adapdata(adap, priv);1140 1141 dev_info(dev,1142 "initialize %s on virtual base %p\n",1143 adap->name, priv->virtbase);1144 1145 ret = i2c_add_adapter(adap);1146 if (ret)1147 return ret;1148 1149 pm_runtime_put(dev);1150 1151 return 0;1152}1153 1154static void nmk_i2c_remove(struct amba_device *adev)1155{1156 struct nmk_i2c_dev *priv = amba_get_drvdata(adev);1157 1158 i2c_del_adapter(&priv->adap);1159 flush_i2c_fifo(priv);1160 disable_all_interrupts(priv);1161 clear_all_interrupts(priv);1162 /* disable the controller */1163 i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE);1164}1165 1166static struct i2c_vendor_data vendor_stn8815 = {1167 .has_mtdws = false,1168 .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */1169};1170 1171static struct i2c_vendor_data vendor_db8500 = {1172 .has_mtdws = true,1173 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */1174};1175 1176static const struct amba_id nmk_i2c_ids[] = {1177 {1178 .id = 0x00180024,1179 .mask = 0x00ffffff,1180 .data = &vendor_stn8815,1181 },1182 {1183 .id = 0x00380024,1184 .mask = 0x00ffffff,1185 .data = &vendor_db8500,1186 },1187 {},1188};1189 1190MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);1191 1192static struct amba_driver nmk_i2c_driver = {1193 .drv = {1194 .name = DRIVER_NAME,1195 .pm = pm_ptr(&nmk_i2c_pm),1196 },1197 .id_table = nmk_i2c_ids,1198 .probe = nmk_i2c_probe,1199 .remove = nmk_i2c_remove,1200};1201 1202static int __init nmk_i2c_init(void)1203{1204 return amba_driver_register(&nmk_i2c_driver);1205}1206 1207static void __exit nmk_i2c_exit(void)1208{1209 amba_driver_unregister(&nmk_i2c_driver);1210}1211 1212subsys_initcall(nmk_i2c_init);1213module_exit(nmk_i2c_exit);1214 1215MODULE_AUTHOR("Sachin Verma");1216MODULE_AUTHOR("Srinidhi KASAGAR");1217MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");1218MODULE_LICENSE("GPL");1219