852 lines · c
1/*2 * (C) Copyright 2009-20103 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com4 *5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.6 *7 * This file contains the shared part of the driver for the i2c adapter in8 * Cavium Networks' OCTEON processors and ThunderX SOCs.9 *10 * This file is licensed under the terms of the GNU General Public11 * License version 2. This program is licensed "as is" without any12 * warranty of any kind, whether express or implied.13 */14 15#include <linux/delay.h>16#include <linux/i2c.h>17#include <linux/interrupt.h>18#include <linux/kernel.h>19#include <linux/module.h>20#include <linux/pci.h>21 22#include "i2c-octeon-core.h"23 24#define INITIAL_DELTA_HZ 100000025#define TWSI_MASTER_CLK_REG_DEF_VAL 0x1826#define TWSI_MASTER_CLK_REG_OTX2_VAL 0x327 28/* interrupt service routine */29irqreturn_t octeon_i2c_isr(int irq, void *dev_id)30{31 struct octeon_i2c *i2c = dev_id;32 33 i2c->int_disable(i2c);34 wake_up(&i2c->queue);35 36 return IRQ_HANDLED;37}38 39static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)40{41 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);42}43 44/**45 * octeon_i2c_wait - wait for the IFLG to be set46 * @i2c: The struct octeon_i2c47 *48 * Returns 0 on success, otherwise a negative errno.49 */50static int octeon_i2c_wait(struct octeon_i2c *i2c)51{52 long time_left;53 54 /*55 * Some chip revisions don't assert the irq in the interrupt56 * controller. So we must poll for the IFLG change.57 */58 if (i2c->broken_irq_mode) {59 u64 end = get_jiffies_64() + i2c->adap.timeout;60 61 while (!octeon_i2c_test_iflg(i2c) &&62 time_before64(get_jiffies_64(), end))63 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);64 65 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;66 }67 68 i2c->int_enable(i2c);69 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),70 i2c->adap.timeout);71 i2c->int_disable(i2c);72 73 if (i2c->broken_irq_check && !time_left &&74 octeon_i2c_test_iflg(i2c)) {75 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");76 i2c->broken_irq_mode = true;77 return 0;78 }79 80 if (!time_left)81 return -ETIMEDOUT;82 83 return 0;84}85 86static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)87{88 return (__raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)) & SW_TWSI_V) == 0;89}90 91static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)92{93 /* clear ST/TS events, listen for neither */94 octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);95}96 97/*98 * Cleanup low-level state & enable high-level controller.99 */100static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)101{102 int try = 0;103 u64 val;104 105 if (i2c->hlc_enabled)106 return;107 i2c->hlc_enabled = true;108 109 while (1) {110 val = octeon_i2c_ctl_read(i2c);111 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP)))112 break;113 114 /* clear IFLG event */115 if (val & TWSI_CTL_IFLG)116 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);117 118 if (try++ > 100) {119 pr_err("%s: giving up\n", __func__);120 break;121 }122 123 /* spin until any start/stop has finished */124 udelay(10);125 }126 octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);127}128 129static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)130{131 if (!i2c->hlc_enabled)132 return;133 134 i2c->hlc_enabled = false;135 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);136}137 138/**139 * octeon_i2c_hlc_wait - wait for an HLC operation to complete140 * @i2c: The struct octeon_i2c141 *142 * Returns 0 on success, otherwise -ETIMEDOUT.143 */144static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)145{146 int time_left;147 148 /*149 * Some cn38xx boards don't assert the irq in the interrupt150 * controller. So we must poll for the valid bit change.151 */152 if (i2c->broken_irq_mode) {153 u64 end = get_jiffies_64() + i2c->adap.timeout;154 155 while (!octeon_i2c_hlc_test_valid(i2c) &&156 time_before64(get_jiffies_64(), end))157 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT);158 159 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;160 }161 162 i2c->hlc_int_enable(i2c);163 time_left = wait_event_timeout(i2c->queue,164 octeon_i2c_hlc_test_valid(i2c),165 i2c->adap.timeout);166 i2c->hlc_int_disable(i2c);167 if (!time_left)168 octeon_i2c_hlc_int_clear(i2c);169 170 if (i2c->broken_irq_check && !time_left &&171 octeon_i2c_hlc_test_valid(i2c)) {172 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");173 i2c->broken_irq_mode = true;174 return 0;175 }176 177 if (!time_left)178 return -ETIMEDOUT;179 return 0;180}181 182static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)183{184 u8 stat;185 u64 mode;186 187 /*188 * This is ugly... in HLC mode the status is not in the status register189 * but in the lower 8 bits of OCTEON_REG_SW_TWSI.190 */191 if (i2c->hlc_enabled)192 stat = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));193 else194 stat = octeon_i2c_stat_read(i2c);195 196 switch (stat) {197 /* Everything is fine */198 case STAT_IDLE:199 case STAT_AD2W_ACK:200 case STAT_RXADDR_ACK:201 case STAT_TXADDR_ACK:202 case STAT_TXDATA_ACK:203 return 0;204 205 /* ACK allowed on pre-terminal bytes only */206 case STAT_RXDATA_ACK:207 if (!final_read)208 return 0;209 return -EIO;210 211 /* NAK allowed on terminal byte only */212 case STAT_RXDATA_NAK:213 if (final_read)214 return 0;215 return -EIO;216 217 /* Arbitration lost */218 case STAT_LOST_ARB_38:219 case STAT_LOST_ARB_68:220 case STAT_LOST_ARB_78:221 case STAT_LOST_ARB_B0:222 return -EAGAIN;223 224 /* Being addressed as local target, should back off & listen */225 case STAT_SLAVE_60:226 case STAT_SLAVE_70:227 case STAT_GENDATA_ACK:228 case STAT_GENDATA_NAK:229 return -EOPNOTSUPP;230 231 /* Core busy as local target */232 case STAT_SLAVE_80:233 case STAT_SLAVE_88:234 case STAT_SLAVE_A0:235 case STAT_SLAVE_A8:236 case STAT_SLAVE_LOST:237 case STAT_SLAVE_NAK:238 case STAT_SLAVE_ACK:239 return -EOPNOTSUPP;240 241 case STAT_TXDATA_NAK:242 case STAT_BUS_ERROR:243 return -EIO;244 case STAT_TXADDR_NAK:245 case STAT_RXADDR_NAK:246 case STAT_AD2W_NAK:247 return -ENXIO;248 249 case STAT_WDOG_TOUT:250 mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));251 /* Set BUS_MON_RST to reset bus monitor */252 mode |= BUS_MON_RST_MASK;253 octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c));254 return -EIO;255 default:256 dev_err(i2c->dev, "unhandled state: %d\n", stat);257 return -EIO;258 }259}260 261static int octeon_i2c_recovery(struct octeon_i2c *i2c)262{263 int ret;264 265 ret = i2c_recover_bus(&i2c->adap);266 if (ret)267 /* recover failed, try hardware re-init */268 ret = octeon_i2c_init_lowlevel(i2c);269 return ret;270}271 272/**273 * octeon_i2c_start - send START to the bus274 * @i2c: The struct octeon_i2c275 *276 * Returns 0 on success, otherwise a negative errno.277 */278static int octeon_i2c_start(struct octeon_i2c *i2c)279{280 int ret;281 u8 stat;282 283 octeon_i2c_hlc_disable(i2c);284 285 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);286 ret = octeon_i2c_wait(i2c);287 if (ret)288 goto error;289 290 stat = octeon_i2c_stat_read(i2c);291 if (stat == STAT_START || stat == STAT_REP_START)292 /* START successful, bail out */293 return 0;294 295error:296 /* START failed, try to recover */297 ret = octeon_i2c_recovery(i2c);298 return (ret) ? ret : -EAGAIN;299}300 301/* send STOP to the bus */302static void octeon_i2c_stop(struct octeon_i2c *i2c)303{304 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);305}306 307/**308 * octeon_i2c_read - receive data from the bus via low-level controller309 * @i2c: The struct octeon_i2c310 * @target: Target address311 * @data: Pointer to the location to store the data312 * @rlength: Length of the data313 * @recv_len: flag for length byte314 *315 * The address is sent over the bus, then the data is read.316 *317 * Returns 0 on success, otherwise a negative errno.318 */319static int octeon_i2c_read(struct octeon_i2c *i2c, int target,320 u8 *data, u16 *rlength, bool recv_len)321{322 int i, result, length = *rlength;323 bool final_read = false;324 325 octeon_i2c_data_write(i2c, (target << 1) | 1);326 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);327 328 result = octeon_i2c_wait(i2c);329 if (result)330 return result;331 332 /* address OK ? */333 result = octeon_i2c_check_status(i2c, false);334 if (result)335 return result;336 337 for (i = 0; i < length; i++) {338 /*339 * For the last byte to receive TWSI_CTL_AAK must not be set.340 *341 * A special case is I2C_M_RECV_LEN where we don't know the342 * additional length yet. If recv_len is set we assume we're343 * not reading the final byte and therefore need to set344 * TWSI_CTL_AAK.345 */346 if ((i + 1 == length) && !(recv_len && i == 0))347 final_read = true;348 349 /* clear iflg to allow next event */350 if (final_read)351 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);352 else353 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);354 355 result = octeon_i2c_wait(i2c);356 if (result)357 return result;358 359 data[i] = octeon_i2c_data_read(i2c, &result);360 if (result)361 return result;362 if (recv_len && i == 0) {363 if (data[i] > I2C_SMBUS_BLOCK_MAX)364 return -EPROTO;365 length += data[i];366 }367 368 result = octeon_i2c_check_status(i2c, final_read);369 if (result)370 return result;371 }372 *rlength = length;373 return 0;374}375 376/**377 * octeon_i2c_write - send data to the bus via low-level controller378 * @i2c: The struct octeon_i2c379 * @target: Target address380 * @data: Pointer to the data to be sent381 * @length: Length of the data382 *383 * The address is sent over the bus, then the data.384 *385 * Returns 0 on success, otherwise a negative errno.386 */387static int octeon_i2c_write(struct octeon_i2c *i2c, int target,388 const u8 *data, int length)389{390 int i, result;391 392 octeon_i2c_data_write(i2c, target << 1);393 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);394 395 result = octeon_i2c_wait(i2c);396 if (result)397 return result;398 399 for (i = 0; i < length; i++) {400 result = octeon_i2c_check_status(i2c, false);401 if (result)402 return result;403 404 octeon_i2c_data_write(i2c, data[i]);405 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);406 407 result = octeon_i2c_wait(i2c);408 if (result)409 return result;410 }411 412 return 0;413}414 415/* high-level-controller pure read of up to 8 bytes */416static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)417{418 int i, j, ret = 0;419 u64 cmd;420 421 octeon_i2c_hlc_enable(i2c);422 octeon_i2c_hlc_int_clear(i2c);423 424 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;425 /* SIZE */426 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;427 /* A */428 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;429 430 if (msgs[0].flags & I2C_M_TEN)431 cmd |= SW_TWSI_OP_10;432 else433 cmd |= SW_TWSI_OP_7;434 435 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));436 ret = octeon_i2c_hlc_wait(i2c);437 if (ret)438 goto err;439 440 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));441 if ((cmd & SW_TWSI_R) == 0)442 return octeon_i2c_check_status(i2c, false);443 444 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)445 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;446 447 if (msgs[0].len > 4) {448 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));449 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)450 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;451 }452 453err:454 return ret;455}456 457/* high-level-controller pure write of up to 8 bytes */458static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)459{460 int i, j, ret = 0;461 u64 cmd;462 463 octeon_i2c_hlc_enable(i2c);464 octeon_i2c_hlc_int_clear(i2c);465 466 cmd = SW_TWSI_V | SW_TWSI_SOVR;467 /* SIZE */468 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;469 /* A */470 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;471 472 if (msgs[0].flags & I2C_M_TEN)473 cmd |= SW_TWSI_OP_10;474 else475 cmd |= SW_TWSI_OP_7;476 477 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)478 cmd |= (u64)msgs[0].buf[j] << (8 * i);479 480 if (msgs[0].len > 4) {481 u64 ext = 0;482 483 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)484 ext |= (u64)msgs[0].buf[j] << (8 * i);485 octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));486 }487 488 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));489 ret = octeon_i2c_hlc_wait(i2c);490 if (ret)491 goto err;492 493 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));494 if ((cmd & SW_TWSI_R) == 0)495 return octeon_i2c_check_status(i2c, false);496 497err:498 return ret;499}500 501/* high-level-controller composite write+read, msg0=addr, msg1=data */502static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)503{504 int i, j, ret = 0;505 u64 cmd;506 507 octeon_i2c_hlc_enable(i2c);508 509 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;510 /* SIZE */511 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;512 /* A */513 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;514 515 if (msgs[0].flags & I2C_M_TEN)516 cmd |= SW_TWSI_OP_10_IA;517 else518 cmd |= SW_TWSI_OP_7_IA;519 520 if (msgs[0].len == 2) {521 u64 ext = 0;522 523 cmd |= SW_TWSI_EIA;524 ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;525 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;526 octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));527 } else {528 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;529 }530 531 octeon_i2c_hlc_int_clear(i2c);532 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));533 534 ret = octeon_i2c_hlc_wait(i2c);535 if (ret)536 goto err;537 538 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));539 if ((cmd & SW_TWSI_R) == 0)540 return octeon_i2c_check_status(i2c, false);541 542 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)543 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;544 545 if (msgs[1].len > 4) {546 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));547 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)548 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;549 }550 551err:552 return ret;553}554 555/* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */556static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)557{558 bool set_ext = false;559 int i, j, ret = 0;560 u64 cmd, ext = 0;561 562 octeon_i2c_hlc_enable(i2c);563 564 cmd = SW_TWSI_V | SW_TWSI_SOVR;565 /* SIZE */566 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;567 /* A */568 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;569 570 if (msgs[0].flags & I2C_M_TEN)571 cmd |= SW_TWSI_OP_10_IA;572 else573 cmd |= SW_TWSI_OP_7_IA;574 575 if (msgs[0].len == 2) {576 cmd |= SW_TWSI_EIA;577 ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;578 set_ext = true;579 cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;580 } else {581 cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;582 }583 584 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)585 cmd |= (u64)msgs[1].buf[j] << (8 * i);586 587 if (msgs[1].len > 4) {588 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)589 ext |= (u64)msgs[1].buf[j] << (8 * i);590 set_ext = true;591 }592 if (set_ext)593 octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));594 595 octeon_i2c_hlc_int_clear(i2c);596 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));597 598 ret = octeon_i2c_hlc_wait(i2c);599 if (ret)600 goto err;601 602 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));603 if ((cmd & SW_TWSI_R) == 0)604 return octeon_i2c_check_status(i2c, false);605 606err:607 return ret;608}609 610/**611 * octeon_i2c_xfer - The driver's xfer function612 * @adap: Pointer to the i2c_adapter structure613 * @msgs: Pointer to the messages to be processed614 * @num: Length of the MSGS array615 *616 * Returns the number of messages processed, or a negative errno on failure.617 */618int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)619{620 struct octeon_i2c *i2c = i2c_get_adapdata(adap);621 int i, ret = 0;622 623 if (IS_LS_FREQ(i2c->twsi_freq)) {624 if (num == 1) {625 if (msgs[0].len > 0 && msgs[0].len <= 8) {626 if (msgs[0].flags & I2C_M_RD)627 ret = octeon_i2c_hlc_read(i2c, msgs);628 else629 ret = octeon_i2c_hlc_write(i2c, msgs);630 goto out;631 }632 } else if (num == 2) {633 if ((msgs[0].flags & I2C_M_RD) == 0 &&634 (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&635 msgs[0].len > 0 && msgs[0].len <= 2 &&636 msgs[1].len > 0 && msgs[1].len <= 8 &&637 msgs[0].addr == msgs[1].addr) {638 if (msgs[1].flags & I2C_M_RD)639 ret = octeon_i2c_hlc_comp_read(i2c, msgs);640 else641 ret = octeon_i2c_hlc_comp_write(i2c, msgs);642 goto out;643 }644 }645 }646 647 for (i = 0; ret == 0 && i < num; i++) {648 struct i2c_msg *pmsg = &msgs[i];649 650 /* zero-length messages are not supported */651 if (!pmsg->len) {652 ret = -EOPNOTSUPP;653 break;654 }655 656 ret = octeon_i2c_start(i2c);657 if (ret)658 return ret;659 660 if (pmsg->flags & I2C_M_RD)661 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,662 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);663 else664 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,665 pmsg->len);666 }667 octeon_i2c_stop(i2c);668out:669 return (ret != 0) ? ret : num;670}671 672/* calculate and set clock divisors */673void octeon_i2c_set_clock(struct octeon_i2c *i2c)674{675 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;676 bool is_plat_otx2;677 /*678 * Find divisors to produce target frequency, start with large delta679 * to cover wider range of divisors, note thp = TCLK half period and680 * ds is OSCL output frequency divisor.681 */682 unsigned int thp, mdiv_min, mdiv = 2, ndiv = 0, ds = 10;683 unsigned int delta_hz = INITIAL_DELTA_HZ;684 685 is_plat_otx2 = octeon_i2c_is_otx2(to_pci_dev(i2c->dev));686 687 if (is_plat_otx2) {688 thp = TWSI_MASTER_CLK_REG_OTX2_VAL;689 mdiv_min = 0;690 if (!IS_LS_FREQ(i2c->twsi_freq))691 ds = 15;692 } else {693 thp = TWSI_MASTER_CLK_REG_DEF_VAL;694 mdiv_min = 2;695 }696 697 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {698 /*699 * An mdiv value of less than 2 seems to not work well700 * with ds1337 RTCs, so we constrain it to larger values.701 */702 for (mdiv_idx = 15; mdiv_idx >= mdiv_min && delta_hz != 0; mdiv_idx--) {703 /*704 * For given ndiv and mdiv values check the705 * two closest thp values.706 */707 tclk = i2c->twsi_freq * (mdiv_idx + 1) * ds;708 tclk *= (1 << ndiv_idx);709 if (is_plat_otx2)710 thp_base = (i2c->sys_freq / tclk) - 2;711 else712 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;713 714 for (inc = 0; inc <= 1; inc++) {715 thp_idx = thp_base + inc;716 if (thp_idx < 5 || thp_idx > 0xff)717 continue;718 719 if (is_plat_otx2)720 foscl = i2c->sys_freq / (thp_idx + 2);721 else722 foscl = i2c->sys_freq /723 (2 * (thp_idx + 1));724 foscl = foscl / (1 << ndiv_idx);725 foscl = foscl / (mdiv_idx + 1) / ds;726 if (foscl > i2c->twsi_freq)727 continue;728 diff = abs(foscl - i2c->twsi_freq);729 /*730 * Diff holds difference between calculated frequency731 * value vs desired frequency.732 * Delta_hz is updated with last minimum diff.733 */734 if (diff < delta_hz) {735 delta_hz = diff;736 thp = thp_idx;737 mdiv = mdiv_idx;738 ndiv = ndiv_idx;739 }740 }741 }742 }743 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);744 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);745 if (is_plat_otx2) {746 u64 mode;747 748 mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));749 /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */750 if (!IS_LS_FREQ(i2c->twsi_freq))751 mode |= TWSX_MODE_HS_MASK;752 else753 mode &= ~TWSX_MODE_HS_MASK;754 octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c));755 }756}757 758int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)759{760 u8 status = 0;761 int tries;762 763 /* reset controller */764 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);765 766 for (tries = 10; tries && status != STAT_IDLE; tries--) {767 udelay(1);768 status = octeon_i2c_stat_read(i2c);769 if (status == STAT_IDLE)770 break;771 }772 773 if (status != STAT_IDLE) {774 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",775 __func__, status);776 return -EIO;777 }778 779 /* toggle twice to force both teardowns */780 octeon_i2c_hlc_enable(i2c);781 octeon_i2c_hlc_disable(i2c);782 return 0;783}784 785static int octeon_i2c_get_scl(struct i2c_adapter *adap)786{787 struct octeon_i2c *i2c = i2c_get_adapdata(adap);788 u64 state;789 790 state = octeon_i2c_read_int(i2c);791 return state & TWSI_INT_SCL;792}793 794static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val)795{796 struct octeon_i2c *i2c = i2c_get_adapdata(adap);797 798 octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR);799}800 801static int octeon_i2c_get_sda(struct i2c_adapter *adap)802{803 struct octeon_i2c *i2c = i2c_get_adapdata(adap);804 u64 state;805 806 state = octeon_i2c_read_int(i2c);807 return state & TWSI_INT_SDA;808}809 810static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap)811{812 struct octeon_i2c *i2c = i2c_get_adapdata(adap);813 814 octeon_i2c_hlc_disable(i2c);815 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);816 /* wait for software reset to settle */817 udelay(5);818 819 /*820 * Bring control register to a good state regardless821 * of HLC state.822 */823 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);824 825 octeon_i2c_write_int(i2c, 0);826}827 828static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap)829{830 struct octeon_i2c *i2c = i2c_get_adapdata(adap);831 832 /*833 * Generate STOP to finish the unfinished transaction.834 * Can't generate STOP via the TWSI CTL register835 * since it could bring the TWSI controller into an inoperable state.836 */837 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);838 udelay(5);839 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);840 udelay(5);841 octeon_i2c_write_int(i2c, 0);842}843 844struct i2c_bus_recovery_info octeon_i2c_recovery_info = {845 .recover_bus = i2c_generic_scl_recovery,846 .get_scl = octeon_i2c_get_scl,847 .set_scl = octeon_i2c_set_scl,848 .get_sda = octeon_i2c_get_sda,849 .prepare_recovery = octeon_i2c_prepare_recovery,850 .unprepare_recovery = octeon_i2c_unprepare_recovery,851};852