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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * TI OMAP I2C master mode driver4 *5 * Copyright (C) 2003 MontaVista Software, Inc.6 * Copyright (C) 2005 Nokia Corporation7 * Copyright (C) 2004 - 2007 Texas Instruments.8 *9 * Originally written by MontaVista Software, Inc.10 * Additional contributions by:11 * Tony Lindgren <tony@atomide.com>12 * Imre Deak <imre.deak@nokia.com>13 * Juha Yrjölä <juha.yrjola@solidboot.com>14 * Syed Khasim <x0khasim@ti.com>15 * Nishant Menon <nm@ti.com>16 */17 18#include <linux/module.h>19#include <linux/delay.h>20#include <linux/i2c.h>21#include <linux/err.h>22#include <linux/interrupt.h>23#include <linux/completion.h>24#include <linux/platform_device.h>25#include <linux/clk.h>26#include <linux/io.h>27#include <linux/of.h>28#include <linux/slab.h>29#include <linux/platform_data/i2c-omap.h>30#include <linux/pm_runtime.h>31#include <linux/pinctrl/consumer.h>32#include <linux/property.h>33 34/* I2C controller revisions */35#define OMAP_I2C_OMAP1_REV_2 0x2036 37/* I2C controller revisions present on specific hardware */38#define OMAP_I2C_REV_ON_2430 0x0000003639#define OMAP_I2C_REV_ON_3430_3530 0x0000003C40#define OMAP_I2C_REV_ON_3630 0x0000004041#define OMAP_I2C_REV_ON_4430_PLUS 0x5040000242 43/* timeout waiting for the controller to respond */44#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))45 46/* timeout for pm runtime autosuspend */47#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */48 49/* timeout for making decision on bus free status */50#define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))51 52/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */53enum {54 OMAP_I2C_REV_REG = 0,55 OMAP_I2C_IE_REG,56 OMAP_I2C_STAT_REG,57 OMAP_I2C_IV_REG,58 OMAP_I2C_WE_REG,59 OMAP_I2C_SYSS_REG,60 OMAP_I2C_BUF_REG,61 OMAP_I2C_CNT_REG,62 OMAP_I2C_DATA_REG,63 OMAP_I2C_SYSC_REG,64 OMAP_I2C_CON_REG,65 OMAP_I2C_OA_REG,66 OMAP_I2C_SA_REG,67 OMAP_I2C_PSC_REG,68 OMAP_I2C_SCLL_REG,69 OMAP_I2C_SCLH_REG,70 OMAP_I2C_SYSTEST_REG,71 OMAP_I2C_BUFSTAT_REG,72 /* only on OMAP4430 */73 OMAP_I2C_IP_V2_REVNB_LO,74 OMAP_I2C_IP_V2_REVNB_HI,75 OMAP_I2C_IP_V2_IRQSTATUS_RAW,76 OMAP_I2C_IP_V2_IRQENABLE_SET,77 OMAP_I2C_IP_V2_IRQENABLE_CLR,78};79 80/* I2C Interrupt Enable Register (OMAP_I2C_IE): */81#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */82#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */83#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */84#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */85#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */86#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */87#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */88 89/* I2C Status Register (OMAP_I2C_STAT): */90#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */91#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */92#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */93#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */94#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */95#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */96#define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */97#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */98#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */99#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */100#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */101#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */102 103/* I2C WE wakeup enable register */104#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */105#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */106#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/107#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */108#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */109#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */110#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */111#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */112#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */113#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */114 115#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \116 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \117 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \118 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \119 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)120 121/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */122#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */123#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */124#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */125#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */126 127/* I2C Configuration Register (OMAP_I2C_CON): */128#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */129#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */130#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */131#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */132#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */133#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */134#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */135#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */136#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */137#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */138 139/* I2C SCL time value when Master */140#define OMAP_I2C_SCLL_HSSCLL 8141#define OMAP_I2C_SCLH_HSSCLH 8142 143/* I2C System Test Register (OMAP_I2C_SYSTEST): */144#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */145#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */146#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */147#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */148/* Functional mode */149#define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */150#define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */151#define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */152#define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */153/* SDA/SCL IO mode */154#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */155#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */156#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */157#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */158 159/* OCP_SYSSTATUS bit definitions */160#define SYSS_RESETDONE_MASK (1 << 0)161 162/* OCP_SYSCONFIG bit definitions */163#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)164#define SYSC_SIDLEMODE_MASK (0x3 << 3)165#define SYSC_ENAWAKEUP_MASK (1 << 2)166#define SYSC_SOFTRESET_MASK (1 << 1)167#define SYSC_AUTOIDLE_MASK (1 << 0)168 169#define SYSC_IDLEMODE_SMART 0x2170#define SYSC_CLOCKACTIVITY_FCLK 0x2171 172/* Errata definitions */173#define I2C_OMAP_ERRATA_I207 (1 << 0)174#define I2C_OMAP_ERRATA_I462 (1 << 1)175 176#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF177 178struct omap_i2c_dev {179 struct device *dev;180 void __iomem *base; /* virtual */181 int irq;182 int reg_shift; /* bit shift for I2C register addresses */183 struct completion cmd_complete;184 struct resource *ioarea;185 u32 latency; /* maximum mpu wkup latency */186 void (*set_mpu_wkup_lat)(struct device *dev,187 long latency);188 u32 speed; /* Speed of bus in kHz */189 u32 flags;190 u16 scheme;191 u16 cmd_err;192 u8 *buf;193 u8 *regs;194 size_t buf_len;195 struct i2c_adapter adapter;196 u8 threshold;197 u8 fifo_size; /* use as flag and value198 * fifo_size==0 implies no fifo199 * if set, should be trsh+1200 */201 u32 rev;202 unsigned b_hw:1; /* bad h/w fixes */203 unsigned bb_valid:1; /* true when BB-bit reflects204 * the I2C bus state205 */206 unsigned receiver:1; /* true when we're in receiver mode */207 u16 iestate; /* Saved interrupt register */208 u16 pscstate;209 u16 scllstate;210 u16 sclhstate;211 u16 syscstate;212 u16 westate;213 u16 errata;214};215 216static const u8 reg_map_ip_v1[] = {217 [OMAP_I2C_REV_REG] = 0x00,218 [OMAP_I2C_IE_REG] = 0x01,219 [OMAP_I2C_STAT_REG] = 0x02,220 [OMAP_I2C_IV_REG] = 0x03,221 [OMAP_I2C_WE_REG] = 0x03,222 [OMAP_I2C_SYSS_REG] = 0x04,223 [OMAP_I2C_BUF_REG] = 0x05,224 [OMAP_I2C_CNT_REG] = 0x06,225 [OMAP_I2C_DATA_REG] = 0x07,226 [OMAP_I2C_SYSC_REG] = 0x08,227 [OMAP_I2C_CON_REG] = 0x09,228 [OMAP_I2C_OA_REG] = 0x0a,229 [OMAP_I2C_SA_REG] = 0x0b,230 [OMAP_I2C_PSC_REG] = 0x0c,231 [OMAP_I2C_SCLL_REG] = 0x0d,232 [OMAP_I2C_SCLH_REG] = 0x0e,233 [OMAP_I2C_SYSTEST_REG] = 0x0f,234 [OMAP_I2C_BUFSTAT_REG] = 0x10,235};236 237static const u8 reg_map_ip_v2[] = {238 [OMAP_I2C_REV_REG] = 0x04,239 [OMAP_I2C_IE_REG] = 0x2c,240 [OMAP_I2C_STAT_REG] = 0x28,241 [OMAP_I2C_IV_REG] = 0x34,242 [OMAP_I2C_WE_REG] = 0x34,243 [OMAP_I2C_SYSS_REG] = 0x90,244 [OMAP_I2C_BUF_REG] = 0x94,245 [OMAP_I2C_CNT_REG] = 0x98,246 [OMAP_I2C_DATA_REG] = 0x9c,247 [OMAP_I2C_SYSC_REG] = 0x10,248 [OMAP_I2C_CON_REG] = 0xa4,249 [OMAP_I2C_OA_REG] = 0xa8,250 [OMAP_I2C_SA_REG] = 0xac,251 [OMAP_I2C_PSC_REG] = 0xb0,252 [OMAP_I2C_SCLL_REG] = 0xb4,253 [OMAP_I2C_SCLH_REG] = 0xb8,254 [OMAP_I2C_SYSTEST_REG] = 0xbC,255 [OMAP_I2C_BUFSTAT_REG] = 0xc0,256 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,257 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,258 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,259 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,260 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,261};262 263static int omap_i2c_xfer_data(struct omap_i2c_dev *omap);264 265static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,266 int reg, u16 val)267{268 writew_relaxed(val, omap->base +269 (omap->regs[reg] << omap->reg_shift));270}271 272static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)273{274 return readw_relaxed(omap->base +275 (omap->regs[reg] << omap->reg_shift));276}277 278static void __omap_i2c_init(struct omap_i2c_dev *omap)279{280 281 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);282 283 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */284 omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);285 286 /* SCL low and high time values */287 omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);288 omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);289 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)290 omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);291 292 /* Take the I2C module out of reset: */293 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);294 295 /*296 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the297 * bus is busy. It will be changed to 1 on the next IP FCLK clock.298 * udelay(1) will be enough to fix that.299 */300 301 /*302 * Don't write to this register if the IE state is 0 as it can303 * cause deadlock.304 */305 if (omap->iestate)306 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);307}308 309static int omap_i2c_reset(struct omap_i2c_dev *omap)310{311 unsigned long timeout;312 u16 sysc;313 314 if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {315 sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);316 317 /* Disable I2C controller before soft reset */318 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,319 omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &320 ~(OMAP_I2C_CON_EN));321 322 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);323 /* For some reason we need to set the EN bit before the324 * reset done bit gets set. */325 timeout = jiffies + OMAP_I2C_TIMEOUT;326 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);327 while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &328 SYSS_RESETDONE_MASK)) {329 if (time_after(jiffies, timeout)) {330 dev_warn(omap->dev, "timeout waiting "331 "for controller reset\n");332 return -ETIMEDOUT;333 }334 msleep(1);335 }336 337 /* SYSC register is cleared by the reset; rewrite it */338 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);339 340 if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {341 /* Schedule I2C-bus monitoring on the next transfer */342 omap->bb_valid = 0;343 }344 }345 346 return 0;347}348 349static int omap_i2c_init(struct omap_i2c_dev *omap)350{351 u16 psc = 0, scll = 0, sclh = 0;352 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;353 unsigned long fclk_rate = 12000000;354 unsigned long internal_clk = 0;355 struct clk *fclk;356 int error;357 358 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {359 /*360 * Enabling all wakup sources to stop I2C freezing on361 * WFI instruction.362 * REVISIT: Some wkup sources might not be needed.363 */364 omap->westate = OMAP_I2C_WE_ALL;365 }366 367 if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {368 /*369 * The I2C functional clock is the armxor_ck, so there's370 * no need to get "armxor_ck" separately. Now, if OMAP2420371 * always returns 12MHz for the functional clock, we can372 * do this bit unconditionally.373 */374 fclk = clk_get(omap->dev, "fck");375 if (IS_ERR(fclk)) {376 error = PTR_ERR(fclk);377 dev_err(omap->dev, "could not get fck: %i\n", error);378 379 return error;380 }381 382 fclk_rate = clk_get_rate(fclk);383 clk_put(fclk);384 385 /* TRM for 5912 says the I2C clock must be prescaled to be386 * between 7 - 12 MHz. The XOR input clock is typically387 * 12, 13 or 19.2 MHz. So we should have code that produces:388 *389 * XOR MHz Divider Prescaler390 * 12 1 0391 * 13 2 1392 * 19.2 2 1393 */394 if (fclk_rate > 12000000)395 psc = fclk_rate / 12000000;396 }397 398 if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {399 400 /*401 * HSI2C controller internal clk rate should be 19.2 Mhz for402 * HS and for all modes on 2430. On 34xx we can use lower rate403 * to get longer filter period for better noise suppression.404 * The filter is iclk (fclk for HS) period.405 */406 if (omap->speed > 400 ||407 omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)408 internal_clk = 19200;409 else if (omap->speed > 100)410 internal_clk = 9600;411 else412 internal_clk = 4000;413 fclk = clk_get(omap->dev, "fck");414 if (IS_ERR(fclk)) {415 error = PTR_ERR(fclk);416 dev_err(omap->dev, "could not get fck: %i\n", error);417 418 return error;419 }420 fclk_rate = clk_get_rate(fclk) / 1000;421 clk_put(fclk);422 423 /* Compute prescaler divisor */424 psc = fclk_rate / internal_clk;425 psc = psc - 1;426 427 /* If configured for High Speed */428 if (omap->speed > 400) {429 unsigned long scl;430 431 /* For first phase of HS mode */432 scl = internal_clk / 400;433 fsscll = scl - (scl / 3) - 7;434 fssclh = (scl / 3) - 5;435 436 /* For second phase of HS mode */437 scl = fclk_rate / omap->speed;438 hsscll = scl - (scl / 3) - 7;439 hssclh = (scl / 3) - 5;440 } else if (omap->speed > 100) {441 unsigned long scl;442 443 /* Fast mode */444 scl = internal_clk / omap->speed;445 fsscll = scl - (scl / 3) - 7;446 fssclh = (scl / 3) - 5;447 } else {448 /* Standard mode */449 fsscll = internal_clk / (omap->speed * 2) - 7;450 fssclh = internal_clk / (omap->speed * 2) - 5;451 }452 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;453 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;454 } else {455 /* Program desired operating rate */456 fclk_rate /= (psc + 1) * 1000;457 if (psc > 2)458 psc = 2;459 scll = fclk_rate / (omap->speed * 2) - 7 + psc;460 sclh = fclk_rate / (omap->speed * 2) - 7 + psc;461 }462 463 omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |464 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |465 OMAP_I2C_IE_AL) | ((omap->fifo_size) ?466 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);467 468 omap->pscstate = psc;469 omap->scllstate = scll;470 omap->sclhstate = sclh;471 472 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {473 /* Not implemented */474 omap->bb_valid = 1;475 }476 477 __omap_i2c_init(omap);478 479 return 0;480}481 482/*483 * Try bus recovery, but only if SDA is actually low.484 */485static int omap_i2c_recover_bus(struct omap_i2c_dev *omap)486{487 u16 systest;488 489 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);490 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&491 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC))492 return 0; /* bus seems to already be fine */493 if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC))494 return -EBUSY; /* recovery would not fix SCL */495 return i2c_recover_bus(&omap->adapter);496}497 498/*499 * Waiting on Bus Busy500 */501static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)502{503 unsigned long timeout;504 505 timeout = jiffies + OMAP_I2C_TIMEOUT;506 while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {507 if (time_after(jiffies, timeout))508 return omap_i2c_recover_bus(omap);509 msleep(1);510 }511 512 return 0;513}514 515/*516 * Wait while BB-bit doesn't reflect the I2C bus state517 *518 * In a multimaster environment, after IP software reset, BB-bit value doesn't519 * correspond to the current bus state. It may happen what BB-bit will be 0,520 * while the bus is busy due to another I2C master activity.521 * Here are BB-bit values after reset:522 * SDA SCL BB NOTES523 * 0 0 0 1, 2524 * 1 0 0 1, 2525 * 0 1 1526 * 1 1 0 3527 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)528 * combinations on the bus, it set BB-bit to 1.529 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,530 * it set BB-bit to 0 and BF to 1.531 * BB and BF bits correctly tracks the bus state while IP is suspended532 * BB bit became valid on the next FCLK clock after CON_EN bit set533 *534 * NOTES:535 * 1. Any transfer started when BB=0 and bus is busy wouldn't be536 * completed by IP and results in controller timeout.537 * 2. Any transfer started when BB=0 and SCL=0 results in IP538 * starting to drive SDA low. In that case IP corrupt data539 * on the bus.540 * 3. Any transfer started in the middle of another master's transfer541 * results in unpredictable results and data corruption542 */543static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)544{545 unsigned long bus_free_timeout = 0;546 unsigned long timeout;547 int bus_free = 0;548 u16 stat, systest;549 550 if (omap->bb_valid)551 return 0;552 553 timeout = jiffies + OMAP_I2C_TIMEOUT;554 while (1) {555 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);556 /*557 * We will see BB or BF event in a case IP had detected any558 * activity on the I2C bus. Now IP correctly tracks the bus559 * state. BB-bit value is valid.560 */561 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))562 break;563 564 /*565 * Otherwise, we must look signals on the bus to make566 * the right decision.567 */568 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);569 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&570 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {571 if (!bus_free) {572 bus_free_timeout = jiffies +573 OMAP_I2C_BUS_FREE_TIMEOUT;574 bus_free = 1;575 }576 577 /*578 * SDA and SCL lines was high for 10 ms without bus579 * activity detected. The bus is free. Consider580 * BB-bit value is valid.581 */582 if (time_after(jiffies, bus_free_timeout))583 break;584 } else {585 bus_free = 0;586 }587 588 if (time_after(jiffies, timeout)) {589 /*590 * SDA or SCL were low for the entire timeout without591 * any activity detected. Most likely, a slave is592 * locking up the bus with no master driving the clock.593 */594 dev_warn(omap->dev, "timeout waiting for bus ready\n");595 return omap_i2c_recover_bus(omap);596 }597 598 msleep(1);599 }600 601 omap->bb_valid = 1;602 return 0;603}604 605static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)606{607 u16 buf;608 609 if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)610 return;611 612 /*613 * Set up notification threshold based on message size. We're doing614 * this to try and avoid draining feature as much as possible. Whenever615 * we have big messages to transfer (bigger than our total fifo size)616 * then we might use draining feature to transfer the remaining bytes.617 */618 619 omap->threshold = clamp(size, (u8) 1, omap->fifo_size);620 621 buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);622 623 if (is_rx) {624 /* Clear RX Threshold */625 buf &= ~(0x3f << 8);626 buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;627 } else {628 /* Clear TX Threshold */629 buf &= ~0x3f;630 buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;631 }632 633 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);634 635 if (omap->rev < OMAP_I2C_REV_ON_3630)636 omap->b_hw = 1; /* Enable hardware fixes */637 638 /* calculate wakeup latency constraint for MPU */639 if (omap->set_mpu_wkup_lat != NULL)640 omap->latency = (1000000 * omap->threshold) /641 (1000 * omap->speed / 8);642}643 644static void omap_i2c_wait(struct omap_i2c_dev *omap)645{646 u16 stat;647 u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);648 int count = 0;649 650 do {651 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);652 count++;653 } while (!(stat & mask) && count < 5);654}655 656/*657 * Low level master read/write transaction.658 */659static int omap_i2c_xfer_msg(struct i2c_adapter *adap,660 struct i2c_msg *msg, int stop, bool polling)661{662 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);663 unsigned long time_left;664 u16 w;665 int ret;666 667 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",668 msg->addr, msg->len, msg->flags, stop);669 670 omap->receiver = !!(msg->flags & I2C_M_RD);671 omap_i2c_resize_fifo(omap, msg->len, omap->receiver);672 673 omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);674 675 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */676 omap->buf = msg->buf;677 omap->buf_len = msg->len;678 679 /* make sure writes to omap->buf_len are ordered */680 barrier();681 682 omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);683 684 /* Clear the FIFO Buffers */685 w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);686 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;687 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);688 689 if (!polling)690 reinit_completion(&omap->cmd_complete);691 omap->cmd_err = 0;692 693 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;694 695 /* High speed configuration */696 if (omap->speed > 400)697 w |= OMAP_I2C_CON_OPMODE_HS;698 699 if (msg->flags & I2C_M_STOP)700 stop = 1;701 if (msg->flags & I2C_M_TEN)702 w |= OMAP_I2C_CON_XA;703 if (!(msg->flags & I2C_M_RD))704 w |= OMAP_I2C_CON_TRX;705 706 if (!omap->b_hw && stop)707 w |= OMAP_I2C_CON_STP;708 /*709 * NOTE: STAT_BB bit could became 1 here if another master occupy710 * the bus. IP successfully complete transfer when the bus will be711 * free again (BB reset to 0).712 */713 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);714 715 /*716 * Don't write stt and stp together on some hardware.717 */718 if (omap->b_hw && stop) {719 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;720 u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);721 while (con & OMAP_I2C_CON_STT) {722 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);723 724 /* Let the user know if i2c is in a bad state */725 if (time_after(jiffies, delay)) {726 dev_err(omap->dev, "controller timed out "727 "waiting for start condition to finish\n");728 return -ETIMEDOUT;729 }730 cpu_relax();731 }732 733 w |= OMAP_I2C_CON_STP;734 w &= ~OMAP_I2C_CON_STT;735 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);736 }737 738 /*739 * REVISIT: We should abort the transfer on signals, but the bus goes740 * into arbitration and we're currently unable to recover from it.741 */742 if (!polling) {743 time_left = wait_for_completion_timeout(&omap->cmd_complete,744 OMAP_I2C_TIMEOUT);745 } else {746 do {747 omap_i2c_wait(omap);748 ret = omap_i2c_xfer_data(omap);749 } while (ret == -EAGAIN);750 751 time_left = !ret;752 }753 754 if (time_left == 0) {755 omap_i2c_reset(omap);756 __omap_i2c_init(omap);757 return -ETIMEDOUT;758 }759 760 if (likely(!omap->cmd_err))761 return 0;762 763 /* We have an error */764 if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {765 omap_i2c_reset(omap);766 __omap_i2c_init(omap);767 return -EIO;768 }769 770 if (omap->cmd_err & OMAP_I2C_STAT_AL)771 return -EAGAIN;772 773 if (omap->cmd_err & OMAP_I2C_STAT_NACK) {774 if (msg->flags & I2C_M_IGNORE_NAK)775 return 0;776 777 w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);778 w |= OMAP_I2C_CON_STP;779 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);780 return -EREMOTEIO;781 }782 return -EIO;783}784 785 786/*787 * Prepare controller for a transaction and call omap_i2c_xfer_msg788 * to do the work during IRQ processing.789 */790static int791omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num,792 bool polling)793{794 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);795 int i;796 int r;797 798 r = pm_runtime_get_sync(omap->dev);799 if (r < 0)800 goto out;801 802 r = omap_i2c_wait_for_bb_valid(omap);803 if (r < 0)804 goto out;805 806 r = omap_i2c_wait_for_bb(omap);807 if (r < 0)808 goto out;809 810 if (omap->set_mpu_wkup_lat != NULL)811 omap->set_mpu_wkup_lat(omap->dev, omap->latency);812 813 for (i = 0; i < num; i++) {814 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)),815 polling);816 if (r != 0)817 break;818 }819 820 if (r == 0)821 r = num;822 823 omap_i2c_wait_for_bb(omap);824 825 if (omap->set_mpu_wkup_lat != NULL)826 omap->set_mpu_wkup_lat(omap->dev, -1);827 828out:829 pm_runtime_mark_last_busy(omap->dev);830 pm_runtime_put_autosuspend(omap->dev);831 return r;832}833 834static int835omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)836{837 return omap_i2c_xfer_common(adap, msgs, num, false);838}839 840static int841omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)842{843 return omap_i2c_xfer_common(adap, msgs, num, true);844}845 846static u32847omap_i2c_func(struct i2c_adapter *adap)848{849 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |850 I2C_FUNC_PROTOCOL_MANGLING;851}852 853static inline void854omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)855{856 omap->cmd_err |= err;857 complete(&omap->cmd_complete);858}859 860static inline void861omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)862{863 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);864}865 866static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)867{868 /*869 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)870 * Not applicable for OMAP4.871 * Under certain rare conditions, RDR could be set again872 * when the bus is busy, then ignore the interrupt and873 * clear the interrupt.874 */875 if (stat & OMAP_I2C_STAT_RDR) {876 /* Step 1: If RDR is set, clear it */877 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);878 879 /* Step 2: */880 if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)881 & OMAP_I2C_STAT_BB)) {882 883 /* Step 3: */884 if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)885 & OMAP_I2C_STAT_RDR) {886 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);887 dev_dbg(omap->dev, "RDR when bus is busy.\n");888 }889 890 }891 }892}893 894/* rev1 devices are apparently only on some 15xx */895#ifdef CONFIG_ARCH_OMAP15XX896 897static irqreturn_t898omap_i2c_omap1_isr(int this_irq, void *dev_id)899{900 struct omap_i2c_dev *omap = dev_id;901 u16 iv, w;902 903 if (pm_runtime_suspended(omap->dev))904 return IRQ_NONE;905 906 iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);907 switch (iv) {908 case 0x00: /* None */909 break;910 case 0x01: /* Arbitration lost */911 dev_err(omap->dev, "Arbitration lost\n");912 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);913 break;914 case 0x02: /* No acknowledgement */915 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);916 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);917 break;918 case 0x03: /* Register access ready */919 omap_i2c_complete_cmd(omap, 0);920 break;921 case 0x04: /* Receive data ready */922 if (omap->buf_len) {923 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);924 *omap->buf++ = w;925 omap->buf_len--;926 if (omap->buf_len) {927 *omap->buf++ = w >> 8;928 omap->buf_len--;929 }930 } else931 dev_err(omap->dev, "RRDY IRQ while no data requested\n");932 break;933 case 0x05: /* Transmit data ready */934 if (omap->buf_len) {935 w = *omap->buf++;936 omap->buf_len--;937 if (omap->buf_len) {938 w |= *omap->buf++ << 8;939 omap->buf_len--;940 }941 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);942 } else943 dev_err(omap->dev, "XRDY IRQ while no data to send\n");944 break;945 default:946 return IRQ_NONE;947 }948 949 return IRQ_HANDLED;950}951#else952#define omap_i2c_omap1_isr NULL953#endif954 955/*956 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing957 * data to DATA_REG. Otherwise some data bytes can be lost while transferring958 * them from the memory to the I2C interface.959 */960static int errata_omap3_i462(struct omap_i2c_dev *omap)961{962 unsigned long timeout = 10000;963 u16 stat;964 965 do {966 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);967 if (stat & OMAP_I2C_STAT_XUDF)968 break;969 970 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {971 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |972 OMAP_I2C_STAT_XDR));973 if (stat & OMAP_I2C_STAT_NACK) {974 omap->cmd_err |= OMAP_I2C_STAT_NACK;975 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);976 }977 978 if (stat & OMAP_I2C_STAT_AL) {979 dev_err(omap->dev, "Arbitration lost\n");980 omap->cmd_err |= OMAP_I2C_STAT_AL;981 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);982 }983 984 return -EIO;985 }986 987 cpu_relax();988 } while (--timeout);989 990 if (!timeout) {991 dev_err(omap->dev, "timeout waiting on XUDF bit\n");992 return 0;993 }994 995 return 0;996}997 998static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,999 bool is_rdr)1000{1001 u16 w;1002 1003 while (num_bytes--) {1004 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);1005 *omap->buf++ = w;1006 omap->buf_len--;1007 1008 /*1009 * Data reg in 2430, omap3 and1010 * omap4 is 8 bit wide1011 */1012 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {1013 *omap->buf++ = w >> 8;1014 omap->buf_len--;1015 }1016 }1017}1018 1019static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,1020 bool is_xdr)1021{1022 u16 w;1023 1024 while (num_bytes--) {1025 w = *omap->buf++;1026 omap->buf_len--;1027 1028 /*1029 * Data reg in 2430, omap3 and1030 * omap4 is 8 bit wide1031 */1032 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {1033 w |= *omap->buf++ << 8;1034 omap->buf_len--;1035 }1036 1037 if (omap->errata & I2C_OMAP_ERRATA_I462) {1038 int ret;1039 1040 ret = errata_omap3_i462(omap);1041 if (ret < 0)1042 return ret;1043 }1044 1045 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);1046 }1047 1048 return 0;1049}1050 1051static irqreturn_t1052omap_i2c_isr(int irq, void *dev_id)1053{1054 struct omap_i2c_dev *omap = dev_id;1055 irqreturn_t ret = IRQ_HANDLED;1056 u16 mask;1057 u16 stat;1058 1059 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);1060 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG) & ~OMAP_I2C_STAT_NACK;1061 1062 if (stat & mask)1063 ret = IRQ_WAKE_THREAD;1064 1065 return ret;1066}1067 1068static int omap_i2c_xfer_data(struct omap_i2c_dev *omap)1069{1070 u16 bits;1071 u16 stat;1072 int err = 0, count = 0;1073 1074 do {1075 bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);1076 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);1077 stat &= bits;1078 1079 /* If we're in receiver mode, ignore XDR/XRDY */1080 if (omap->receiver)1081 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);1082 else1083 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);1084 1085 if (!stat) {1086 /* my work here is done */1087 err = -EAGAIN;1088 break;1089 }1090 1091 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);1092 if (count++ == 100) {1093 dev_warn(omap->dev, "Too much work in one IRQ\n");1094 break;1095 }1096 1097 if (stat & OMAP_I2C_STAT_NACK) {1098 err |= OMAP_I2C_STAT_NACK;1099 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);1100 }1101 1102 if (stat & OMAP_I2C_STAT_AL) {1103 dev_err(omap->dev, "Arbitration lost\n");1104 err |= OMAP_I2C_STAT_AL;1105 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);1106 }1107 1108 /*1109 * ProDB0017052: Clear ARDY bit twice1110 */1111 if (stat & OMAP_I2C_STAT_ARDY)1112 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);1113 1114 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |1115 OMAP_I2C_STAT_AL)) {1116 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |1117 OMAP_I2C_STAT_RDR |1118 OMAP_I2C_STAT_XRDY |1119 OMAP_I2C_STAT_XDR |1120 OMAP_I2C_STAT_ARDY));1121 break;1122 }1123 1124 if (stat & OMAP_I2C_STAT_RDR) {1125 u8 num_bytes = 1;1126 1127 if (omap->fifo_size)1128 num_bytes = omap->buf_len;1129 1130 if (omap->errata & I2C_OMAP_ERRATA_I207) {1131 i2c_omap_errata_i207(omap, stat);1132 num_bytes = (omap_i2c_read_reg(omap,1133 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;1134 }1135 1136 omap_i2c_receive_data(omap, num_bytes, true);1137 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);1138 continue;1139 }1140 1141 if (stat & OMAP_I2C_STAT_RRDY) {1142 u8 num_bytes = 1;1143 1144 if (omap->threshold)1145 num_bytes = omap->threshold;1146 1147 omap_i2c_receive_data(omap, num_bytes, false);1148 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);1149 continue;1150 }1151 1152 if (stat & OMAP_I2C_STAT_XDR) {1153 u8 num_bytes = 1;1154 int ret;1155 1156 if (omap->fifo_size)1157 num_bytes = omap->buf_len;1158 1159 ret = omap_i2c_transmit_data(omap, num_bytes, true);1160 if (ret < 0)1161 break;1162 1163 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);1164 continue;1165 }1166 1167 if (stat & OMAP_I2C_STAT_XRDY) {1168 u8 num_bytes = 1;1169 int ret;1170 1171 if (omap->threshold)1172 num_bytes = omap->threshold;1173 1174 ret = omap_i2c_transmit_data(omap, num_bytes, false);1175 if (ret < 0)1176 break;1177 1178 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);1179 continue;1180 }1181 1182 if (stat & OMAP_I2C_STAT_ROVR) {1183 dev_err(omap->dev, "Receive overrun\n");1184 err |= OMAP_I2C_STAT_ROVR;1185 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);1186 break;1187 }1188 1189 if (stat & OMAP_I2C_STAT_XUDF) {1190 dev_err(omap->dev, "Transmit underflow\n");1191 err |= OMAP_I2C_STAT_XUDF;1192 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);1193 break;1194 }1195 } while (stat);1196 1197 return err;1198}1199 1200static irqreturn_t1201omap_i2c_isr_thread(int this_irq, void *dev_id)1202{1203 int ret;1204 struct omap_i2c_dev *omap = dev_id;1205 1206 ret = omap_i2c_xfer_data(omap);1207 if (ret != -EAGAIN)1208 omap_i2c_complete_cmd(omap, ret);1209 1210 return IRQ_HANDLED;1211}1212 1213static const struct i2c_algorithm omap_i2c_algo = {1214 .master_xfer = omap_i2c_xfer_irq,1215 .master_xfer_atomic = omap_i2c_xfer_polling,1216 .functionality = omap_i2c_func,1217};1218 1219static const struct i2c_adapter_quirks omap_i2c_quirks = {1220 .flags = I2C_AQ_NO_ZERO_LEN,1221};1222 1223#ifdef CONFIG_OF1224static struct omap_i2c_bus_platform_data omap2420_pdata = {1225 .rev = OMAP_I2C_IP_VERSION_1,1226 .flags = OMAP_I2C_FLAG_NO_FIFO |1227 OMAP_I2C_FLAG_SIMPLE_CLOCK |1228 OMAP_I2C_FLAG_16BIT_DATA_REG |1229 OMAP_I2C_FLAG_BUS_SHIFT_2,1230};1231 1232static struct omap_i2c_bus_platform_data omap2430_pdata = {1233 .rev = OMAP_I2C_IP_VERSION_1,1234 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |1235 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,1236};1237 1238static struct omap_i2c_bus_platform_data omap3_pdata = {1239 .rev = OMAP_I2C_IP_VERSION_1,1240 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,1241};1242 1243static struct omap_i2c_bus_platform_data omap4_pdata = {1244 .rev = OMAP_I2C_IP_VERSION_2,1245};1246 1247static const struct of_device_id omap_i2c_of_match[] = {1248 {1249 .compatible = "ti,omap4-i2c",1250 .data = &omap4_pdata,1251 },1252 {1253 .compatible = "ti,omap3-i2c",1254 .data = &omap3_pdata,1255 },1256 {1257 .compatible = "ti,omap2430-i2c",1258 .data = &omap2430_pdata,1259 },1260 {1261 .compatible = "ti,omap2420-i2c",1262 .data = &omap2420_pdata,1263 },1264 { }1265};1266MODULE_DEVICE_TABLE(of, omap_i2c_of_match);1267#endif1268 1269#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)1270 1271#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)1272#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)1273 1274#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)1275#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)1276#define OMAP_I2C_SCHEME_0 01277#define OMAP_I2C_SCHEME_1 11278 1279static int omap_i2c_get_scl(struct i2c_adapter *adap)1280{1281 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);1282 u32 reg;1283 1284 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);1285 1286 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;1287}1288 1289static int omap_i2c_get_sda(struct i2c_adapter *adap)1290{1291 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);1292 u32 reg;1293 1294 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);1295 1296 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;1297}1298 1299static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)1300{1301 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);1302 u32 reg;1303 1304 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);1305 if (val)1306 reg |= OMAP_I2C_SYSTEST_SCL_O;1307 else1308 reg &= ~OMAP_I2C_SYSTEST_SCL_O;1309 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);1310}1311 1312static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)1313{1314 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);1315 u32 reg;1316 1317 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);1318 /* enable test mode */1319 reg |= OMAP_I2C_SYSTEST_ST_EN;1320 /* select SDA/SCL IO mode */1321 reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;1322 /* set SCL to high-impedance state (reset value is 0) */1323 reg |= OMAP_I2C_SYSTEST_SCL_O;1324 /* set SDA to high-impedance state (reset value is 0) */1325 reg |= OMAP_I2C_SYSTEST_SDA_O;1326 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);1327}1328 1329static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)1330{1331 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);1332 u32 reg;1333 1334 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);1335 /* restore reset values */1336 reg &= ~OMAP_I2C_SYSTEST_ST_EN;1337 reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;1338 reg &= ~OMAP_I2C_SYSTEST_SCL_O;1339 reg &= ~OMAP_I2C_SYSTEST_SDA_O;1340 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);1341}1342 1343static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {1344 .get_scl = omap_i2c_get_scl,1345 .get_sda = omap_i2c_get_sda,1346 .set_scl = omap_i2c_set_scl,1347 .prepare_recovery = omap_i2c_prepare_recovery,1348 .unprepare_recovery = omap_i2c_unprepare_recovery,1349 .recover_bus = i2c_generic_scl_recovery,1350};1351 1352static int1353omap_i2c_probe(struct platform_device *pdev)1354{1355 struct omap_i2c_dev *omap;1356 struct i2c_adapter *adap;1357 const struct omap_i2c_bus_platform_data *pdata =1358 dev_get_platdata(&pdev->dev);1359 struct device_node *node = pdev->dev.of_node;1360 int irq;1361 int r;1362 u32 rev;1363 u16 minor, major;1364 1365 irq = platform_get_irq(pdev, 0);1366 if (irq < 0)1367 return irq;1368 1369 omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);1370 if (!omap)1371 return -ENOMEM;1372 1373 omap->base = devm_platform_ioremap_resource(pdev, 0);1374 if (IS_ERR(omap->base))1375 return PTR_ERR(omap->base);1376 1377 if (pdev->dev.of_node) {1378 u32 freq = I2C_MAX_STANDARD_MODE_FREQ;1379 1380 pdata = device_get_match_data(&pdev->dev);1381 omap->flags = pdata->flags;1382 1383 of_property_read_u32(node, "clock-frequency", &freq);1384 /* convert DT freq value in Hz into kHz for speed */1385 omap->speed = freq / 1000;1386 } else if (pdata != NULL) {1387 omap->speed = pdata->clkrate;1388 omap->flags = pdata->flags;1389 omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;1390 }1391 1392 omap->dev = &pdev->dev;1393 omap->irq = irq;1394 1395 platform_set_drvdata(pdev, omap);1396 init_completion(&omap->cmd_complete);1397 1398 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;1399 1400 pm_runtime_enable(omap->dev);1401 pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);1402 pm_runtime_use_autosuspend(omap->dev);1403 1404 r = pm_runtime_resume_and_get(omap->dev);1405 if (r < 0)1406 goto err_disable_pm;1407 1408 /*1409 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.1410 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.1411 * Also since the omap_i2c_read_reg uses reg_map_ip_* a1412 * readw_relaxed is done.1413 */1414 rev = readw_relaxed(omap->base + 0x04);1415 1416 omap->scheme = OMAP_I2C_SCHEME(rev);1417 switch (omap->scheme) {1418 case OMAP_I2C_SCHEME_0:1419 omap->regs = (u8 *)reg_map_ip_v1;1420 omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);1421 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);1422 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);1423 break;1424 case OMAP_I2C_SCHEME_1:1425 default:1426 omap->regs = (u8 *)reg_map_ip_v2;1427 rev = (rev << 16) |1428 omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);1429 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);1430 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);1431 omap->rev = rev;1432 }1433 1434 omap->errata = 0;1435 1436 if (omap->rev >= OMAP_I2C_REV_ON_2430 &&1437 omap->rev < OMAP_I2C_REV_ON_4430_PLUS)1438 omap->errata |= I2C_OMAP_ERRATA_I207;1439 1440 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)1441 omap->errata |= I2C_OMAP_ERRATA_I462;1442 1443 if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {1444 u16 s;1445 1446 /* Set up the fifo size - Get total size */1447 s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;1448 omap->fifo_size = 0x8 << s;1449 1450 /*1451 * Set up notification threshold as half the total available1452 * size. This is to ensure that we can handle the status on int1453 * call back latencies.1454 */1455 1456 omap->fifo_size = (omap->fifo_size / 2);1457 1458 if (omap->rev < OMAP_I2C_REV_ON_3630)1459 omap->b_hw = 1; /* Enable hardware fixes */1460 1461 /* calculate wakeup latency constraint for MPU */1462 if (omap->set_mpu_wkup_lat != NULL)1463 omap->latency = (1000000 * omap->fifo_size) /1464 (1000 * omap->speed / 8);1465 }1466 1467 /* reset ASAP, clearing any IRQs */1468 omap_i2c_init(omap);1469 1470 if (omap->rev < OMAP_I2C_OMAP1_REV_2)1471 r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,1472 IRQF_NO_SUSPEND, pdev->name, omap);1473 else1474 r = devm_request_threaded_irq(&pdev->dev, omap->irq,1475 omap_i2c_isr, omap_i2c_isr_thread,1476 IRQF_NO_SUSPEND | IRQF_ONESHOT,1477 pdev->name, omap);1478 1479 if (r) {1480 dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);1481 goto err_unuse_clocks;1482 }1483 1484 adap = &omap->adapter;1485 i2c_set_adapdata(adap, omap);1486 adap->owner = THIS_MODULE;1487 adap->class = I2C_CLASS_DEPRECATED;1488 strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));1489 adap->algo = &omap_i2c_algo;1490 adap->quirks = &omap_i2c_quirks;1491 adap->dev.parent = &pdev->dev;1492 adap->dev.of_node = pdev->dev.of_node;1493 adap->bus_recovery_info = &omap_i2c_bus_recovery_info;1494 1495 /* i2c device drivers may be active on return from add_adapter() */1496 adap->nr = pdev->id;1497 r = i2c_add_numbered_adapter(adap);1498 if (r)1499 goto err_unuse_clocks;1500 1501 dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,1502 major, minor, omap->speed);1503 1504 pm_runtime_mark_last_busy(omap->dev);1505 pm_runtime_put_autosuspend(omap->dev);1506 1507 return 0;1508 1509err_unuse_clocks:1510 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);1511 pm_runtime_dont_use_autosuspend(omap->dev);1512 pm_runtime_put_sync(omap->dev);1513err_disable_pm:1514 pm_runtime_disable(&pdev->dev);1515 1516 return r;1517}1518 1519static void omap_i2c_remove(struct platform_device *pdev)1520{1521 struct omap_i2c_dev *omap = platform_get_drvdata(pdev);1522 int ret;1523 1524 i2c_del_adapter(&omap->adapter);1525 1526 ret = pm_runtime_get_sync(&pdev->dev);1527 if (ret < 0)1528 dev_err(omap->dev, "Failed to resume hardware, skip disable\n");1529 else1530 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);1531 1532 pm_runtime_dont_use_autosuspend(&pdev->dev);1533 pm_runtime_put_sync(&pdev->dev);1534 pm_runtime_disable(&pdev->dev);1535}1536 1537static int omap_i2c_runtime_suspend(struct device *dev)1538{1539 struct omap_i2c_dev *omap = dev_get_drvdata(dev);1540 1541 omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);1542 1543 if (omap->scheme == OMAP_I2C_SCHEME_0)1544 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);1545 else1546 omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,1547 OMAP_I2C_IP_V2_INTERRUPTS_MASK);1548 1549 if (omap->rev < OMAP_I2C_OMAP1_REV_2) {1550 omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */1551 } else {1552 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);1553 1554 /* Flush posted write */1555 omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);1556 }1557 1558 pinctrl_pm_select_sleep_state(dev);1559 1560 return 0;1561}1562 1563static int omap_i2c_runtime_resume(struct device *dev)1564{1565 struct omap_i2c_dev *omap = dev_get_drvdata(dev);1566 1567 pinctrl_pm_select_default_state(dev);1568 1569 if (!omap->regs)1570 return 0;1571 1572 __omap_i2c_init(omap);1573 1574 return 0;1575}1576 1577static int omap_i2c_suspend(struct device *dev)1578{1579 /*1580 * If the controller is autosuspended, there is no way to wakeup it once1581 * runtime pm is disabled (in suspend_late()).1582 * But a device may need the controller up during suspend_noirq() or1583 * resume_noirq().1584 * Wakeup the controller while runtime pm is enabled, so it is available1585 * until its suspend_noirq(), and from resume_noirq().1586 */1587 return pm_runtime_resume_and_get(dev);1588}1589 1590static int omap_i2c_resume(struct device *dev)1591{1592 pm_runtime_mark_last_busy(dev);1593 pm_runtime_put_autosuspend(dev);1594 1595 return 0;1596}1597 1598static const struct dev_pm_ops omap_i2c_pm_ops = {1599 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,1600 pm_runtime_force_resume)1601 SYSTEM_SLEEP_PM_OPS(omap_i2c_suspend, omap_i2c_resume)1602 RUNTIME_PM_OPS(omap_i2c_runtime_suspend,1603 omap_i2c_runtime_resume, NULL)1604};1605 1606static struct platform_driver omap_i2c_driver = {1607 .probe = omap_i2c_probe,1608 .remove_new = omap_i2c_remove,1609 .driver = {1610 .name = "omap_i2c",1611 .pm = pm_ptr(&omap_i2c_pm_ops),1612 .of_match_table = of_match_ptr(omap_i2c_of_match),1613 },1614};1615 1616/* I2C may be needed to bring up other drivers */1617static int __init1618omap_i2c_init_driver(void)1619{1620 return platform_driver_register(&omap_i2c_driver);1621}1622subsys_initcall(omap_i2c_init_driver);1623 1624static void __exit omap_i2c_exit_driver(void)1625{1626 platform_driver_unregister(&omap_i2c_driver);1627}1628module_exit(omap_i2c_exit_driver);1629 1630MODULE_AUTHOR("MontaVista Software, Inc. (and others)");1631MODULE_DESCRIPTION("TI OMAP I2C bus adapter");1632MODULE_LICENSE("GPL");1633MODULE_ALIAS("platform:omap_i2c");1634