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1// SPDX-License-Identifier: GPL-2.02/*3 * Renesas RIIC driver4 *5 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>6 * Copyright (C) 2013 Renesas Solutions Corp.7 */8 9/*10 * This i2c core has a lot of interrupts, namely 8. We use their chaining as11 * some kind of state machine.12 *13 * 1) The main xfer routine kicks off a transmission by putting the start bit14 * (or repeated start) on the bus and enabling the transmit interrupt (TIE)15 * since we need to send the target address + RW bit in every case.16 *17 * 2) TIE sends target address + RW bit and selects how to continue.18 *19 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we20 * are done, we switch over to the transmission done interrupt (TEIE) and mark21 * the message as completed (includes sending STOP) there.22 *23 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is24 * needed to start clocking, then we keep receiving until we are done. Note25 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by26 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a27 * message to create the final NACK as sketched in the datasheet. This caused28 * some subtle races (when byte n was processed and byte n+1 was already29 * waiting), though, and I started with the safe approach.30 *31 * 4) If we got a NACK somewhere, we flag the error and stop the transmission32 * via NAKIE.33 *34 * Also check the comments in the interrupt routines for some gory details.35 */36 37#include <linux/clk.h>38#include <linux/completion.h>39#include <linux/err.h>40#include <linux/i2c.h>41#include <linux/interrupt.h>42#include <linux/io.h>43#include <linux/module.h>44#include <linux/of.h>45#include <linux/platform_device.h>46#include <linux/pm_runtime.h>47#include <linux/reset.h>48 49#define ICCR1_ICE 0x8050#define ICCR1_IICRST 0x4051#define ICCR1_SOWP 0x1052 53#define ICCR2_BBSY 0x8054#define ICCR2_SP 0x0855#define ICCR2_RS 0x0456#define ICCR2_ST 0x0257 58#define ICMR1_CKS_MASK 0x7059#define ICMR1_BCWP 0x0860#define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)61 62#define ICMR3_RDRFS 0x2063#define ICMR3_ACKWP 0x1064#define ICMR3_ACKBT 0x0865 66#define ICFER_FMPE 0x8067 68#define ICIER_TIE 0x8069#define ICIER_TEIE 0x4070#define ICIER_RIE 0x2071#define ICIER_NAKIE 0x1072#define ICIER_SPIE 0x0873 74#define ICSR2_NACKF 0x1075 76#define ICBR_RESERVED 0xe0 /* Should be 1 on writes */77 78#define RIIC_INIT_MSG -179 80enum riic_reg_list {81 RIIC_ICCR1 = 0,82 RIIC_ICCR2,83 RIIC_ICMR1,84 RIIC_ICMR3,85 RIIC_ICFER,86 RIIC_ICSER,87 RIIC_ICIER,88 RIIC_ICSR2,89 RIIC_ICBRL,90 RIIC_ICBRH,91 RIIC_ICDRT,92 RIIC_ICDRR,93 RIIC_REG_END,94};95 96struct riic_of_data {97 const u8 *regs;98 bool fast_mode_plus;99};100 101struct riic_dev {102 void __iomem *base;103 u8 *buf;104 struct i2c_msg *msg;105 int bytes_left;106 int err;107 int is_last;108 const struct riic_of_data *info;109 struct completion msg_done;110 struct i2c_adapter adapter;111 struct clk *clk;112 struct reset_control *rstc;113 struct i2c_timings i2c_t;114};115 116struct riic_irq_desc {117 int res_num;118 irq_handler_t isr;119 char *name;120};121 122static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset)123{124 writeb(val, riic->base + riic->info->regs[offset]);125}126 127static inline u8 riic_readb(struct riic_dev *riic, u8 offset)128{129 return readb(riic->base + riic->info->regs[offset]);130}131 132static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)133{134 riic_writeb(riic, (riic_readb(riic, reg) & ~clear) | set, reg);135}136 137static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)138{139 struct riic_dev *riic = i2c_get_adapdata(adap);140 struct device *dev = adap->dev.parent;141 unsigned long time_left;142 int i, ret;143 u8 start_bit;144 145 ret = pm_runtime_resume_and_get(dev);146 if (ret)147 return ret;148 149 if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) {150 riic->err = -EBUSY;151 goto out;152 }153 154 reinit_completion(&riic->msg_done);155 riic->err = 0;156 157 riic_writeb(riic, 0, RIIC_ICSR2);158 159 for (i = 0, start_bit = ICCR2_ST; i < num; i++) {160 riic->bytes_left = RIIC_INIT_MSG;161 riic->buf = msgs[i].buf;162 riic->msg = &msgs[i];163 riic->is_last = (i == num - 1);164 165 riic_writeb(riic, ICIER_NAKIE | ICIER_TIE, RIIC_ICIER);166 167 riic_writeb(riic, start_bit, RIIC_ICCR2);168 169 time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);170 if (time_left == 0)171 riic->err = -ETIMEDOUT;172 173 if (riic->err)174 break;175 176 start_bit = ICCR2_RS;177 }178 179 out:180 pm_runtime_mark_last_busy(dev);181 pm_runtime_put_autosuspend(dev);182 183 return riic->err ?: num;184}185 186static irqreturn_t riic_tdre_isr(int irq, void *data)187{188 struct riic_dev *riic = data;189 u8 val;190 191 if (!riic->bytes_left)192 return IRQ_NONE;193 194 if (riic->bytes_left == RIIC_INIT_MSG) {195 if (riic->msg->flags & I2C_M_RD)196 /* On read, switch over to receive interrupt */197 riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);198 else199 /* On write, initialize length */200 riic->bytes_left = riic->msg->len;201 202 val = i2c_8bit_addr_from_msg(riic->msg);203 } else {204 val = *riic->buf;205 riic->buf++;206 riic->bytes_left--;207 }208 209 /*210 * Switch to transmission ended interrupt when done. Do check here211 * after bytes_left was initialized to support SMBUS_QUICK (new msg has212 * 0 length then)213 */214 if (riic->bytes_left == 0)215 riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);216 217 /*218 * This acks the TIE interrupt. We get another TIE immediately if our219 * value could be moved to the shadow shift register right away. So220 * this must be after updates to ICIER (where we want to disable TIE)!221 */222 riic_writeb(riic, val, RIIC_ICDRT);223 224 return IRQ_HANDLED;225}226 227static irqreturn_t riic_tend_isr(int irq, void *data)228{229 struct riic_dev *riic = data;230 231 if (riic_readb(riic, RIIC_ICSR2) & ICSR2_NACKF) {232 /* We got a NACKIE */233 riic_readb(riic, RIIC_ICDRR); /* dummy read */234 riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);235 riic->err = -ENXIO;236 } else if (riic->bytes_left) {237 return IRQ_NONE;238 }239 240 if (riic->is_last || riic->err) {241 riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);242 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2);243 } else {244 /* Transfer is complete, but do not send STOP */245 riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);246 complete(&riic->msg_done);247 }248 249 return IRQ_HANDLED;250}251 252static irqreturn_t riic_rdrf_isr(int irq, void *data)253{254 struct riic_dev *riic = data;255 256 if (!riic->bytes_left)257 return IRQ_NONE;258 259 if (riic->bytes_left == RIIC_INIT_MSG) {260 riic->bytes_left = riic->msg->len;261 riic_readb(riic, RIIC_ICDRR); /* dummy read */262 return IRQ_HANDLED;263 }264 265 if (riic->bytes_left == 1) {266 /* STOP must come before we set ACKBT! */267 if (riic->is_last) {268 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);269 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2);270 }271 272 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);273 274 } else {275 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);276 }277 278 /* Reading acks the RIE interrupt */279 *riic->buf = riic_readb(riic, RIIC_ICDRR);280 riic->buf++;281 riic->bytes_left--;282 283 return IRQ_HANDLED;284}285 286static irqreturn_t riic_stop_isr(int irq, void *data)287{288 struct riic_dev *riic = data;289 290 /* read back registers to confirm writes have fully propagated */291 riic_writeb(riic, 0, RIIC_ICSR2);292 riic_readb(riic, RIIC_ICSR2);293 riic_writeb(riic, 0, RIIC_ICIER);294 riic_readb(riic, RIIC_ICIER);295 296 complete(&riic->msg_done);297 298 return IRQ_HANDLED;299}300 301static u32 riic_func(struct i2c_adapter *adap)302{303 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;304}305 306static const struct i2c_algorithm riic_algo = {307 .xfer = riic_xfer,308 .functionality = riic_func,309};310 311static int riic_init_hw(struct riic_dev *riic)312{313 int ret;314 unsigned long rate;315 int total_ticks, cks, brl, brh;316 struct i2c_timings *t = &riic->i2c_t;317 struct device *dev = riic->adapter.dev.parent;318 bool fast_mode_plus = riic->info->fast_mode_plus;319 u32 max_freq = fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ320 : I2C_MAX_FAST_MODE_FREQ;321 322 if (t->bus_freq_hz > max_freq)323 return dev_err_probe(&riic->adapter.dev, -EINVAL,324 "unsupported bus speed %uHz (%u max)\n",325 t->bus_freq_hz, max_freq);326 327 rate = clk_get_rate(riic->clk);328 329 /*330 * Assume the default register settings:331 * FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)332 * FER.NFE = 1 (noise circuit enabled)333 * MR3.NF = 0 (1 cycle of noise filtered out)334 *335 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)336 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)337 */338 339 /*340 * Determine reference clock rate. We must be able to get the desired341 * frequency with only 62 clock ticks max (31 high, 31 low).342 * Aim for a duty of 60% LOW, 40% HIGH.343 */344 total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz ?: 1);345 346 for (cks = 0; cks < 7; cks++) {347 /*348 * 60% low time must be less than BRL + 2 + 1349 * BRL max register value is 0x1F.350 */351 brl = ((total_ticks * 6) / 10);352 if (brl <= (0x1F + 3))353 break;354 355 total_ticks /= 2;356 rate /= 2;357 }358 359 if (brl > (0x1F + 3)) {360 dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",361 (unsigned long)t->bus_freq_hz);362 return -EINVAL;363 }364 365 brh = total_ticks - brl;366 367 /* Remove automatic clock ticks for sync circuit and NF */368 if (cks == 0) {369 brl -= 4;370 brh -= 4;371 } else {372 brl -= 3;373 brh -= 3;374 }375 376 /*377 * Remove clock ticks for rise and fall times. Convert ns to clock378 * ticks.379 */380 brl -= t->scl_fall_ns / (1000000000 / rate);381 brh -= t->scl_rise_ns / (1000000000 / rate);382 383 /* Adjust for min register values for when SCLE=1 and NFE=1 */384 if (brl < 1)385 brl = 1;386 if (brh < 1)387 brh = 1;388 389 pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",390 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),391 t->scl_fall_ns / (1000000000 / rate),392 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);393 394 ret = pm_runtime_resume_and_get(dev);395 if (ret)396 return ret;397 398 /* Changing the order of accessing IICRST and ICE may break things! */399 riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1);400 riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);401 402 riic_writeb(riic, ICMR1_CKS(cks), RIIC_ICMR1);403 riic_writeb(riic, brh | ICBR_RESERVED, RIIC_ICBRH);404 riic_writeb(riic, brl | ICBR_RESERVED, RIIC_ICBRL);405 406 riic_writeb(riic, 0, RIIC_ICSER);407 riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3);408 409 if (fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)410 riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER);411 412 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);413 414 pm_runtime_mark_last_busy(dev);415 pm_runtime_put_autosuspend(dev);416 return 0;417}418 419static struct riic_irq_desc riic_irqs[] = {420 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },421 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },422 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },423 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },424 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },425};426 427static void riic_reset_control_assert(void *data)428{429 reset_control_assert(data);430}431 432static int riic_i2c_probe(struct platform_device *pdev)433{434 struct device *dev = &pdev->dev;435 struct riic_dev *riic;436 struct i2c_adapter *adap;437 int i, ret;438 439 riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL);440 if (!riic)441 return -ENOMEM;442 443 riic->base = devm_platform_ioremap_resource(pdev, 0);444 if (IS_ERR(riic->base))445 return PTR_ERR(riic->base);446 447 riic->clk = devm_clk_get(dev, NULL);448 if (IS_ERR(riic->clk)) {449 dev_err(dev, "missing controller clock");450 return PTR_ERR(riic->clk);451 }452 453 riic->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);454 if (IS_ERR(riic->rstc))455 return dev_err_probe(dev, PTR_ERR(riic->rstc),456 "Error: missing reset ctrl\n");457 458 ret = reset_control_deassert(riic->rstc);459 if (ret)460 return ret;461 462 ret = devm_add_action_or_reset(dev, riic_reset_control_assert, riic->rstc);463 if (ret)464 return ret;465 466 for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {467 ret = platform_get_irq(pdev, riic_irqs[i].res_num);468 if (ret < 0)469 return ret;470 471 ret = devm_request_irq(dev, ret, riic_irqs[i].isr,472 0, riic_irqs[i].name, riic);473 if (ret) {474 dev_err(dev, "failed to request irq %s\n", riic_irqs[i].name);475 return ret;476 }477 }478 479 riic->info = of_device_get_match_data(dev);480 481 adap = &riic->adapter;482 i2c_set_adapdata(adap, riic);483 strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));484 adap->owner = THIS_MODULE;485 adap->algo = &riic_algo;486 adap->dev.parent = dev;487 adap->dev.of_node = dev->of_node;488 489 init_completion(&riic->msg_done);490 491 i2c_parse_fw_timings(dev, &riic->i2c_t, true);492 493 /* Default 0 to save power. Can be overridden via sysfs for lower latency. */494 pm_runtime_set_autosuspend_delay(dev, 0);495 pm_runtime_use_autosuspend(dev);496 pm_runtime_enable(dev);497 498 ret = riic_init_hw(riic);499 if (ret)500 goto out;501 502 ret = i2c_add_adapter(adap);503 if (ret)504 goto out;505 506 platform_set_drvdata(pdev, riic);507 508 dev_info(dev, "registered with %dHz bus speed\n", riic->i2c_t.bus_freq_hz);509 return 0;510 511out:512 pm_runtime_disable(dev);513 pm_runtime_dont_use_autosuspend(dev);514 return ret;515}516 517static void riic_i2c_remove(struct platform_device *pdev)518{519 struct riic_dev *riic = platform_get_drvdata(pdev);520 struct device *dev = &pdev->dev;521 int ret;522 523 ret = pm_runtime_resume_and_get(dev);524 if (!ret) {525 riic_writeb(riic, 0, RIIC_ICIER);526 pm_runtime_put(dev);527 }528 i2c_del_adapter(&riic->adapter);529 pm_runtime_disable(dev);530 pm_runtime_dont_use_autosuspend(dev);531}532 533static const u8 riic_rz_a_regs[RIIC_REG_END] = {534 [RIIC_ICCR1] = 0x00,535 [RIIC_ICCR2] = 0x04,536 [RIIC_ICMR1] = 0x08,537 [RIIC_ICMR3] = 0x10,538 [RIIC_ICFER] = 0x14,539 [RIIC_ICSER] = 0x18,540 [RIIC_ICIER] = 0x1c,541 [RIIC_ICSR2] = 0x24,542 [RIIC_ICBRL] = 0x34,543 [RIIC_ICBRH] = 0x38,544 [RIIC_ICDRT] = 0x3c,545 [RIIC_ICDRR] = 0x40,546};547 548static const struct riic_of_data riic_rz_a_info = {549 .regs = riic_rz_a_regs,550 .fast_mode_plus = true,551};552 553static const struct riic_of_data riic_rz_a1h_info = {554 .regs = riic_rz_a_regs,555};556 557static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {558 [RIIC_ICCR1] = 0x00,559 [RIIC_ICCR2] = 0x01,560 [RIIC_ICMR1] = 0x02,561 [RIIC_ICMR3] = 0x04,562 [RIIC_ICFER] = 0x05,563 [RIIC_ICSER] = 0x06,564 [RIIC_ICIER] = 0x07,565 [RIIC_ICSR2] = 0x09,566 [RIIC_ICBRL] = 0x10,567 [RIIC_ICBRH] = 0x11,568 [RIIC_ICDRT] = 0x12,569 [RIIC_ICDRR] = 0x13,570};571 572static const struct riic_of_data riic_rz_v2h_info = {573 .regs = riic_rz_v2h_regs,574 .fast_mode_plus = true,575};576 577static int riic_i2c_suspend(struct device *dev)578{579 struct riic_dev *riic = dev_get_drvdata(dev);580 int ret;581 582 ret = pm_runtime_resume_and_get(dev);583 if (ret)584 return ret;585 586 i2c_mark_adapter_suspended(&riic->adapter);587 588 /* Disable output on SDA, SCL pins. */589 riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1);590 591 pm_runtime_mark_last_busy(dev);592 pm_runtime_put_sync(dev);593 594 return reset_control_assert(riic->rstc);595}596 597static int riic_i2c_resume(struct device *dev)598{599 struct riic_dev *riic = dev_get_drvdata(dev);600 int ret;601 602 ret = reset_control_deassert(riic->rstc);603 if (ret)604 return ret;605 606 ret = riic_init_hw(riic);607 if (ret) {608 /*609 * In case this happens there is no way to recover from this610 * state. The driver will remain loaded. We want to avoid611 * keeping the reset line de-asserted for no reason.612 */613 reset_control_assert(riic->rstc);614 return ret;615 }616 617 i2c_mark_adapter_resumed(&riic->adapter);618 619 return 0;620}621 622static const struct dev_pm_ops riic_i2c_pm_ops = {623 SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume)624};625 626static const struct of_device_id riic_i2c_dt_ids[] = {627 { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },628 { .compatible = "renesas,riic-r7s72100", .data = &riic_rz_a1h_info, },629 { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },630 { /* Sentinel */ },631};632 633static struct platform_driver riic_i2c_driver = {634 .probe = riic_i2c_probe,635 .remove_new = riic_i2c_remove,636 .driver = {637 .name = "i2c-riic",638 .of_match_table = riic_i2c_dt_ids,639 .pm = pm_ptr(&riic_i2c_pm_ops),640 },641};642 643module_platform_driver(riic_i2c_driver);644 645MODULE_DESCRIPTION("Renesas RIIC adapter");646MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");647MODULE_LICENSE("GPL v2");648MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);649