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1// SPDX-License-Identifier: GPL-2.0-or-later2/* linux/drivers/i2c/busses/i2c-s3c2410.c3 *4 * Copyright (C) 2004,2005,2009 Simtec Electronics5 * Ben Dooks <ben@simtec.co.uk>6 *7 * S3C2410 I2C Controller8*/9 10#include <linux/kernel.h>11#include <linux/module.h>12 13#include <linux/i2c.h>14#include <linux/init.h>15#include <linux/time.h>16#include <linux/interrupt.h>17#include <linux/delay.h>18#include <linux/errno.h>19#include <linux/err.h>20#include <linux/platform_device.h>21#include <linux/pm_runtime.h>22#include <linux/clk.h>23#include <linux/cpufreq.h>24#include <linux/slab.h>25#include <linux/io.h>26#include <linux/of.h>27#include <linux/gpio/consumer.h>28#include <linux/pinctrl/consumer.h>29#include <linux/mfd/syscon.h>30#include <linux/regmap.h>31 32#include <asm/irq.h>33 34#include <linux/platform_data/i2c-s3c2410.h>35 36/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */37 38#define S3C2410_IICCON 0x0039#define S3C2410_IICSTAT 0x0440#define S3C2410_IICADD 0x0841#define S3C2410_IICDS 0x0C42#define S3C2440_IICLC 0x1043 44#define S3C2410_IICCON_ACKEN (1 << 7)45#define S3C2410_IICCON_TXDIV_16 (0 << 6)46#define S3C2410_IICCON_TXDIV_512 (1 << 6)47#define S3C2410_IICCON_IRQEN (1 << 5)48#define S3C2410_IICCON_IRQPEND (1 << 4)49#define S3C2410_IICCON_SCALE(x) ((x) & 0xf)50#define S3C2410_IICCON_SCALEMASK (0xf)51 52#define S3C2410_IICSTAT_MASTER_RX (2 << 6)53#define S3C2410_IICSTAT_MASTER_TX (3 << 6)54#define S3C2410_IICSTAT_SLAVE_RX (0 << 6)55#define S3C2410_IICSTAT_SLAVE_TX (1 << 6)56#define S3C2410_IICSTAT_MODEMASK (3 << 6)57 58#define S3C2410_IICSTAT_START (1 << 5)59#define S3C2410_IICSTAT_BUSBUSY (1 << 5)60#define S3C2410_IICSTAT_TXRXEN (1 << 4)61#define S3C2410_IICSTAT_ARBITR (1 << 3)62#define S3C2410_IICSTAT_ASSLAVE (1 << 2)63#define S3C2410_IICSTAT_ADDR0 (1 << 1)64#define S3C2410_IICSTAT_LASTBIT (1 << 0)65 66#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)67#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)68#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)69#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)70#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)71 72#define S3C2410_IICLC_FILTER_ON (1 << 2)73 74/* Treat S3C2410 as baseline hardware, anything else is supported via quirks */75#define QUIRK_S3C2440 (1 << 0)76#define QUIRK_HDMIPHY (1 << 1)77#define QUIRK_NO_GPIO (1 << 2)78#define QUIRK_POLL (1 << 3)79#define QUIRK_ATOMIC (1 << 4)80 81/* Max time to wait for bus to become idle after a xfer (in us) */82#define S3C2410_IDLE_TIMEOUT 500083 84/* Exynos5 Sysreg offset */85#define EXYNOS5_SYS_I2C_CFG 0x023486 87/* i2c controller state */88enum s3c24xx_i2c_state {89 STATE_IDLE,90 STATE_START,91 STATE_READ,92 STATE_WRITE,93 STATE_STOP94};95 96struct s3c24xx_i2c {97 wait_queue_head_t wait;98 kernel_ulong_t quirks;99 100 struct i2c_msg *msg;101 unsigned int msg_num;102 unsigned int msg_idx;103 unsigned int msg_ptr;104 105 unsigned int tx_setup;106 unsigned int irq;107 108 enum s3c24xx_i2c_state state;109 unsigned long clkrate;110 111 void __iomem *regs;112 struct clk *clk;113 struct device *dev;114 struct i2c_adapter adap;115 116 struct s3c2410_platform_i2c *pdata;117 struct gpio_desc *gpios[2];118 struct pinctrl *pctrl;119 struct regmap *sysreg;120 unsigned int sys_i2c_cfg;121};122 123static const struct platform_device_id s3c24xx_driver_ids[] = {124 {125 .name = "s3c2410-i2c",126 .driver_data = 0,127 }, {128 .name = "s3c2440-i2c",129 .driver_data = QUIRK_S3C2440,130 }, {131 .name = "s3c2440-hdmiphy-i2c",132 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,133 }, { }134};135MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);136 137static void i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);138 139#ifdef CONFIG_OF140static const struct of_device_id s3c24xx_i2c_match[] = {141 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },142 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },143 { .compatible = "samsung,s3c2440-hdmiphy-i2c",144 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },145 { .compatible = "samsung,exynos5-sata-phy-i2c",146 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },147 {},148};149MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);150#endif151 152/*153 * Get controller type either from device tree or platform device variant.154 */155static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)156{157 if (pdev->dev.of_node)158 return (kernel_ulong_t)of_device_get_match_data(&pdev->dev);159 160 return platform_get_device_id(pdev)->driver_data;161}162 163/*164 * Complete the message and wake up the caller, using the given return code,165 * or zero to mean ok.166 */167static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)168{169 dev_dbg(i2c->dev, "master_complete %d\n", ret);170 171 i2c->msg_ptr = 0;172 i2c->msg = NULL;173 i2c->msg_idx++;174 i2c->msg_num = 0;175 if (ret)176 i2c->msg_idx = ret;177 178 if (!(i2c->quirks & (QUIRK_POLL | QUIRK_ATOMIC)))179 wake_up(&i2c->wait);180}181 182static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)183{184 unsigned long tmp;185 186 tmp = readl(i2c->regs + S3C2410_IICCON);187 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);188}189 190static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)191{192 unsigned long tmp;193 194 tmp = readl(i2c->regs + S3C2410_IICCON);195 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);196}197 198/* irq enable/disable functions */199static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)200{201 unsigned long tmp;202 203 tmp = readl(i2c->regs + S3C2410_IICCON);204 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);205}206 207static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)208{209 unsigned long tmp;210 211 tmp = readl(i2c->regs + S3C2410_IICCON);212 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);213}214 215static bool is_ack(struct s3c24xx_i2c *i2c)216{217 int tries;218 219 for (tries = 50; tries; --tries) {220 unsigned long tmp = readl(i2c->regs + S3C2410_IICCON);221 222 if (!(tmp & S3C2410_IICCON_ACKEN)) {223 /*224 * Wait a bit for the bus to stabilize,225 * delay estimated experimentally.226 */227 usleep_range(100, 200);228 return true;229 }230 if (tmp & S3C2410_IICCON_IRQPEND) {231 if (!(readl(i2c->regs + S3C2410_IICSTAT)232 & S3C2410_IICSTAT_LASTBIT))233 return true;234 }235 usleep_range(1000, 2000);236 }237 dev_err(i2c->dev, "ack was not received\n");238 return false;239}240 241/*242 * put the start of a message onto the bus243 */244static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,245 struct i2c_msg *msg)246{247 unsigned int addr = (msg->addr & 0x7f) << 1;248 unsigned long stat;249 unsigned long iiccon;250 251 stat = 0;252 stat |= S3C2410_IICSTAT_TXRXEN;253 254 if (msg->flags & I2C_M_RD) {255 stat |= S3C2410_IICSTAT_MASTER_RX;256 addr |= 1;257 } else258 stat |= S3C2410_IICSTAT_MASTER_TX;259 260 if (msg->flags & I2C_M_REV_DIR_ADDR)261 addr ^= 1;262 263 /* todo - check for whether ack wanted or not */264 s3c24xx_i2c_enable_ack(i2c);265 266 iiccon = readl(i2c->regs + S3C2410_IICCON);267 writel(stat, i2c->regs + S3C2410_IICSTAT);268 269 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);270 writeb(addr, i2c->regs + S3C2410_IICDS);271 272 /*273 * delay here to ensure the data byte has gotten onto the bus274 * before the transaction is started275 */276 ndelay(i2c->tx_setup);277 278 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);279 writel(iiccon, i2c->regs + S3C2410_IICCON);280 281 stat |= S3C2410_IICSTAT_START;282 writel(stat, i2c->regs + S3C2410_IICSTAT);283}284 285static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)286{287 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);288 289 dev_dbg(i2c->dev, "STOP\n");290 291 /*292 * The datasheet says that the STOP sequence should be:293 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')294 * 2) I2CCON.4 = 0 - Clear IRQPEND295 * 3) Wait until the stop condition takes effect.296 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN297 *298 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.299 *300 * However, after much experimentation, it appears that:301 * a) normal buses automatically clear BUSY and transition from302 * Master->Slave when they complete generating a STOP condition.303 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4304 * after starting the STOP generation here.305 * b) HDMIPHY bus does neither, so there is no way to do step 3.306 * There is no indication when this bus has finished generating307 * STOP.308 *309 * In fact, we have found that as soon as the IRQPEND bit is cleared in310 * step 2, the HDMIPHY bus generates the STOP condition, and then311 * immediately starts transferring another data byte, even though the312 * bus is supposedly stopped. This is presumably because the bus is313 * still in "Master" mode, and its BUSY bit is still set.314 *315 * To avoid these extra post-STOP transactions on HDMI phy devices, we316 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,317 * instead of first generating a proper STOP condition. This should318 * float SDA & SCK terminating the transfer. Subsequent transfers319 * start with a proper START condition, and proceed normally.320 *321 * The HDMIPHY bus is an internal bus that always has exactly two322 * devices, the host as Master and the HDMIPHY device as the slave.323 * Skipping the STOP condition has been tested on this bus and works.324 */325 if (i2c->quirks & QUIRK_HDMIPHY) {326 /* Stop driving the I2C pins */327 iicstat &= ~S3C2410_IICSTAT_TXRXEN;328 } else {329 /* stop the transfer */330 iicstat &= ~S3C2410_IICSTAT_START;331 }332 writel(iicstat, i2c->regs + S3C2410_IICSTAT);333 334 i2c->state = STATE_STOP;335 336 s3c24xx_i2c_master_complete(i2c, ret);337 s3c24xx_i2c_disable_irq(i2c);338}339 340/*341 * helper functions to determine the current state in the set of342 * messages we are sending343 */344 345/*346 * returns TRUE if the current message is the last in the set347 */348static inline int is_lastmsg(struct s3c24xx_i2c *i2c)349{350 return i2c->msg_idx >= (i2c->msg_num - 1);351}352 353/*354 * returns TRUE if we this is the last byte in the current message355 */356static inline int is_msglast(struct s3c24xx_i2c *i2c)357{358 /*359 * msg->len is always 1 for the first byte of smbus block read.360 * Actual length will be read from slave. More bytes will be361 * read according to the length then.362 */363 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)364 return 0;365 366 return i2c->msg_ptr == i2c->msg->len-1;367}368 369/*370 * returns TRUE if we reached the end of the current message371 */372static inline int is_msgend(struct s3c24xx_i2c *i2c)373{374 return i2c->msg_ptr >= i2c->msg->len;375}376 377/*378 * process an interrupt and work out what to do379 */380static void i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)381{382 unsigned long tmp;383 unsigned char byte;384 385 switch (i2c->state) {386 387 case STATE_IDLE:388 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);389 goto out;390 391 case STATE_STOP:392 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);393 s3c24xx_i2c_disable_irq(i2c);394 goto out_ack;395 396 case STATE_START:397 /*398 * last thing we did was send a start condition on the399 * bus, or started a new i2c message400 */401 if (iicstat & S3C2410_IICSTAT_LASTBIT &&402 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {403 /* ack was not received... */404 dev_dbg(i2c->dev, "ack was not received\n");405 s3c24xx_i2c_stop(i2c, -ENXIO);406 goto out_ack;407 }408 409 if (i2c->msg->flags & I2C_M_RD)410 i2c->state = STATE_READ;411 else412 i2c->state = STATE_WRITE;413 414 /*415 * Terminate the transfer if there is nothing to do416 * as this is used by the i2c probe to find devices.417 */418 if (is_lastmsg(i2c) && i2c->msg->len == 0) {419 s3c24xx_i2c_stop(i2c, 0);420 goto out_ack;421 }422 423 if (i2c->state == STATE_READ)424 goto prepare_read;425 426 /*427 * fall through to the write state, as we will need to428 * send a byte as well429 */430 fallthrough;431 case STATE_WRITE:432 /*433 * we are writing data to the device... check for the434 * end of the message, and if so, work out what to do435 */436 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {437 if (iicstat & S3C2410_IICSTAT_LASTBIT) {438 dev_dbg(i2c->dev, "WRITE: No Ack\n");439 440 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);441 goto out_ack;442 }443 }444 445 retry_write:446 447 if (!is_msgend(i2c)) {448 byte = i2c->msg->buf[i2c->msg_ptr++];449 writeb(byte, i2c->regs + S3C2410_IICDS);450 451 /*452 * delay after writing the byte to allow the453 * data setup time on the bus, as writing the454 * data to the register causes the first bit455 * to appear on SDA, and SCL will change as456 * soon as the interrupt is acknowledged457 */458 ndelay(i2c->tx_setup);459 460 } else if (!is_lastmsg(i2c)) {461 /* we need to go to the next i2c message */462 463 dev_dbg(i2c->dev, "WRITE: Next Message\n");464 465 i2c->msg_ptr = 0;466 i2c->msg_idx++;467 i2c->msg++;468 469 /* check to see if we need to do another message */470 if (i2c->msg->flags & I2C_M_NOSTART) {471 472 if (i2c->msg->flags & I2C_M_RD) {473 /*474 * cannot do this, the controller475 * forces us to send a new START476 * when we change direction477 */478 dev_dbg(i2c->dev,479 "missing START before write->read\n");480 s3c24xx_i2c_stop(i2c, -EINVAL);481 break;482 }483 484 goto retry_write;485 } else {486 /* send the new start */487 s3c24xx_i2c_message_start(i2c, i2c->msg);488 i2c->state = STATE_START;489 }490 491 } else {492 /* send stop */493 s3c24xx_i2c_stop(i2c, 0);494 }495 break;496 497 case STATE_READ:498 /*499 * we have a byte of data in the data register, do500 * something with it, and then work out whether we are501 * going to do any more read/write502 */503 byte = readb(i2c->regs + S3C2410_IICDS);504 i2c->msg->buf[i2c->msg_ptr++] = byte;505 506 /* Add actual length to read for smbus block read */507 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)508 i2c->msg->len += byte;509 prepare_read:510 if (is_msglast(i2c)) {511 /* last byte of buffer */512 513 if (is_lastmsg(i2c))514 s3c24xx_i2c_disable_ack(i2c);515 516 } else if (is_msgend(i2c)) {517 /*518 * ok, we've read the entire buffer, see if there519 * is anything else we need to do520 */521 if (is_lastmsg(i2c)) {522 /* last message, send stop and complete */523 dev_dbg(i2c->dev, "READ: Send Stop\n");524 525 s3c24xx_i2c_stop(i2c, 0);526 } else {527 /* go to the next transfer */528 dev_dbg(i2c->dev, "READ: Next Transfer\n");529 530 i2c->msg_ptr = 0;531 i2c->msg_idx++;532 i2c->msg++;533 }534 }535 536 break;537 }538 539 /* acknowlegde the IRQ and get back on with the work */540 541 out_ack:542 tmp = readl(i2c->regs + S3C2410_IICCON);543 tmp &= ~S3C2410_IICCON_IRQPEND;544 writel(tmp, i2c->regs + S3C2410_IICCON);545 out:546 return;547}548 549/*550 * top level IRQ servicing routine551 */552static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)553{554 struct s3c24xx_i2c *i2c = dev_id;555 unsigned long status;556 unsigned long tmp;557 558 status = readl(i2c->regs + S3C2410_IICSTAT);559 560 if (status & S3C2410_IICSTAT_ARBITR) {561 /* deal with arbitration loss */562 dev_err(i2c->dev, "deal with arbitration loss\n");563 }564 565 if (i2c->state == STATE_IDLE) {566 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");567 568 tmp = readl(i2c->regs + S3C2410_IICCON);569 tmp &= ~S3C2410_IICCON_IRQPEND;570 writel(tmp, i2c->regs + S3C2410_IICCON);571 goto out;572 }573 574 /*575 * pretty much this leaves us with the fact that we've576 * transmitted or received whatever byte we last sent577 */578 i2c_s3c_irq_nextbyte(i2c, status);579 580 out:581 return IRQ_HANDLED;582}583 584/*585 * Disable the bus so that we won't get any interrupts from now on, or try586 * to drive any lines. This is the default state when we don't have587 * anything to send/receive.588 *589 * If there is an event on the bus, or we have a pre-existing event at590 * kernel boot time, we may not notice the event and the I2C controller591 * will lock the bus with the I2C clock line low indefinitely.592 */593static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)594{595 unsigned long tmp;596 597 /* Stop driving the I2C pins */598 tmp = readl(i2c->regs + S3C2410_IICSTAT);599 tmp &= ~S3C2410_IICSTAT_TXRXEN;600 writel(tmp, i2c->regs + S3C2410_IICSTAT);601 602 /* We don't expect any interrupts now, and don't want send acks */603 tmp = readl(i2c->regs + S3C2410_IICCON);604 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |605 S3C2410_IICCON_ACKEN);606 writel(tmp, i2c->regs + S3C2410_IICCON);607}608 609 610/*611 * get the i2c bus for a master transaction612 */613static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)614{615 unsigned long iicstat;616 int timeout = 400;617 618 while (timeout-- > 0) {619 iicstat = readl(i2c->regs + S3C2410_IICSTAT);620 621 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))622 return 0;623 624 msleep(1);625 }626 627 return -ETIMEDOUT;628}629 630/*631 * wait for the i2c bus to become idle.632 */633static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)634{635 unsigned long iicstat;636 ktime_t start, now;637 unsigned long delay;638 int spins;639 640 /* ensure the stop has been through the bus */641 642 dev_dbg(i2c->dev, "waiting for bus idle\n");643 644 start = now = ktime_get();645 646 /*647 * Most of the time, the bus is already idle within a few usec of the648 * end of a transaction. However, really slow i2c devices can stretch649 * the clock, delaying STOP generation.650 *651 * On slower SoCs this typically happens within a very small number of652 * instructions so busy wait briefly to avoid scheduling overhead.653 */654 spins = 3;655 iicstat = readl(i2c->regs + S3C2410_IICSTAT);656 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {657 cpu_relax();658 iicstat = readl(i2c->regs + S3C2410_IICSTAT);659 }660 661 /*662 * If we do get an appreciable delay as a compromise between idle663 * detection latency for the normal, fast case, and system load in the664 * slow device case, use an exponential back off in the polling loop,665 * up to 1/10th of the total timeout, then continue to poll at a666 * constant rate up to the timeout.667 */668 delay = 1;669 while ((iicstat & S3C2410_IICSTAT_START) &&670 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {671 usleep_range(delay, 2 * delay);672 if (delay < S3C2410_IDLE_TIMEOUT / 10)673 delay <<= 1;674 now = ktime_get();675 iicstat = readl(i2c->regs + S3C2410_IICSTAT);676 }677 678 if (iicstat & S3C2410_IICSTAT_START)679 dev_warn(i2c->dev, "timeout waiting for bus idle\n");680}681 682/*683 * this starts an i2c transfer684 */685static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,686 struct i2c_msg *msgs, int num)687{688 long time_left = 0;689 int ret;690 691 ret = s3c24xx_i2c_set_master(i2c);692 if (ret != 0) {693 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);694 ret = -EAGAIN;695 goto out;696 }697 698 i2c->msg = msgs;699 i2c->msg_num = num;700 i2c->msg_ptr = 0;701 i2c->msg_idx = 0;702 i2c->state = STATE_START;703 704 s3c24xx_i2c_enable_irq(i2c);705 s3c24xx_i2c_message_start(i2c, msgs);706 707 if (i2c->quirks & (QUIRK_POLL | QUIRK_ATOMIC)) {708 while ((i2c->msg_num != 0) && is_ack(i2c)) {709 unsigned long stat = readl(i2c->regs + S3C2410_IICSTAT);710 711 i2c_s3c_irq_nextbyte(i2c, stat);712 713 stat = readl(i2c->regs + S3C2410_IICSTAT);714 if (stat & S3C2410_IICSTAT_ARBITR)715 dev_err(i2c->dev, "deal with arbitration loss\n");716 }717 } else {718 time_left = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);719 }720 721 ret = i2c->msg_idx;722 723 /*724 * Having these next two as dev_err() makes life very725 * noisy when doing an i2cdetect726 */727 if (time_left == 0)728 dev_dbg(i2c->dev, "timeout\n");729 else if (ret != num)730 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);731 732 /* For QUIRK_HDMIPHY, bus is already disabled */733 if (i2c->quirks & QUIRK_HDMIPHY)734 goto out;735 736 s3c24xx_i2c_wait_idle(i2c);737 738 s3c24xx_i2c_disable_bus(i2c);739 740 out:741 i2c->state = STATE_IDLE;742 743 return ret;744}745 746/*747 * first port of call from the i2c bus code when an message needs748 * transferring across the i2c bus.749 */750static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,751 struct i2c_msg *msgs, int num)752{753 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;754 int retry;755 int ret;756 757 ret = clk_enable(i2c->clk);758 if (ret)759 return ret;760 761 for (retry = 0; retry < adap->retries; retry++) {762 763 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);764 765 if (ret != -EAGAIN) {766 clk_disable(i2c->clk);767 return ret;768 }769 770 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);771 772 udelay(100);773 }774 775 clk_disable(i2c->clk);776 return -EREMOTEIO;777}778 779static int s3c24xx_i2c_xfer_atomic(struct i2c_adapter *adap,780 struct i2c_msg *msgs, int num)781{782 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;783 int ret;784 785 disable_irq(i2c->irq);786 i2c->quirks |= QUIRK_ATOMIC;787 ret = s3c24xx_i2c_xfer(adap, msgs, num);788 i2c->quirks &= ~QUIRK_ATOMIC;789 enable_irq(i2c->irq);790 791 return ret;792}793 794/* declare our i2c functionality */795static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)796{797 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART |798 I2C_FUNC_PROTOCOL_MANGLING;799}800 801/* i2c bus registration info */802static const struct i2c_algorithm s3c24xx_i2c_algorithm = {803 .master_xfer = s3c24xx_i2c_xfer,804 .master_xfer_atomic = s3c24xx_i2c_xfer_atomic,805 .functionality = s3c24xx_i2c_func,806};807 808/*809 * return the divisor settings for a given frequency810 */811static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,812 unsigned int *div1, unsigned int *divs)813{814 unsigned int calc_divs = clkin / wanted;815 unsigned int calc_div1;816 817 if (calc_divs > (16*16))818 calc_div1 = 512;819 else820 calc_div1 = 16;821 822 calc_divs += calc_div1-1;823 calc_divs /= calc_div1;824 825 if (calc_divs == 0)826 calc_divs = 1;827 if (calc_divs > 17)828 calc_divs = 17;829 830 *divs = calc_divs;831 *div1 = calc_div1;832 833 return clkin / (calc_divs * calc_div1);834}835 836/*837 * work out a divisor for the user requested frequency setting,838 * either by the requested frequency, or scanning the acceptable839 * range of frequencies until something is found840 */841static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)842{843 struct s3c2410_platform_i2c *pdata = i2c->pdata;844 unsigned long clkin = clk_get_rate(i2c->clk);845 unsigned int divs, div1;846 unsigned long target_frequency;847 u32 iiccon;848 int freq;849 850 i2c->clkrate = clkin;851 clkin /= 1000; /* clkin now in KHz */852 853 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);854 855 target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ;856 857 target_frequency /= 1000; /* Target frequency now in KHz */858 859 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);860 861 if (freq > target_frequency) {862 dev_err(i2c->dev,863 "Unable to achieve desired frequency %luKHz." \864 " Lowest achievable %dKHz\n", target_frequency, freq);865 return -EINVAL;866 }867 868 *got = freq;869 870 iiccon = readl(i2c->regs + S3C2410_IICCON);871 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);872 iiccon |= (divs-1);873 874 if (div1 == 512)875 iiccon |= S3C2410_IICCON_TXDIV_512;876 877 if (i2c->quirks & QUIRK_POLL)878 iiccon |= S3C2410_IICCON_SCALE(2);879 880 writel(iiccon, i2c->regs + S3C2410_IICCON);881 882 if (i2c->quirks & QUIRK_S3C2440) {883 unsigned long sda_delay;884 885 if (pdata->sda_delay) {886 sda_delay = clkin * pdata->sda_delay;887 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);888 sda_delay = DIV_ROUND_UP(sda_delay, 5);889 if (sda_delay > 3)890 sda_delay = 3;891 sda_delay |= S3C2410_IICLC_FILTER_ON;892 } else893 sda_delay = 0;894 895 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);896 writel(sda_delay, i2c->regs + S3C2440_IICLC);897 }898 899 return 0;900}901 902#ifdef CONFIG_OF903static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)904{905 int i;906 907 if (i2c->quirks & QUIRK_NO_GPIO)908 return 0;909 910 for (i = 0; i < 2; i++) {911 i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,912 i, GPIOD_ASIS);913 if (IS_ERR(i2c->gpios[i])) {914 dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);915 return -EINVAL;916 }917 }918 return 0;919}920 921#else922static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)923{924 return 0;925}926#endif927 928/*929 * initialise the controller, set the IO lines and frequency930 */931static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)932{933 struct s3c2410_platform_i2c *pdata;934 unsigned int freq;935 936 /* get the plafrom data */937 938 pdata = i2c->pdata;939 940 /* write slave address */941 942 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);943 944 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);945 946 writel(0, i2c->regs + S3C2410_IICCON);947 writel(0, i2c->regs + S3C2410_IICSTAT);948 949 /* we need to work out the divisors for the clock... */950 951 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {952 dev_err(i2c->dev, "cannot meet bus frequency required\n");953 return -EINVAL;954 }955 956 /* todo - check that the i2c lines aren't being dragged anywhere */957 958 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);959 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",960 readl(i2c->regs + S3C2410_IICCON));961 962 return 0;963}964 965#ifdef CONFIG_OF966/*967 * Parse the device tree node and retreive the platform data.968 */969static void970s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)971{972 struct s3c2410_platform_i2c *pdata = i2c->pdata;973 int id;974 975 if (!np)976 return;977 978 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */979 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);980 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);981 of_property_read_u32(np, "samsung,i2c-max-bus-freq",982 (u32 *)&pdata->frequency);983 /*984 * Exynos5's legacy i2c controller and new high speed i2c985 * controller have muxed interrupt sources. By default the986 * interrupts for 4-channel HS-I2C controller are enabled.987 * If nodes for first four channels of legacy i2c controller988 * are available then re-configure the interrupts via the989 * system register.990 */991 id = of_alias_get_id(np, "i2c");992 i2c->sysreg = syscon_regmap_lookup_by_phandle(np,993 "samsung,sysreg-phandle");994 if (IS_ERR(i2c->sysreg))995 return;996 997 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);998}999#else1000static void1001s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }1002#endif1003 1004static int s3c24xx_i2c_probe(struct platform_device *pdev)1005{1006 struct s3c24xx_i2c *i2c;1007 struct s3c2410_platform_i2c *pdata = NULL;1008 struct resource *res;1009 int ret;1010 1011 if (!pdev->dev.of_node) {1012 pdata = dev_get_platdata(&pdev->dev);1013 if (!pdata) {1014 dev_err(&pdev->dev, "no platform data\n");1015 return -EINVAL;1016 }1017 }1018 1019 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);1020 if (!i2c)1021 return -ENOMEM;1022 1023 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);1024 if (!i2c->pdata)1025 return -ENOMEM;1026 1027 i2c->quirks = s3c24xx_get_device_quirks(pdev);1028 i2c->sysreg = ERR_PTR(-ENOENT);1029 if (pdata)1030 memcpy(i2c->pdata, pdata, sizeof(*pdata));1031 else1032 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);1033 1034 strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));1035 i2c->adap.owner = THIS_MODULE;1036 i2c->adap.algo = &s3c24xx_i2c_algorithm;1037 i2c->adap.retries = 2;1038 i2c->adap.class = I2C_CLASS_DEPRECATED;1039 i2c->tx_setup = 50;1040 1041 init_waitqueue_head(&i2c->wait);1042 1043 /* find the clock and enable it */1044 i2c->dev = &pdev->dev;1045 i2c->clk = devm_clk_get(&pdev->dev, "i2c");1046 if (IS_ERR(i2c->clk)) {1047 dev_err(&pdev->dev, "cannot get clock\n");1048 return -ENOENT;1049 }1050 1051 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);1052 1053 /* map the registers */1054 i2c->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);1055 if (IS_ERR(i2c->regs))1056 return PTR_ERR(i2c->regs);1057 1058 dev_dbg(&pdev->dev, "registers %p (%p)\n",1059 i2c->regs, res);1060 1061 /* setup info block for the i2c core */1062 i2c->adap.algo_data = i2c;1063 i2c->adap.dev.parent = &pdev->dev;1064 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);1065 1066 /* inititalise the i2c gpio lines */1067 if (i2c->pdata->cfg_gpio)1068 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));1069 else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))1070 return -EINVAL;1071 1072 /* initialise the i2c controller */1073 ret = clk_prepare_enable(i2c->clk);1074 if (ret) {1075 dev_err(&pdev->dev, "I2C clock enable failed\n");1076 return ret;1077 }1078 1079 ret = s3c24xx_i2c_init(i2c);1080 clk_disable(i2c->clk);1081 if (ret != 0) {1082 dev_err(&pdev->dev, "I2C controller init failed\n");1083 clk_unprepare(i2c->clk);1084 return ret;1085 }1086 1087 /*1088 * find the IRQ for this unit (note, this relies on the init call to1089 * ensure no current IRQs pending1090 */1091 if (!(i2c->quirks & QUIRK_POLL)) {1092 i2c->irq = ret = platform_get_irq(pdev, 0);1093 if (ret < 0) {1094 clk_unprepare(i2c->clk);1095 return ret;1096 }1097 1098 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,1099 0, dev_name(&pdev->dev), i2c);1100 if (ret != 0) {1101 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);1102 clk_unprepare(i2c->clk);1103 return ret;1104 }1105 }1106 1107 /*1108 * Note, previous versions of the driver used i2c_add_adapter()1109 * to add the bus at any number. We now pass the bus number via1110 * the platform data, so if unset it will now default to always1111 * being bus 0.1112 */1113 i2c->adap.nr = i2c->pdata->bus_num;1114 i2c->adap.dev.of_node = pdev->dev.of_node;1115 1116 platform_set_drvdata(pdev, i2c);1117 1118 pm_runtime_enable(&pdev->dev);1119 1120 ret = i2c_add_numbered_adapter(&i2c->adap);1121 if (ret < 0) {1122 pm_runtime_disable(&pdev->dev);1123 clk_unprepare(i2c->clk);1124 return ret;1125 }1126 1127 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));1128 return 0;1129}1130 1131static void s3c24xx_i2c_remove(struct platform_device *pdev)1132{1133 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);1134 1135 clk_unprepare(i2c->clk);1136 1137 pm_runtime_disable(&pdev->dev);1138 1139 i2c_del_adapter(&i2c->adap);1140}1141 1142static int s3c24xx_i2c_suspend_noirq(struct device *dev)1143{1144 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);1145 1146 i2c_mark_adapter_suspended(&i2c->adap);1147 1148 if (!IS_ERR(i2c->sysreg))1149 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);1150 1151 return 0;1152}1153 1154static int s3c24xx_i2c_resume_noirq(struct device *dev)1155{1156 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);1157 int ret;1158 1159 if (!IS_ERR(i2c->sysreg))1160 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);1161 1162 ret = clk_enable(i2c->clk);1163 if (ret)1164 return ret;1165 s3c24xx_i2c_init(i2c);1166 clk_disable(i2c->clk);1167 i2c_mark_adapter_resumed(&i2c->adap);1168 1169 return 0;1170}1171 1172static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {1173 NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,1174 s3c24xx_i2c_resume_noirq)1175};1176 1177static struct platform_driver s3c24xx_i2c_driver = {1178 .probe = s3c24xx_i2c_probe,1179 .remove_new = s3c24xx_i2c_remove,1180 .id_table = s3c24xx_driver_ids,1181 .driver = {1182 .name = "s3c-i2c",1183 .pm = pm_sleep_ptr(&s3c24xx_i2c_dev_pm_ops),1184 .of_match_table = of_match_ptr(s3c24xx_i2c_match),1185 },1186};1187 1188static int __init i2c_adap_s3c_init(void)1189{1190 return platform_driver_register(&s3c24xx_i2c_driver);1191}1192subsys_initcall(i2c_adap_s3c_init);1193 1194static void __exit i2c_adap_s3c_exit(void)1195{1196 platform_driver_unregister(&s3c24xx_i2c_driver);1197}1198module_exit(i2c_adap_s3c_exit);1199 1200MODULE_DESCRIPTION("S3C24XX I2C Bus driver");1201MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");1202MODULE_LICENSE("GPL");1203