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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>4 */5 6#include <linux/clk.h>7#include <linux/i2c.h>8#include <linux/iopoll.h>9#include <linux/interrupt.h>10#include <linux/io.h>11#include <linux/module.h>12#include <linux/platform_device.h>13 14#define UNIPHIER_FI2C_CR 0x00 /* control register */15#define UNIPHIER_FI2C_CR_MST BIT(3) /* controller mode */16#define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */17#define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */18#define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */19#define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */20#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (target addr) */21#define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */22#define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */23#define UNIPHIER_FI2C_SLAD 0x0c /* target address */24#define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */25#define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */26#define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */27#define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */28#define UNIPHIER_FI2C_INT 0x20 /* interrupt status */29#define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */30#define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */31#define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */32#define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */33#define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */34#define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */35#define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */36#define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */37#define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */38#define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */39#define UNIPHIER_FI2C_SR 0x2c /* status register */40#define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */41#define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */42#define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */43#define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */44#define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */45#define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */46#define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */47#define UNIPHIER_FI2C_RST 0x34 /* reset control */48#define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */49#define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */50#define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */51#define UNIPHIER_FI2C_BM 0x38 /* bus monitor */52#define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */53#define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */54#define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */55#define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */56#define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */57#define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */58#define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */59#define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */60#define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */61#define UNIPHIER_FI2C_BRST 0x50 /* bus reset */62#define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */63#define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */64 65#define UNIPHIER_FI2C_INT_FAULTS \66 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)67#define UNIPHIER_FI2C_INT_STOP \68 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)69 70#define UNIPHIER_FI2C_RD BIT(0)71#define UNIPHIER_FI2C_STOP BIT(1)72#define UNIPHIER_FI2C_MANUAL_NACK BIT(2)73#define UNIPHIER_FI2C_BYTE_WISE BIT(3)74#define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4)75 76#define UNIPHIER_FI2C_FIFO_SIZE 877 78struct uniphier_fi2c_priv {79 struct completion comp;80 struct i2c_adapter adap;81 void __iomem *membase;82 struct clk *clk;83 unsigned int len;84 u8 *buf;85 u32 enabled_irqs;86 int error;87 unsigned int flags;88 unsigned int busy_cnt;89 unsigned int clk_cycle;90 spinlock_t lock; /* IRQ synchronization */91};92 93static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,94 bool first)95{96 int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;97 98 /*99 * TX-FIFO stores target address in it for the first access.100 * Decrement the counter.101 */102 if (first)103 fifo_space--;104 105 while (priv->len) {106 if (fifo_space-- <= 0)107 break;108 109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);110 priv->len--;111 }112}113 114static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)115{116 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?117 1 : UNIPHIER_FI2C_FIFO_SIZE;118 119 while (priv->len) {120 if (fifo_left-- <= 0)121 break;122 123 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);124 priv->len--;125 }126}127 128static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)129{130 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);131}132 133static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv,134 u32 mask)135{136 writel(mask, priv->membase + UNIPHIER_FI2C_IC);137}138 139static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)140{141 priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;142 uniphier_fi2c_set_irqs(priv);143 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,144 priv->membase + UNIPHIER_FI2C_CR);145}146 147static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)148{149 struct uniphier_fi2c_priv *priv = dev_id;150 u32 irq_status;151 152 spin_lock(&priv->lock);153 154 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);155 irq_status &= priv->enabled_irqs;156 157 if (irq_status & UNIPHIER_FI2C_INT_STOP)158 goto complete;159 160 if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {161 priv->error = -EAGAIN;162 goto complete;163 }164 165 if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {166 priv->error = -ENXIO;167 if (priv->flags & UNIPHIER_FI2C_RD) {168 /*169 * work around a hardware bug:170 * The receive-completed interrupt is never set even if171 * STOP condition is detected after the address phase172 * of read transaction fails to get ACK.173 * To avoid time-out error, we issue STOP here,174 * but do not wait for its completion.175 * It should be checked after exiting this handler.176 */177 uniphier_fi2c_stop(priv);178 priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;179 goto complete;180 }181 goto stop;182 }183 184 if (irq_status & UNIPHIER_FI2C_INT_TE) {185 if (!priv->len)186 goto data_done;187 188 uniphier_fi2c_fill_txfifo(priv, false);189 goto handled;190 }191 192 if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {193 uniphier_fi2c_drain_rxfifo(priv);194 /*195 * If the number of bytes to read is multiple of the FIFO size196 * (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little197 * earlier than INT_RB. We wait for INT_RB to confirm the198 * completion of the current message.199 */200 if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB))201 goto data_done;202 203 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {204 if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&205 !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {206 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;207 uniphier_fi2c_set_irqs(priv);208 priv->flags |= UNIPHIER_FI2C_BYTE_WISE;209 }210 if (priv->len <= 1)211 writel(UNIPHIER_FI2C_CR_MST |212 UNIPHIER_FI2C_CR_NACK,213 priv->membase + UNIPHIER_FI2C_CR);214 }215 216 goto handled;217 }218 219 spin_unlock(&priv->lock);220 221 return IRQ_NONE;222 223data_done:224 if (priv->flags & UNIPHIER_FI2C_STOP) {225stop:226 uniphier_fi2c_stop(priv);227 } else {228complete:229 priv->enabled_irqs = 0;230 uniphier_fi2c_set_irqs(priv);231 complete(&priv->comp);232 }233 234handled:235 /*236 * This controller makes a pause while any bit of the IRQ status is237 * asserted. Clear the asserted bit to kick the controller just before238 * exiting the handler.239 */240 uniphier_fi2c_clear_irqs(priv, irq_status);241 242 spin_unlock(&priv->lock);243 244 return IRQ_HANDLED;245}246 247static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr,248 bool repeat)249{250 priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;251 uniphier_fi2c_set_irqs(priv);252 253 /* do not use TX byte counter */254 writel(0, priv->membase + UNIPHIER_FI2C_TBC);255 /* set target address */256 writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,257 priv->membase + UNIPHIER_FI2C_DTTX);258 /*259 * First chunk of data. For a repeated START condition, do not write260 * data to the TX fifo here to avoid the timing issue.261 */262 if (!repeat)263 uniphier_fi2c_fill_txfifo(priv, true);264}265 266static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)267{268 priv->flags |= UNIPHIER_FI2C_RD;269 270 if (likely(priv->len < 256)) {271 /*272 * If possible, use RX byte counter.273 * It can automatically handle NACK for the last byte.274 */275 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);276 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |277 UNIPHIER_FI2C_INT_RB;278 } else {279 /*280 * The byte counter can not count over 256. In this case,281 * do not use it at all. Drain data when FIFO gets full,282 * but treat the last portion as a special case.283 */284 writel(0, priv->membase + UNIPHIER_FI2C_RBC);285 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;286 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;287 }288 289 uniphier_fi2c_set_irqs(priv);290 291 /* set target address with RD bit */292 writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,293 priv->membase + UNIPHIER_FI2C_DTTX);294}295 296static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)297{298 writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);299}300 301static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)302{303 writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,304 priv->membase + UNIPHIER_FI2C_BRST);305}306 307static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)308{309 uniphier_fi2c_reset(priv);310 i2c_recover_bus(&priv->adap);311}312 313static int uniphier_fi2c_xfer_one(struct i2c_adapter *adap, struct i2c_msg *msg,314 bool repeat, bool stop)315{316 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);317 bool is_read = msg->flags & I2C_M_RD;318 unsigned long time_left, flags;319 320 priv->len = msg->len;321 priv->buf = msg->buf;322 priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;323 priv->error = 0;324 priv->flags = 0;325 326 if (stop)327 priv->flags |= UNIPHIER_FI2C_STOP;328 329 reinit_completion(&priv->comp);330 uniphier_fi2c_clear_irqs(priv, U32_MAX);331 writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,332 priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */333 334 spin_lock_irqsave(&priv->lock, flags);335 336 if (is_read)337 uniphier_fi2c_rx_init(priv, msg->addr);338 else339 uniphier_fi2c_tx_init(priv, msg->addr, repeat);340 341 /*342 * For a repeated START condition, writing a target address to the FIFO343 * kicks the controller. So, the UNIPHIER_FI2C_CR register should be344 * written only for a non-repeated START condition.345 */346 if (!repeat)347 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,348 priv->membase + UNIPHIER_FI2C_CR);349 350 spin_unlock_irqrestore(&priv->lock, flags);351 352 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);353 354 spin_lock_irqsave(&priv->lock, flags);355 priv->enabled_irqs = 0;356 uniphier_fi2c_set_irqs(priv);357 spin_unlock_irqrestore(&priv->lock, flags);358 359 if (!time_left) {360 uniphier_fi2c_recover(priv);361 return -ETIMEDOUT;362 }363 364 if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {365 u32 status;366 int ret;367 368 ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR,369 status,370 (status & UNIPHIER_FI2C_SR_STS) &&371 !(status & UNIPHIER_FI2C_SR_BB),372 1, 20);373 if (ret) {374 dev_err(&adap->dev,375 "stop condition was not completed.\n");376 uniphier_fi2c_recover(priv);377 return ret;378 }379 }380 381 return priv->error;382}383 384static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)385{386 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);387 388 if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {389 if (priv->busy_cnt++ > 3) {390 /*391 * If bus busy continues too long, it is probably392 * in a wrong state. Try bus recovery.393 */394 uniphier_fi2c_recover(priv);395 priv->busy_cnt = 0;396 }397 398 return -EAGAIN;399 }400 401 priv->busy_cnt = 0;402 return 0;403}404 405static int uniphier_fi2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)406{407 struct i2c_msg *msg, *emsg = msgs + num;408 bool repeat = false;409 int ret;410 411 ret = uniphier_fi2c_check_bus_busy(adap);412 if (ret)413 return ret;414 415 for (msg = msgs; msg < emsg; msg++) {416 /* Emit STOP if it is the last message or I2C_M_STOP is set. */417 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);418 419 ret = uniphier_fi2c_xfer_one(adap, msg, repeat, stop);420 if (ret)421 return ret;422 423 repeat = !stop;424 }425 426 return num;427}428 429static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)430{431 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;432}433 434static const struct i2c_algorithm uniphier_fi2c_algo = {435 .xfer = uniphier_fi2c_xfer,436 .functionality = uniphier_fi2c_functionality,437};438 439static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)440{441 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);442 443 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &444 UNIPHIER_FI2C_BM_SCLS);445}446 447static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)448{449 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);450 451 writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,452 priv->membase + UNIPHIER_FI2C_BRST);453}454 455static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)456{457 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);458 459 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &460 UNIPHIER_FI2C_BM_SDAS);461}462 463static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)464{465 uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));466}467 468static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {469 .recover_bus = i2c_generic_scl_recovery,470 .get_scl = uniphier_fi2c_get_scl,471 .set_scl = uniphier_fi2c_set_scl,472 .get_sda = uniphier_fi2c_get_sda,473 .unprepare_recovery = uniphier_fi2c_unprepare_recovery,474};475 476static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv)477{478 unsigned int cyc = priv->clk_cycle;479 u32 tmp;480 481 tmp = readl(priv->membase + UNIPHIER_FI2C_CR);482 tmp |= UNIPHIER_FI2C_CR_MST;483 writel(tmp, priv->membase + UNIPHIER_FI2C_CR);484 485 uniphier_fi2c_reset(priv);486 487 /*488 * Standard-mode: tLOW + tHIGH = 10 us489 * Fast-mode: tLOW + tHIGH = 2.5 us490 */491 writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);492 /*493 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us494 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us495 * "tLow/tHIGH = 5/4" meets both.496 */497 writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL);498 /*499 * Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us500 * Fast-mode: tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us501 */502 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);503 /*504 * Standard-mode: tSU;DAT = 250 ns505 * Fast-mode: tSU;DAT = 100 ns506 */507 writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);508 509 uniphier_fi2c_prepare_operation(priv);510}511 512static int uniphier_fi2c_probe(struct platform_device *pdev)513{514 struct device *dev = &pdev->dev;515 struct uniphier_fi2c_priv *priv;516 u32 bus_speed;517 unsigned long clk_rate;518 int irq, ret;519 520 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);521 if (!priv)522 return -ENOMEM;523 524 priv->membase = devm_platform_ioremap_resource(pdev, 0);525 if (IS_ERR(priv->membase))526 return PTR_ERR(priv->membase);527 528 irq = platform_get_irq(pdev, 0);529 if (irq < 0)530 return irq;531 532 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))533 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;534 535 if (!bus_speed || bus_speed > I2C_MAX_FAST_MODE_FREQ) {536 dev_err(dev, "invalid clock-frequency %d\n", bus_speed);537 return -EINVAL;538 }539 540 priv->clk = devm_clk_get_enabled(dev, NULL);541 if (IS_ERR(priv->clk)) {542 dev_err(dev, "failed to enable clock\n");543 return PTR_ERR(priv->clk);544 }545 546 clk_rate = clk_get_rate(priv->clk);547 if (!clk_rate) {548 dev_err(dev, "input clock rate should not be zero\n");549 return -EINVAL;550 }551 552 priv->clk_cycle = clk_rate / bus_speed;553 init_completion(&priv->comp);554 spin_lock_init(&priv->lock);555 priv->adap.owner = THIS_MODULE;556 priv->adap.algo = &uniphier_fi2c_algo;557 priv->adap.dev.parent = dev;558 priv->adap.dev.of_node = dev->of_node;559 strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));560 priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;561 i2c_set_adapdata(&priv->adap, priv);562 platform_set_drvdata(pdev, priv);563 564 uniphier_fi2c_hw_init(priv);565 566 ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,567 pdev->name, priv);568 if (ret) {569 dev_err(dev, "failed to request irq %d\n", irq);570 return ret;571 }572 573 return i2c_add_adapter(&priv->adap);574}575 576static void uniphier_fi2c_remove(struct platform_device *pdev)577{578 struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);579 580 i2c_del_adapter(&priv->adap);581}582 583static int __maybe_unused uniphier_fi2c_suspend(struct device *dev)584{585 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);586 587 clk_disable_unprepare(priv->clk);588 589 return 0;590}591 592static int __maybe_unused uniphier_fi2c_resume(struct device *dev)593{594 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);595 int ret;596 597 ret = clk_prepare_enable(priv->clk);598 if (ret)599 return ret;600 601 uniphier_fi2c_hw_init(priv);602 603 return 0;604}605 606static const struct dev_pm_ops uniphier_fi2c_pm_ops = {607 SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume)608};609 610static const struct of_device_id uniphier_fi2c_match[] = {611 { .compatible = "socionext,uniphier-fi2c" },612 { /* sentinel */ }613};614MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);615 616static struct platform_driver uniphier_fi2c_drv = {617 .probe = uniphier_fi2c_probe,618 .remove_new = uniphier_fi2c_remove,619 .driver = {620 .name = "uniphier-fi2c",621 .of_match_table = uniphier_fi2c_match,622 .pm = &uniphier_fi2c_pm_ops,623 },624};625module_platform_driver(uniphier_fi2c_drv);626 627MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");628MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");629MODULE_LICENSE("GPL");630