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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright(c) 2024 Shanghai Zhaoxin Semiconductor Corporation.4 * All rights reserved.5 */6 7#include <linux/acpi.h>8#include "i2c-viai2c-common.h"9 10/*11 * registers12 */13/* Zhaoxin specific register bit fields */14/* REG_CR Bit fields */15#define ZXI2C_CR_MST_RST BIT(7)16#define ZXI2C_CR_FIFO_MODE BIT(14)17/* REG_ISR/IMR Bit fields */18#define ZXI2C_IRQ_FIFONACK BIT(4)19#define ZXI2C_IRQ_FIFOEND BIT(3)20#define ZXI2C_IRQ_MASK (VIAI2C_ISR_MASK_ALL \21 | ZXI2C_IRQ_FIFOEND \22 | ZXI2C_IRQ_FIFONACK)23/* Zhaoxin specific registers */24#define ZXI2C_REG_CLK 0x1025#define ZXI2C_CLK_50M BIT(0)26#define ZXI2C_REG_REV 0x1127#define ZXI2C_REG_HCR 0x1228#define ZXI2C_HCR_RST_FIFO GENMASK(1, 0)29#define ZXI2C_REG_HTDR 0x1330#define ZXI2C_REG_HRDR 0x1431#define ZXI2C_REG_HTLR 0x1532#define ZXI2C_REG_HRLR 0x1633#define ZXI2C_REG_HWCNTR 0x1834#define ZXI2C_REG_HRCNTR 0x1935 36/* parameters Constants */37#define ZXI2C_GOLD_FSTP_100K 0xF338#define ZXI2C_GOLD_FSTP_400K 0x3839#define ZXI2C_GOLD_FSTP_1M 0x1340#define ZXI2C_GOLD_FSTP_3400K 0x3741#define ZXI2C_HS_CTRL_CODE (0x08 << 8)42 43#define ZXI2C_FIFO_SIZE 3244 45struct viai2c_zhaoxin {46 u8 hrv;47 u16 tr;48 u16 mcr;49 u16 xfer_len;50};51 52static int viai2c_fifo_xfer(struct viai2c *i2c)53{54 u16 i;55 u8 tmp;56 struct i2c_msg *msg = i2c->msg;57 void __iomem *base = i2c->base;58 bool read = !!(msg->flags & I2C_M_RD);59 struct viai2c_zhaoxin *priv = i2c->pltfm_priv;60 61 /* reset fifo buffer */62 tmp = ioread8(base + ZXI2C_REG_HCR);63 iowrite8(tmp | ZXI2C_HCR_RST_FIFO, base + ZXI2C_REG_HCR);64 65 /* set xfer len */66 priv->xfer_len = min_t(u16, msg->len - i2c->xfered_len, ZXI2C_FIFO_SIZE);67 if (read) {68 iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HRLR);69 } else {70 iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HTLR);71 /* set write data */72 for (i = 0; i < priv->xfer_len; i++)73 iowrite8(msg->buf[i2c->xfered_len + i], base + ZXI2C_REG_HTDR);74 }75 76 /* prepare to stop transmission */77 if (priv->hrv && msg->len == (i2c->xfered_len + priv->xfer_len)) {78 tmp = ioread8(base + VIAI2C_REG_CR);79 tmp |= read ? VIAI2C_CR_RX_END : VIAI2C_CR_TX_END;80 iowrite8(tmp, base + VIAI2C_REG_CR);81 }82 83 u16 tcr_val = i2c->tcr;84 85 /* start transmission */86 tcr_val |= read ? VIAI2C_TCR_READ : 0;87 writew(tcr_val | msg->addr, base + VIAI2C_REG_TCR);88 89 return 0;90}91 92static int viai2c_fifo_irq_xfer(struct viai2c *i2c)93{94 u16 i;95 u8 tmp;96 struct i2c_msg *msg = i2c->msg;97 void __iomem *base = i2c->base;98 bool read = !!(msg->flags & I2C_M_RD);99 struct viai2c_zhaoxin *priv = i2c->pltfm_priv;100 101 /* get the received data */102 if (read)103 for (i = 0; i < priv->xfer_len; i++)104 msg->buf[i2c->xfered_len + i] = ioread8(base + ZXI2C_REG_HRDR);105 106 i2c->xfered_len += priv->xfer_len;107 if (i2c->xfered_len == msg->len)108 return 1;109 110 /* reset fifo buffer */111 tmp = ioread8(base + ZXI2C_REG_HCR);112 iowrite8(tmp | ZXI2C_HCR_RST_FIFO, base + ZXI2C_REG_HCR);113 114 /* set xfer len */115 priv->xfer_len = min_t(u16, msg->len - i2c->xfered_len, ZXI2C_FIFO_SIZE);116 if (read) {117 iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HRLR);118 } else {119 iowrite8(priv->xfer_len - 1, base + ZXI2C_REG_HTLR);120 /* set write data */121 for (i = 0; i < priv->xfer_len; i++)122 iowrite8(msg->buf[i2c->xfered_len + i], base + ZXI2C_REG_HTDR);123 }124 125 /* prepare to stop transmission */126 if (priv->hrv && msg->len == (i2c->xfered_len + priv->xfer_len)) {127 tmp = ioread8(base + VIAI2C_REG_CR);128 tmp |= read ? VIAI2C_CR_RX_END : VIAI2C_CR_TX_END;129 iowrite8(tmp, base + VIAI2C_REG_CR);130 }131 132 /* continue transmission */133 tmp = ioread8(base + VIAI2C_REG_CR);134 iowrite8(tmp |= VIAI2C_CR_CPU_RDY, base + VIAI2C_REG_CR);135 136 return 0;137}138 139static int zxi2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)140{141 u8 tmp;142 int ret;143 struct viai2c *i2c = (struct viai2c *)i2c_get_adapdata(adap);144 struct viai2c_zhaoxin *priv = i2c->pltfm_priv;145 void __iomem *base = i2c->base;146 147 ret = viai2c_wait_bus_not_busy(i2c);148 if (ret)149 return ret;150 151 tmp = ioread8(base + VIAI2C_REG_CR);152 tmp &= ~(VIAI2C_CR_RX_END | VIAI2C_CR_TX_END);153 154 if (num == 1 && msgs->len >= 2 && (priv->hrv || msgs->len <= ZXI2C_FIFO_SIZE)) {155 /* enable fifo mode */156 iowrite16(ZXI2C_CR_FIFO_MODE | tmp, base + VIAI2C_REG_CR);157 /* clear irq status */158 iowrite8(ZXI2C_IRQ_MASK, base + VIAI2C_REG_ISR);159 /* enable fifo irq */160 iowrite8(VIAI2C_ISR_NACK_ADDR | ZXI2C_IRQ_FIFOEND, base + VIAI2C_REG_IMR);161 162 i2c->msg = msgs;163 i2c->mode = VIAI2C_FIFO_MODE;164 priv->xfer_len = 0;165 i2c->xfered_len = 0;166 167 viai2c_fifo_xfer(i2c);168 169 if (!wait_for_completion_timeout(&i2c->complete, VIAI2C_TIMEOUT))170 return -ETIMEDOUT;171 172 ret = i2c->ret;173 } else {174 /* enable byte mode */175 iowrite16(tmp, base + VIAI2C_REG_CR);176 /* clear irq status */177 iowrite8(ZXI2C_IRQ_MASK, base + VIAI2C_REG_ISR);178 /* enable byte irq */179 iowrite8(VIAI2C_ISR_NACK_ADDR | VIAI2C_IMR_BYTE, base + VIAI2C_REG_IMR);180 181 ret = viai2c_xfer(adap, msgs, num);182 if (ret == -ETIMEDOUT)183 iowrite16(tmp | VIAI2C_CR_END_MASK, base + VIAI2C_REG_CR);184 }185 /* dis interrupt */186 iowrite8(0, base + VIAI2C_REG_IMR);187 188 return ret;189}190 191static u32 zxi2c_func(struct i2c_adapter *adap)192{193 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;194}195 196static const struct i2c_algorithm zxi2c_algorithm = {197 .xfer = zxi2c_xfer,198 .functionality = zxi2c_func,199};200 201static const struct i2c_adapter_quirks zxi2c_quirks = {202 .flags = I2C_AQ_NO_ZERO_LEN | I2C_AQ_COMB_WRITE_THEN_READ,203};204 205static const u32 zxi2c_speed_params_table[][3] = {206 /* speed, ZXI2C_TCR, ZXI2C_FSTP */207 { I2C_MAX_STANDARD_MODE_FREQ, 0, ZXI2C_GOLD_FSTP_100K },208 { I2C_MAX_FAST_MODE_FREQ, VIAI2C_TCR_FAST, ZXI2C_GOLD_FSTP_400K },209 { I2C_MAX_FAST_MODE_PLUS_FREQ, VIAI2C_TCR_FAST, ZXI2C_GOLD_FSTP_1M },210 { I2C_MAX_HIGH_SPEED_MODE_FREQ, VIAI2C_TCR_HS_MODE | VIAI2C_TCR_FAST,211 ZXI2C_GOLD_FSTP_3400K },212};213 214static void zxi2c_set_bus_speed(struct viai2c *i2c)215{216 struct viai2c_zhaoxin *priv = i2c->pltfm_priv;217 218 iowrite16(priv->tr, i2c->base + VIAI2C_REG_TR);219 iowrite8(ZXI2C_CLK_50M, i2c->base + ZXI2C_REG_CLK);220 iowrite16(priv->mcr, i2c->base + VIAI2C_REG_MCR);221}222 223static void zxi2c_get_bus_speed(struct viai2c *i2c)224{225 u8 i, count;226 u8 fstp;227 const u32 *params;228 struct viai2c_zhaoxin *priv = i2c->pltfm_priv;229 u32 acpi_speed = i2c_acpi_find_bus_speed(i2c->dev);230 231 count = ARRAY_SIZE(zxi2c_speed_params_table);232 for (i = 0; i < count; i++)233 if (acpi_speed == zxi2c_speed_params_table[i][0])234 break;235 /* if not found, use 400k as default */236 i = i < count ? i : 1;237 238 params = zxi2c_speed_params_table[i];239 fstp = ioread8(i2c->base + VIAI2C_REG_TR);240 if (abs(fstp - params[2]) > 0x10) {241 /*242 * if BIOS setting value far from golden value,243 * use golden value and warn user244 */245 dev_warn(i2c->dev, "FW FSTP[%x] might cause wrong timings, dropped\n", fstp);246 priv->tr = params[2] | 0xff00;247 } else {248 priv->tr = fstp | 0xff00;249 }250 251 i2c->tcr = params[1];252 priv->mcr = ioread16(i2c->base + VIAI2C_REG_MCR);253 /* for Hs-mode, use 0x80 as controller code */254 if (params[0] == I2C_MAX_HIGH_SPEED_MODE_FREQ)255 priv->mcr |= ZXI2C_HS_CTRL_CODE;256 257 dev_info(i2c->dev, "speed mode is %s\n", i2c_freq_mode_string(params[0]));258}259 260static irqreturn_t zxi2c_isr(int irq, void *data)261{262 struct viai2c *i2c = data;263 u8 status;264 265 /* save the status and write-clear it */266 status = readw(i2c->base + VIAI2C_REG_ISR);267 if (!status)268 return IRQ_NONE;269 270 writew(status, i2c->base + VIAI2C_REG_ISR);271 272 i2c->ret = 0;273 if (status & VIAI2C_ISR_NACK_ADDR)274 i2c->ret = -EIO;275 276 if (!i2c->ret) {277 if (i2c->mode == VIAI2C_BYTE_MODE)278 i2c->ret = viai2c_irq_xfer(i2c);279 else280 i2c->ret = viai2c_fifo_irq_xfer(i2c);281 }282 283 /* All the data has been successfully transferred or error occurred */284 if (i2c->ret)285 complete(&i2c->complete);286 287 return IRQ_HANDLED;288}289 290static int zxi2c_probe(struct platform_device *pdev)291{292 int error;293 struct viai2c *i2c;294 struct i2c_adapter *adap;295 struct viai2c_zhaoxin *priv;296 297 error = viai2c_init(pdev, &i2c, VIAI2C_PLAT_ZHAOXIN);298 if (error)299 return error;300 301 i2c->irq = platform_get_irq(pdev, 0);302 if (i2c->irq < 0)303 return i2c->irq;304 305 error = devm_request_irq(&pdev->dev, i2c->irq, zxi2c_isr,306 IRQF_SHARED, pdev->name, i2c);307 if (error)308 return dev_err_probe(&pdev->dev, error,309 "failed to request irq %i\n", i2c->irq);310 311 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);312 if (!priv)313 return -ENOMEM;314 i2c->pltfm_priv = priv;315 316 zxi2c_get_bus_speed(i2c);317 zxi2c_set_bus_speed(i2c);318 319 priv->hrv = ioread8(i2c->base + ZXI2C_REG_REV);320 321 adap = &i2c->adapter;322 adap->owner = THIS_MODULE;323 adap->algo = &zxi2c_algorithm;324 adap->quirks = &zxi2c_quirks;325 adap->dev.parent = &pdev->dev;326 ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));327 snprintf(adap->name, sizeof(adap->name), "zhaoxin-%s-%s",328 dev_name(pdev->dev.parent), dev_name(i2c->dev));329 i2c_set_adapdata(adap, i2c);330 331 return devm_i2c_add_adapter(&pdev->dev, adap);332}333 334static int __maybe_unused zxi2c_resume(struct device *dev)335{336 struct viai2c *i2c = dev_get_drvdata(dev);337 338 iowrite8(ZXI2C_CR_MST_RST, i2c->base + VIAI2C_REG_CR);339 zxi2c_set_bus_speed(i2c);340 341 return 0;342}343 344static const struct dev_pm_ops zxi2c_pm = {345 SET_SYSTEM_SLEEP_PM_OPS(NULL, zxi2c_resume)346};347 348static const struct acpi_device_id zxi2c_acpi_match[] = {349 {"IIC1D17", 0 },350 { }351};352MODULE_DEVICE_TABLE(acpi, zxi2c_acpi_match);353 354static struct platform_driver zxi2c_driver = {355 .probe = zxi2c_probe,356 .driver = {357 .name = "i2c_zhaoxin",358 .acpi_match_table = zxi2c_acpi_match,359 .pm = &zxi2c_pm,360 },361};362 363module_platform_driver(zxi2c_driver);364 365MODULE_AUTHOR("HansHu@zhaoxin.com");366MODULE_DESCRIPTION("Shanghai Zhaoxin IIC driver");367MODULE_LICENSE("GPL");368