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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * I3C HCI Quirks4 *5 * Copyright 2024 Advanced Micro Devices, Inc.6 *7 * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>8 * Guruvendra Punugupati <Guruvendra.Punugupati@amd.com>9 */10 11#include <linux/i3c/master.h>12#include "hci.h"13 14/* Timing registers */15#define HCI_SCL_I3C_OD_TIMING 0x21416#define HCI_SCL_I3C_PP_TIMING 0x21817#define HCI_SDA_HOLD_SWITCH_DLY_TIMING 0x23018 19/* Timing values to configure 9MHz frequency */20#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf21#define AMD_SCL_I3C_PP_TIMING 0x0016001622 23#define QUEUE_THLD_CTRL 0xD024 25void amd_set_od_pp_timing(struct i3c_hci *hci)26{27 u32 data;28 29 reg_write(HCI_SCL_I3C_OD_TIMING, AMD_SCL_I3C_OD_TIMING);30 reg_write(HCI_SCL_I3C_PP_TIMING, AMD_SCL_I3C_PP_TIMING);31 data = reg_read(HCI_SDA_HOLD_SWITCH_DLY_TIMING);32 /* Configure maximum TX hold time */33 data |= W0_MASK(18, 16);34 reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);35}36 37void amd_set_resp_buf_thld(struct i3c_hci *hci)38{39 u32 data;40 41 data = reg_read(QUEUE_THLD_CTRL);42 data = data & ~W0_MASK(15, 8);43 reg_write(QUEUE_THLD_CTRL, data);44}45