1379 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) 2022 ROHM Semiconductors4 *5 * ROHM/KIONIX accelerometer driver6 */7 8#include <linux/delay.h>9#include <linux/device.h>10#include <linux/interrupt.h>11#include <linux/module.h>12#include <linux/moduleparam.h>13#include <linux/mutex.h>14#include <linux/property.h>15#include <linux/regmap.h>16#include <linux/regulator/consumer.h>17#include <linux/slab.h>18#include <linux/string_choices.h>19#include <linux/units.h>20 21#include <linux/iio/iio.h>22#include <linux/iio/sysfs.h>23#include <linux/iio/trigger.h>24#include <linux/iio/trigger_consumer.h>25#include <linux/iio/triggered_buffer.h>26 27#include "kionix-kx022a.h"28 29/*30 * The KX022A has FIFO which can store 43 samples of HiRes data from 231 * channels. This equals to 43 (samples) * 3 (channels) * 2 (bytes/sample) to32 * 258 bytes of sample data. The quirk to know is that the amount of bytes in33 * the FIFO is advertised via 8 bit register (max value 255). The thing to note34 * is that full 258 bytes of data is indicated using the max value 255.35 */36#define KX022A_FIFO_LENGTH 4337#define KX022A_FIFO_FULL_VALUE 25538#define KX022A_SOFT_RESET_WAIT_TIME_US (5 * USEC_PER_MSEC)39#define KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US (500 * USEC_PER_MSEC)40 41/* 3 axis, 2 bytes of data for each of the axis */42#define KX022A_FIFO_SAMPLES_SIZE_BYTES 643#define KX022A_FIFO_MAX_BYTES \44 (KX022A_FIFO_LENGTH * KX022A_FIFO_SAMPLES_SIZE_BYTES)45 46enum {47 KX022A_STATE_SAMPLE,48 KX022A_STATE_FIFO,49};50 51/* kx022a Regmap configs */52static const struct regmap_range kx022a_volatile_ranges[] = {53 {54 .range_min = KX022A_REG_XHP_L,55 .range_max = KX022A_REG_COTR,56 }, {57 .range_min = KX022A_REG_TSCP,58 .range_max = KX022A_REG_INT_REL,59 }, {60 /* The reset bit will be cleared by sensor */61 .range_min = KX022A_REG_CNTL2,62 .range_max = KX022A_REG_CNTL2,63 }, {64 .range_min = KX022A_REG_BUF_STATUS_1,65 .range_max = KX022A_REG_BUF_READ,66 },67};68 69static const struct regmap_access_table kx022a_volatile_regs = {70 .yes_ranges = &kx022a_volatile_ranges[0],71 .n_yes_ranges = ARRAY_SIZE(kx022a_volatile_ranges),72};73 74static const struct regmap_range kx022a_precious_ranges[] = {75 {76 .range_min = KX022A_REG_INT_REL,77 .range_max = KX022A_REG_INT_REL,78 },79};80 81static const struct regmap_access_table kx022a_precious_regs = {82 .yes_ranges = &kx022a_precious_ranges[0],83 .n_yes_ranges = ARRAY_SIZE(kx022a_precious_ranges),84};85 86/*87 * The HW does not set WHO_AM_I reg as read-only but we don't want to write it88 * so we still include it in the read-only ranges.89 */90static const struct regmap_range kx022a_read_only_ranges[] = {91 {92 .range_min = KX022A_REG_XHP_L,93 .range_max = KX022A_REG_INT_REL,94 }, {95 .range_min = KX022A_REG_BUF_STATUS_1,96 .range_max = KX022A_REG_BUF_STATUS_2,97 }, {98 .range_min = KX022A_REG_BUF_READ,99 .range_max = KX022A_REG_BUF_READ,100 },101};102 103static const struct regmap_access_table kx022a_ro_regs = {104 .no_ranges = &kx022a_read_only_ranges[0],105 .n_no_ranges = ARRAY_SIZE(kx022a_read_only_ranges),106};107 108static const struct regmap_range kx022a_write_only_ranges[] = {109 {110 .range_min = KX022A_REG_BTS_WUF_TH,111 .range_max = KX022A_REG_BTS_WUF_TH,112 }, {113 .range_min = KX022A_REG_MAN_WAKE,114 .range_max = KX022A_REG_MAN_WAKE,115 }, {116 .range_min = KX022A_REG_SELF_TEST,117 .range_max = KX022A_REG_SELF_TEST,118 }, {119 .range_min = KX022A_REG_BUF_CLEAR,120 .range_max = KX022A_REG_BUF_CLEAR,121 },122};123 124static const struct regmap_access_table kx022a_wo_regs = {125 .no_ranges = &kx022a_write_only_ranges[0],126 .n_no_ranges = ARRAY_SIZE(kx022a_write_only_ranges),127};128 129static const struct regmap_range kx022a_noinc_read_ranges[] = {130 {131 .range_min = KX022A_REG_BUF_READ,132 .range_max = KX022A_REG_BUF_READ,133 },134};135 136static const struct regmap_access_table kx022a_nir_regs = {137 .yes_ranges = &kx022a_noinc_read_ranges[0],138 .n_yes_ranges = ARRAY_SIZE(kx022a_noinc_read_ranges),139};140 141static const struct regmap_config kx022a_regmap_config = {142 .reg_bits = 8,143 .val_bits = 8,144 .volatile_table = &kx022a_volatile_regs,145 .rd_table = &kx022a_wo_regs,146 .wr_table = &kx022a_ro_regs,147 .rd_noinc_table = &kx022a_nir_regs,148 .precious_table = &kx022a_precious_regs,149 .max_register = KX022A_MAX_REGISTER,150 .cache_type = REGCACHE_RBTREE,151};152 153/* Regmap configs kx132 */154static const struct regmap_range kx132_volatile_ranges[] = {155 {156 .range_min = KX132_REG_XADP_L,157 .range_max = KX132_REG_COTR,158 }, {159 .range_min = KX132_REG_TSCP,160 .range_max = KX132_REG_INT_REL,161 }, {162 /* The reset bit will be cleared by sensor */163 .range_min = KX132_REG_CNTL2,164 .range_max = KX132_REG_CNTL2,165 }, {166 .range_min = KX132_REG_CNTL5,167 .range_max = KX132_REG_CNTL5,168 }, {169 .range_min = KX132_REG_BUF_STATUS_1,170 .range_max = KX132_REG_BUF_READ,171 },172};173 174static const struct regmap_access_table kx132_volatile_regs = {175 .yes_ranges = &kx132_volatile_ranges[0],176 .n_yes_ranges = ARRAY_SIZE(kx132_volatile_ranges),177};178 179static const struct regmap_range kx132_precious_ranges[] = {180 {181 .range_min = KX132_REG_INT_REL,182 .range_max = KX132_REG_INT_REL,183 },184};185 186static const struct regmap_access_table kx132_precious_regs = {187 .yes_ranges = &kx132_precious_ranges[0],188 .n_yes_ranges = ARRAY_SIZE(kx132_precious_ranges),189};190 191static const struct regmap_range kx132_read_only_ranges[] = {192 {193 .range_min = KX132_REG_XADP_L,194 .range_max = KX132_REG_INT_REL,195 }, {196 .range_min = KX132_REG_BUF_STATUS_1,197 .range_max = KX132_REG_BUF_STATUS_2,198 }, {199 .range_min = KX132_REG_BUF_READ,200 .range_max = KX132_REG_BUF_READ,201 }, {202 /* Kionix reserved registers: should not be written */203 .range_min = 0x28,204 .range_max = 0x28,205 }, {206 .range_min = 0x35,207 .range_max = 0x36,208 }, {209 .range_min = 0x3c,210 .range_max = 0x48,211 }, {212 .range_min = 0x4e,213 .range_max = 0x5c,214 }, {215 .range_min = 0x77,216 .range_max = 0x7f,217 },218};219 220static const struct regmap_access_table kx132_ro_regs = {221 .no_ranges = &kx132_read_only_ranges[0],222 .n_no_ranges = ARRAY_SIZE(kx132_read_only_ranges),223};224 225static const struct regmap_range kx132_write_only_ranges[] = {226 {227 .range_min = KX132_REG_SELF_TEST,228 .range_max = KX132_REG_SELF_TEST,229 }, {230 .range_min = KX132_REG_BUF_CLEAR,231 .range_max = KX132_REG_BUF_CLEAR,232 },233};234 235static const struct regmap_access_table kx132_wo_regs = {236 .no_ranges = &kx132_write_only_ranges[0],237 .n_no_ranges = ARRAY_SIZE(kx132_write_only_ranges),238};239 240static const struct regmap_range kx132_noinc_read_ranges[] = {241 {242 .range_min = KX132_REG_BUF_READ,243 .range_max = KX132_REG_BUF_READ,244 },245};246 247static const struct regmap_access_table kx132_nir_regs = {248 .yes_ranges = &kx132_noinc_read_ranges[0],249 .n_yes_ranges = ARRAY_SIZE(kx132_noinc_read_ranges),250};251 252static const struct regmap_config kx132_regmap_config = {253 .reg_bits = 8,254 .val_bits = 8,255 .volatile_table = &kx132_volatile_regs,256 .rd_table = &kx132_wo_regs,257 .wr_table = &kx132_ro_regs,258 .rd_noinc_table = &kx132_nir_regs,259 .precious_table = &kx132_precious_regs,260 .max_register = KX132_MAX_REGISTER,261 .cache_type = REGCACHE_RBTREE,262};263 264struct kx022a_data {265 struct regmap *regmap;266 const struct kx022a_chip_info *chip_info;267 struct iio_trigger *trig;268 struct device *dev;269 struct iio_mount_matrix orientation;270 int64_t timestamp, old_timestamp;271 272 int irq;273 int inc_reg;274 int ien_reg;275 276 unsigned int state;277 unsigned int odr_ns;278 279 bool trigger_enabled;280 /*281 * Prevent toggling the sensor stby/active state (PC1 bit) in the282 * middle of a configuration, or when the fifo is enabled. Also,283 * protect the data stored/retrieved from this structure from284 * concurrent accesses.285 */286 struct mutex mutex;287 u8 watermark;288 289 __le16 *fifo_buffer;290 291 /* 3 x 16bit accel data + timestamp */292 __le16 buffer[8] __aligned(IIO_DMA_MINALIGN);293 struct {294 __le16 channels[3];295 s64 ts __aligned(8);296 } scan;297};298 299static const struct iio_mount_matrix *300kx022a_get_mount_matrix(const struct iio_dev *idev,301 const struct iio_chan_spec *chan)302{303 struct kx022a_data *data = iio_priv(idev);304 305 return &data->orientation;306}307 308enum {309 AXIS_X,310 AXIS_Y,311 AXIS_Z,312 AXIS_MAX313};314 315static const unsigned long kx022a_scan_masks[] = {316 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 0317};318 319static const struct iio_chan_spec_ext_info kx022a_ext_info[] = {320 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kx022a_get_mount_matrix),321 { }322};323 324#define KX022A_ACCEL_CHAN(axis, reg, index) \325{ \326 .type = IIO_ACCEL, \327 .modified = 1, \328 .channel2 = IIO_MOD_##axis, \329 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \330 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \331 BIT(IIO_CHAN_INFO_SAMP_FREQ), \332 .info_mask_shared_by_type_available = \333 BIT(IIO_CHAN_INFO_SCALE) | \334 BIT(IIO_CHAN_INFO_SAMP_FREQ), \335 .ext_info = kx022a_ext_info, \336 .address = reg, \337 .scan_index = index, \338 .scan_type = { \339 .sign = 's', \340 .realbits = 16, \341 .storagebits = 16, \342 .endianness = IIO_LE, \343 }, \344}345 346static const struct iio_chan_spec kx022a_channels[] = {347 KX022A_ACCEL_CHAN(X, KX022A_REG_XOUT_L, 0),348 KX022A_ACCEL_CHAN(Y, KX022A_REG_YOUT_L, 1),349 KX022A_ACCEL_CHAN(Z, KX022A_REG_ZOUT_L, 2),350 IIO_CHAN_SOFT_TIMESTAMP(3),351};352 353static const struct iio_chan_spec kx132_channels[] = {354 KX022A_ACCEL_CHAN(X, KX132_REG_XOUT_L, 0),355 KX022A_ACCEL_CHAN(Y, KX132_REG_YOUT_L, 1),356 KX022A_ACCEL_CHAN(Z, KX132_REG_ZOUT_L, 2),357 IIO_CHAN_SOFT_TIMESTAMP(3),358};359 360/*361 * The sensor HW can support ODR up to 1600 Hz, which is beyond what most of the362 * Linux CPUs can handle without dropping samples. Also, the low power mode is363 * not available for higher sample rates. Thus, the driver only supports 200 Hz364 * and slower ODRs. The slowest is 0.78 Hz.365 */366static const int kx022a_accel_samp_freq_table[][2] = {367 { 0, 780000 },368 { 1, 563000 },369 { 3, 125000 },370 { 6, 250000 },371 { 12, 500000 },372 { 25, 0 },373 { 50, 0 },374 { 100, 0 },375 { 200, 0 },376};377 378static const unsigned int kx022a_odrs[] = {379 1282051282,380 639795266,381 320 * MEGA,382 160 * MEGA,383 80 * MEGA,384 40 * MEGA,385 20 * MEGA,386 10 * MEGA,387 5 * MEGA,388};389 390/*391 * range is typically +-2G/4G/8G/16G, distributed over the amount of bits.392 * The scale table can be calculated using393 * (range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2394 * => KX022A uses 16 bit (HiRes mode - assume the low 8 bits are zeroed395 * in low-power mode(?) )396 * => +/-2G => 4 / 2^16 * 9,80665397 * => +/-2G - 0.000598550415398 * +/-4G - 0.00119710083399 * +/-8G - 0.00239420166400 * +/-16G - 0.00478840332401 */402static const int kx022a_scale_table[][2] = {403 { 0, 598550 },404 { 0, 1197101 },405 { 0, 2394202 },406 { 0, 4788403 },407};408 409static int kx022a_read_avail(struct iio_dev *indio_dev,410 struct iio_chan_spec const *chan,411 const int **vals, int *type, int *length,412 long mask)413{414 switch (mask) {415 case IIO_CHAN_INFO_SAMP_FREQ:416 *vals = (const int *)kx022a_accel_samp_freq_table;417 *length = ARRAY_SIZE(kx022a_accel_samp_freq_table) *418 ARRAY_SIZE(kx022a_accel_samp_freq_table[0]);419 *type = IIO_VAL_INT_PLUS_MICRO;420 return IIO_AVAIL_LIST;421 case IIO_CHAN_INFO_SCALE:422 *vals = (const int *)kx022a_scale_table;423 *length = ARRAY_SIZE(kx022a_scale_table) *424 ARRAY_SIZE(kx022a_scale_table[0]);425 *type = IIO_VAL_INT_PLUS_NANO;426 return IIO_AVAIL_LIST;427 default:428 return -EINVAL;429 }430}431 432#define KX022A_DEFAULT_PERIOD_NS (20 * NSEC_PER_MSEC)433 434static void kx022a_reg2freq(unsigned int val, int *val1, int *val2)435{436 *val1 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][0];437 *val2 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][1];438}439 440static void kx022a_reg2scale(unsigned int val, unsigned int *val1,441 unsigned int *val2)442{443 val &= KX022A_MASK_GSEL;444 val >>= KX022A_GSEL_SHIFT;445 446 *val1 = kx022a_scale_table[val][0];447 *val2 = kx022a_scale_table[val][1];448}449 450static int kx022a_turn_on_off_unlocked(struct kx022a_data *data, bool on)451{452 int ret;453 454 if (on)455 ret = regmap_set_bits(data->regmap, data->chip_info->cntl,456 KX022A_MASK_PC1);457 else458 ret = regmap_clear_bits(data->regmap, data->chip_info->cntl,459 KX022A_MASK_PC1);460 if (ret)461 dev_err(data->dev, "Turn %s fail %d\n", str_on_off(on), ret);462 463 return ret;464}465 466static int kx022a_turn_off_lock(struct kx022a_data *data)467{468 int ret;469 470 mutex_lock(&data->mutex);471 ret = kx022a_turn_on_off_unlocked(data, false);472 if (ret)473 mutex_unlock(&data->mutex);474 475 return ret;476}477 478static int kx022a_turn_on_unlock(struct kx022a_data *data)479{480 int ret;481 482 ret = kx022a_turn_on_off_unlocked(data, true);483 mutex_unlock(&data->mutex);484 485 return ret;486}487 488static int kx022a_write_raw_get_fmt(struct iio_dev *idev,489 struct iio_chan_spec const *chan,490 long mask)491{492 switch (mask) {493 case IIO_CHAN_INFO_SCALE:494 return IIO_VAL_INT_PLUS_NANO;495 case IIO_CHAN_INFO_SAMP_FREQ:496 return IIO_VAL_INT_PLUS_MICRO;497 default:498 return -EINVAL;499 }500}501 502static int kx022a_write_raw(struct iio_dev *idev,503 struct iio_chan_spec const *chan,504 int val, int val2, long mask)505{506 struct kx022a_data *data = iio_priv(idev);507 int ret, n;508 509 /*510 * We should not allow changing scale or frequency when FIFO is running511 * as it will mess the timestamp/scale for samples existing in the512 * buffer. If this turns out to be an issue we can later change logic513 * to internally flush the fifo before reconfiguring so the samples in514 * fifo keep matching the freq/scale settings. (Such setup could cause515 * issues if users trust the watermark to be reached within known516 * time-limit).517 */518 ret = iio_device_claim_direct_mode(idev);519 if (ret)520 return ret;521 522 switch (mask) {523 case IIO_CHAN_INFO_SAMP_FREQ:524 n = ARRAY_SIZE(kx022a_accel_samp_freq_table);525 526 while (n--)527 if (val == kx022a_accel_samp_freq_table[n][0] &&528 val2 == kx022a_accel_samp_freq_table[n][1])529 break;530 if (n < 0) {531 ret = -EINVAL;532 goto unlock_out;533 }534 ret = kx022a_turn_off_lock(data);535 if (ret)536 break;537 538 ret = regmap_update_bits(data->regmap,539 data->chip_info->odcntl,540 KX022A_MASK_ODR, n);541 data->odr_ns = kx022a_odrs[n];542 kx022a_turn_on_unlock(data);543 break;544 case IIO_CHAN_INFO_SCALE:545 n = ARRAY_SIZE(kx022a_scale_table);546 547 while (n-- > 0)548 if (val == kx022a_scale_table[n][0] &&549 val2 == kx022a_scale_table[n][1])550 break;551 if (n < 0) {552 ret = -EINVAL;553 goto unlock_out;554 }555 556 ret = kx022a_turn_off_lock(data);557 if (ret)558 break;559 560 ret = regmap_update_bits(data->regmap, data->chip_info->cntl,561 KX022A_MASK_GSEL,562 n << KX022A_GSEL_SHIFT);563 kx022a_turn_on_unlock(data);564 break;565 default:566 ret = -EINVAL;567 break;568 }569 570unlock_out:571 iio_device_release_direct_mode(idev);572 573 return ret;574}575 576static int kx022a_fifo_set_wmi(struct kx022a_data *data)577{578 u8 threshold;579 580 threshold = data->watermark;581 582 return regmap_update_bits(data->regmap, data->chip_info->buf_cntl1,583 KX022A_MASK_WM_TH, threshold);584}585 586static int kx022a_get_axis(struct kx022a_data *data,587 struct iio_chan_spec const *chan,588 int *val)589{590 int ret;591 592 ret = regmap_bulk_read(data->regmap, chan->address, &data->buffer[0],593 sizeof(__le16));594 if (ret)595 return ret;596 597 *val = le16_to_cpu(data->buffer[0]);598 599 return IIO_VAL_INT;600}601 602static int kx022a_read_raw(struct iio_dev *idev,603 struct iio_chan_spec const *chan,604 int *val, int *val2, long mask)605{606 struct kx022a_data *data = iio_priv(idev);607 unsigned int regval;608 int ret;609 610 switch (mask) {611 case IIO_CHAN_INFO_RAW:612 ret = iio_device_claim_direct_mode(idev);613 if (ret)614 return ret;615 616 mutex_lock(&data->mutex);617 ret = kx022a_get_axis(data, chan, val);618 mutex_unlock(&data->mutex);619 620 iio_device_release_direct_mode(idev);621 622 return ret;623 624 case IIO_CHAN_INFO_SAMP_FREQ:625 ret = regmap_read(data->regmap, data->chip_info->odcntl, ®val);626 if (ret)627 return ret;628 629 if ((regval & KX022A_MASK_ODR) >630 ARRAY_SIZE(kx022a_accel_samp_freq_table)) {631 dev_err(data->dev, "Invalid ODR\n");632 return -EINVAL;633 }634 635 kx022a_reg2freq(regval, val, val2);636 637 return IIO_VAL_INT_PLUS_MICRO;638 639 case IIO_CHAN_INFO_SCALE:640 ret = regmap_read(data->regmap, data->chip_info->cntl, ®val);641 if (ret < 0)642 return ret;643 644 kx022a_reg2scale(regval, val, val2);645 646 return IIO_VAL_INT_PLUS_NANO;647 }648 649 return -EINVAL;650};651 652static int kx022a_set_watermark(struct iio_dev *idev, unsigned int val)653{654 struct kx022a_data *data = iio_priv(idev);655 656 val = min(data->chip_info->fifo_length, val);657 658 mutex_lock(&data->mutex);659 data->watermark = val;660 mutex_unlock(&data->mutex);661 662 return 0;663}664 665static ssize_t hwfifo_enabled_show(struct device *dev,666 struct device_attribute *attr,667 char *buf)668{669 struct iio_dev *idev = dev_to_iio_dev(dev);670 struct kx022a_data *data = iio_priv(idev);671 bool state;672 673 mutex_lock(&data->mutex);674 state = data->state;675 mutex_unlock(&data->mutex);676 677 return sysfs_emit(buf, "%d\n", state);678}679 680static ssize_t hwfifo_watermark_show(struct device *dev,681 struct device_attribute *attr,682 char *buf)683{684 struct iio_dev *idev = dev_to_iio_dev(dev);685 struct kx022a_data *data = iio_priv(idev);686 int wm;687 688 mutex_lock(&data->mutex);689 wm = data->watermark;690 mutex_unlock(&data->mutex);691 692 return sysfs_emit(buf, "%d\n", wm);693}694 695static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0);696static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0);697 698static const struct iio_dev_attr *kx022a_fifo_attributes[] = {699 &iio_dev_attr_hwfifo_watermark,700 &iio_dev_attr_hwfifo_enabled,701 NULL702};703 704static int kx022a_drop_fifo_contents(struct kx022a_data *data)705{706 /*707 * We must clear the old time-stamp to avoid computing the timestamps708 * based on samples acquired when buffer was last enabled.709 *710 * We don't need to protect the timestamp as long as we are only711 * called from fifo-disable where we can guarantee the sensor is not712 * triggering interrupts and where the mutex is locked to prevent the713 * user-space access.714 */715 data->timestamp = 0;716 717 return regmap_write(data->regmap, data->chip_info->buf_clear, 0x0);718}719 720static int kx022a_get_fifo_bytes_available(struct kx022a_data *data)721{722 int ret, fifo_bytes;723 724 ret = regmap_read(data->regmap, KX022A_REG_BUF_STATUS_1, &fifo_bytes);725 if (ret) {726 dev_err(data->dev, "Error reading buffer status\n");727 return ret;728 }729 730 if (fifo_bytes == KX022A_FIFO_FULL_VALUE)731 return KX022A_FIFO_MAX_BYTES;732 733 return fifo_bytes;734}735 736static int kx132_get_fifo_bytes_available(struct kx022a_data *data)737{738 __le16 buf_status;739 int ret, fifo_bytes;740 741 ret = regmap_bulk_read(data->regmap, data->chip_info->buf_status1,742 &buf_status, sizeof(buf_status));743 if (ret) {744 dev_err(data->dev, "Error reading buffer status\n");745 return ret;746 }747 748 fifo_bytes = le16_to_cpu(buf_status);749 fifo_bytes &= data->chip_info->buf_smp_lvl_mask;750 fifo_bytes = min((unsigned int)fifo_bytes, data->chip_info->fifo_length *751 KX022A_FIFO_SAMPLES_SIZE_BYTES);752 753 return fifo_bytes;754}755 756static int __kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples,757 bool irq)758{759 struct kx022a_data *data = iio_priv(idev);760 uint64_t sample_period;761 int count, fifo_bytes;762 bool renable = false;763 int64_t tstamp;764 int ret, i;765 766 fifo_bytes = data->chip_info->get_fifo_bytes_available(data);767 768 if (fifo_bytes % KX022A_FIFO_SAMPLES_SIZE_BYTES)769 dev_warn(data->dev, "Bad FIFO alignment. Data may be corrupt\n");770 771 count = fifo_bytes / KX022A_FIFO_SAMPLES_SIZE_BYTES;772 if (!count)773 return 0;774 775 /*776 * If we are being called from IRQ handler we know the stored timestamp777 * is fairly accurate for the last stored sample. Otherwise, if we are778 * called as a result of a read operation from userspace and hence779 * before the watermark interrupt was triggered, take a timestamp780 * now. We can fall anywhere in between two samples so the error in this781 * case is at most one sample period.782 */783 if (!irq) {784 /*785 * We need to have the IRQ disabled or we risk of messing-up786 * the timestamps. If we are ran from IRQ, then the787 * IRQF_ONESHOT has us covered - but if we are ran by the788 * user-space read we need to disable the IRQ to be on a safe789 * side. We do this usng synchronous disable so that if the790 * IRQ thread is being ran on other CPU we wait for it to be791 * finished.792 */793 disable_irq(data->irq);794 renable = true;795 796 data->old_timestamp = data->timestamp;797 data->timestamp = iio_get_time_ns(idev);798 }799 800 /*801 * Approximate timestamps for each of the sample based on the sampling802 * frequency, timestamp for last sample and number of samples.803 *804 * We'd better not use the current bandwidth settings to compute the805 * sample period. The real sample rate varies with the device and806 * small variation adds when we store a large number of samples.807 *808 * To avoid this issue we compute the actual sample period ourselves809 * based on the timestamp delta between the last two flush operations.810 */811 if (data->old_timestamp) {812 sample_period = data->timestamp - data->old_timestamp;813 do_div(sample_period, count);814 } else {815 sample_period = data->odr_ns;816 }817 tstamp = data->timestamp - (count - 1) * sample_period;818 819 if (samples && count > samples) {820 /*821 * Here we leave some old samples to the buffer. We need to822 * adjust the timestamp to match the first sample in the buffer823 * or we will miscalculate the sample_period at next round.824 */825 data->timestamp -= (count - samples) * sample_period;826 count = samples;827 }828 829 fifo_bytes = count * KX022A_FIFO_SAMPLES_SIZE_BYTES;830 ret = regmap_noinc_read(data->regmap, data->chip_info->buf_read,831 data->fifo_buffer, fifo_bytes);832 if (ret)833 goto renable_out;834 835 for (i = 0; i < count; i++) {836 __le16 *sam = &data->fifo_buffer[i * 3];837 __le16 *chs;838 int bit;839 840 chs = &data->scan.channels[0];841 for_each_set_bit(bit, idev->active_scan_mask, AXIS_MAX)842 chs[bit] = sam[bit];843 844 iio_push_to_buffers_with_timestamp(idev, &data->scan, tstamp);845 846 tstamp += sample_period;847 }848 849 ret = count;850 851renable_out:852 if (renable)853 enable_irq(data->irq);854 855 return ret;856}857 858static int kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples)859{860 struct kx022a_data *data = iio_priv(idev);861 int ret;862 863 mutex_lock(&data->mutex);864 ret = __kx022a_fifo_flush(idev, samples, false);865 mutex_unlock(&data->mutex);866 867 return ret;868}869 870static const struct iio_info kx022a_info = {871 .read_raw = &kx022a_read_raw,872 .write_raw = &kx022a_write_raw,873 .write_raw_get_fmt = &kx022a_write_raw_get_fmt,874 .read_avail = &kx022a_read_avail,875 876 .validate_trigger = iio_validate_own_trigger,877 .hwfifo_set_watermark = kx022a_set_watermark,878 .hwfifo_flush_to_buffer = kx022a_fifo_flush,879};880 881static int kx022a_set_drdy_irq(struct kx022a_data *data, bool en)882{883 if (en)884 return regmap_set_bits(data->regmap, data->chip_info->cntl,885 KX022A_MASK_DRDY);886 887 return regmap_clear_bits(data->regmap, data->chip_info->cntl,888 KX022A_MASK_DRDY);889}890 891static int kx022a_prepare_irq_pin(struct kx022a_data *data)892{893 /* Enable IRQ1 pin. Set polarity to active low */894 int mask = KX022A_MASK_IEN | KX022A_MASK_IPOL |895 KX022A_MASK_ITYP;896 int val = KX022A_MASK_IEN | KX022A_IPOL_LOW |897 KX022A_ITYP_LEVEL;898 int ret;899 900 ret = regmap_update_bits(data->regmap, data->inc_reg, mask, val);901 if (ret)902 return ret;903 904 /* We enable WMI to IRQ pin only at buffer_enable */905 mask = KX022A_MASK_INS2_DRDY;906 907 return regmap_set_bits(data->regmap, data->ien_reg, mask);908}909 910static int kx022a_fifo_disable(struct kx022a_data *data)911{912 int ret = 0;913 914 ret = kx022a_turn_off_lock(data);915 if (ret)916 return ret;917 918 ret = regmap_clear_bits(data->regmap, data->ien_reg, KX022A_MASK_WMI);919 if (ret)920 goto unlock_out;921 922 ret = regmap_clear_bits(data->regmap, data->chip_info->buf_cntl2,923 KX022A_MASK_BUF_EN);924 if (ret)925 goto unlock_out;926 927 data->state &= ~KX022A_STATE_FIFO;928 929 kx022a_drop_fifo_contents(data);930 931 kfree(data->fifo_buffer);932 933 return kx022a_turn_on_unlock(data);934 935unlock_out:936 mutex_unlock(&data->mutex);937 938 return ret;939}940 941static int kx022a_buffer_predisable(struct iio_dev *idev)942{943 struct kx022a_data *data = iio_priv(idev);944 945 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED)946 return 0;947 948 return kx022a_fifo_disable(data);949}950 951static int kx022a_fifo_enable(struct kx022a_data *data)952{953 int ret;954 955 data->fifo_buffer = kmalloc_array(data->chip_info->fifo_length,956 KX022A_FIFO_SAMPLES_SIZE_BYTES,957 GFP_KERNEL);958 if (!data->fifo_buffer)959 return -ENOMEM;960 961 ret = kx022a_turn_off_lock(data);962 if (ret)963 return ret;964 965 /* Update watermark to HW */966 ret = kx022a_fifo_set_wmi(data);967 if (ret)968 goto unlock_out;969 970 /* Enable buffer */971 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2,972 KX022A_MASK_BUF_EN);973 if (ret)974 goto unlock_out;975 976 data->state |= KX022A_STATE_FIFO;977 ret = regmap_set_bits(data->regmap, data->ien_reg,978 KX022A_MASK_WMI);979 if (ret)980 goto unlock_out;981 982 return kx022a_turn_on_unlock(data);983 984unlock_out:985 mutex_unlock(&data->mutex);986 987 return ret;988}989 990static int kx022a_buffer_postenable(struct iio_dev *idev)991{992 struct kx022a_data *data = iio_priv(idev);993 994 /*995 * If we use data-ready trigger, then the IRQ masks should be handled by996 * trigger enable and the hardware buffer is not used but we just update997 * results to the IIO fifo when data-ready triggers.998 */999 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED)1000 return 0;1001 1002 return kx022a_fifo_enable(data);1003}1004 1005static const struct iio_buffer_setup_ops kx022a_buffer_ops = {1006 .postenable = kx022a_buffer_postenable,1007 .predisable = kx022a_buffer_predisable,1008};1009 1010static irqreturn_t kx022a_trigger_handler(int irq, void *p)1011{1012 struct iio_poll_func *pf = p;1013 struct iio_dev *idev = pf->indio_dev;1014 struct kx022a_data *data = iio_priv(idev);1015 int ret;1016 1017 ret = regmap_bulk_read(data->regmap, data->chip_info->xout_l, data->buffer,1018 KX022A_FIFO_SAMPLES_SIZE_BYTES);1019 if (ret < 0)1020 goto err_read;1021 1022 iio_push_to_buffers_with_timestamp(idev, data->buffer, data->timestamp);1023err_read:1024 iio_trigger_notify_done(idev->trig);1025 1026 return IRQ_HANDLED;1027}1028 1029/* Get timestamps and wake the thread if we need to read data */1030static irqreturn_t kx022a_irq_handler(int irq, void *private)1031{1032 struct iio_dev *idev = private;1033 struct kx022a_data *data = iio_priv(idev);1034 1035 data->old_timestamp = data->timestamp;1036 data->timestamp = iio_get_time_ns(idev);1037 1038 if (data->state & KX022A_STATE_FIFO || data->trigger_enabled)1039 return IRQ_WAKE_THREAD;1040 1041 return IRQ_NONE;1042}1043 1044/*1045 * WMI and data-ready IRQs are acked when results are read. If we add1046 * TILT/WAKE or other IRQs - then we may need to implement the acking1047 * (which is racy).1048 */1049static irqreturn_t kx022a_irq_thread_handler(int irq, void *private)1050{1051 struct iio_dev *idev = private;1052 struct kx022a_data *data = iio_priv(idev);1053 irqreturn_t ret = IRQ_NONE;1054 1055 mutex_lock(&data->mutex);1056 1057 if (data->trigger_enabled) {1058 iio_trigger_poll_nested(data->trig);1059 ret = IRQ_HANDLED;1060 }1061 1062 if (data->state & KX022A_STATE_FIFO) {1063 int ok;1064 1065 ok = __kx022a_fifo_flush(idev, data->chip_info->fifo_length, true);1066 if (ok > 0)1067 ret = IRQ_HANDLED;1068 }1069 1070 mutex_unlock(&data->mutex);1071 1072 return ret;1073}1074 1075static int kx022a_trigger_set_state(struct iio_trigger *trig,1076 bool state)1077{1078 struct kx022a_data *data = iio_trigger_get_drvdata(trig);1079 int ret = 0;1080 1081 mutex_lock(&data->mutex);1082 1083 if (data->trigger_enabled == state)1084 goto unlock_out;1085 1086 if (data->state & KX022A_STATE_FIFO) {1087 dev_warn(data->dev, "Can't set trigger when FIFO enabled\n");1088 ret = -EBUSY;1089 goto unlock_out;1090 }1091 1092 ret = kx022a_turn_on_off_unlocked(data, false);1093 if (ret)1094 goto unlock_out;1095 1096 data->trigger_enabled = state;1097 ret = kx022a_set_drdy_irq(data, state);1098 if (ret)1099 goto unlock_out;1100 1101 ret = kx022a_turn_on_off_unlocked(data, true);1102 1103unlock_out:1104 mutex_unlock(&data->mutex);1105 1106 return ret;1107}1108 1109static const struct iio_trigger_ops kx022a_trigger_ops = {1110 .set_trigger_state = kx022a_trigger_set_state,1111};1112 1113static int kx022a_chip_init(struct kx022a_data *data)1114{1115 int ret, val;1116 1117 /* Reset the senor */1118 ret = regmap_write(data->regmap, data->chip_info->cntl2, KX022A_MASK_SRST);1119 if (ret)1120 return ret;1121 1122 /*1123 * I've seen I2C read failures if we poll too fast after the sensor1124 * reset. Slight delay gives I2C block the time to recover.1125 */1126 msleep(1);1127 1128 ret = regmap_read_poll_timeout(data->regmap, data->chip_info->cntl2, val,1129 !(val & KX022A_MASK_SRST),1130 KX022A_SOFT_RESET_WAIT_TIME_US,1131 KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US);1132 if (ret) {1133 dev_err(data->dev, "Sensor reset %s\n",1134 val & KX022A_MASK_SRST ? "timeout" : "fail#");1135 return ret;1136 }1137 1138 ret = regmap_reinit_cache(data->regmap, data->chip_info->regmap_config);1139 if (ret) {1140 dev_err(data->dev, "Failed to reinit reg cache\n");1141 return ret;1142 }1143 1144 /* set data res 16bit */1145 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2,1146 KX022A_MASK_BRES16);1147 if (ret) {1148 dev_err(data->dev, "Failed to set data resolution\n");1149 return ret;1150 }1151 1152 return kx022a_prepare_irq_pin(data);1153}1154 1155const struct kx022a_chip_info kx022a_chip_info = {1156 .name = "kx022-accel",1157 .regmap_config = &kx022a_regmap_config,1158 .channels = kx022a_channels,1159 .num_channels = ARRAY_SIZE(kx022a_channels),1160 .fifo_length = KX022A_FIFO_LENGTH,1161 .who = KX022A_REG_WHO,1162 .id = KX022A_ID,1163 .cntl = KX022A_REG_CNTL,1164 .cntl2 = KX022A_REG_CNTL2,1165 .odcntl = KX022A_REG_ODCNTL,1166 .buf_cntl1 = KX022A_REG_BUF_CNTL1,1167 .buf_cntl2 = KX022A_REG_BUF_CNTL2,1168 .buf_clear = KX022A_REG_BUF_CLEAR,1169 .buf_status1 = KX022A_REG_BUF_STATUS_1,1170 .buf_read = KX022A_REG_BUF_READ,1171 .inc1 = KX022A_REG_INC1,1172 .inc4 = KX022A_REG_INC4,1173 .inc5 = KX022A_REG_INC5,1174 .inc6 = KX022A_REG_INC6,1175 .xout_l = KX022A_REG_XOUT_L,1176 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available,1177};1178EXPORT_SYMBOL_NS_GPL(kx022a_chip_info, IIO_KX022A);1179 1180const struct kx022a_chip_info kx132_chip_info = {1181 .name = "kx132-1211",1182 .regmap_config = &kx132_regmap_config,1183 .channels = kx132_channels,1184 .num_channels = ARRAY_SIZE(kx132_channels),1185 .fifo_length = KX132_FIFO_LENGTH,1186 .who = KX132_REG_WHO,1187 .id = KX132_ID,1188 .cntl = KX132_REG_CNTL,1189 .cntl2 = KX132_REG_CNTL2,1190 .odcntl = KX132_REG_ODCNTL,1191 .buf_cntl1 = KX132_REG_BUF_CNTL1,1192 .buf_cntl2 = KX132_REG_BUF_CNTL2,1193 .buf_clear = KX132_REG_BUF_CLEAR,1194 .buf_status1 = KX132_REG_BUF_STATUS_1,1195 .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL,1196 .buf_read = KX132_REG_BUF_READ,1197 .inc1 = KX132_REG_INC1,1198 .inc4 = KX132_REG_INC4,1199 .inc5 = KX132_REG_INC5,1200 .inc6 = KX132_REG_INC6,1201 .xout_l = KX132_REG_XOUT_L,1202 .get_fifo_bytes_available = kx132_get_fifo_bytes_available,1203};1204EXPORT_SYMBOL_NS_GPL(kx132_chip_info, IIO_KX022A);1205 1206/*1207 * Despite the naming, KX132ACR-LBZ is not similar to KX132-1211 but it is1208 * exact subset of KX022A. KX132ACR-LBZ is meant to be used for industrial1209 * applications and the tap/double tap, free fall and tilt engines were1210 * removed. Rest of the registers and functionalities (excluding the ID1211 * register) are exact match to what is found in KX022.1212 */1213const struct kx022a_chip_info kx132acr_chip_info = {1214 .name = "kx132acr-lbz",1215 .regmap_config = &kx022a_regmap_config,1216 .channels = kx022a_channels,1217 .num_channels = ARRAY_SIZE(kx022a_channels),1218 .fifo_length = KX022A_FIFO_LENGTH,1219 .who = KX022A_REG_WHO,1220 .id = KX132ACR_LBZ_ID,1221 .cntl = KX022A_REG_CNTL,1222 .cntl2 = KX022A_REG_CNTL2,1223 .odcntl = KX022A_REG_ODCNTL,1224 .buf_cntl1 = KX022A_REG_BUF_CNTL1,1225 .buf_cntl2 = KX022A_REG_BUF_CNTL2,1226 .buf_clear = KX022A_REG_BUF_CLEAR,1227 .buf_status1 = KX022A_REG_BUF_STATUS_1,1228 .buf_read = KX022A_REG_BUF_READ,1229 .inc1 = KX022A_REG_INC1,1230 .inc4 = KX022A_REG_INC4,1231 .inc5 = KX022A_REG_INC5,1232 .inc6 = KX022A_REG_INC6,1233 .xout_l = KX022A_REG_XOUT_L,1234 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available,1235};1236EXPORT_SYMBOL_NS_GPL(kx132acr_chip_info, IIO_KX022A);1237 1238int kx022a_probe_internal(struct device *dev, const struct kx022a_chip_info *chip_info)1239{1240 static const char * const regulator_names[] = {"io-vdd", "vdd"};1241 struct iio_trigger *indio_trig;1242 struct fwnode_handle *fwnode;1243 struct kx022a_data *data;1244 struct regmap *regmap;1245 unsigned int chip_id;1246 struct iio_dev *idev;1247 int ret, irq;1248 char *name;1249 1250 regmap = dev_get_regmap(dev, NULL);1251 if (!regmap) {1252 dev_err(dev, "no regmap\n");1253 return -EINVAL;1254 }1255 1256 fwnode = dev_fwnode(dev);1257 if (!fwnode)1258 return -ENODEV;1259 1260 idev = devm_iio_device_alloc(dev, sizeof(*data));1261 if (!idev)1262 return -ENOMEM;1263 1264 data = iio_priv(idev);1265 data->chip_info = chip_info;1266 1267 /*1268 * VDD is the analog and digital domain voltage supply and1269 * IO_VDD is the digital I/O voltage supply.1270 */1271 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),1272 regulator_names);1273 if (ret && ret != -ENODEV)1274 return dev_err_probe(dev, ret, "failed to enable regulator\n");1275 1276 ret = regmap_read(regmap, chip_info->who, &chip_id);1277 if (ret)1278 return dev_err_probe(dev, ret, "Failed to access sensor\n");1279 1280 if (chip_id != chip_info->id)1281 dev_warn(dev, "unknown device 0x%x\n", chip_id);1282 1283 irq = fwnode_irq_get_byname(fwnode, "INT1");1284 if (irq > 0) {1285 data->inc_reg = chip_info->inc1;1286 data->ien_reg = chip_info->inc4;1287 } else {1288 irq = fwnode_irq_get_byname(fwnode, "INT2");1289 if (irq < 0)1290 return dev_err_probe(dev, irq, "No suitable IRQ\n");1291 1292 data->inc_reg = chip_info->inc5;1293 data->ien_reg = chip_info->inc6;1294 }1295 1296 data->regmap = regmap;1297 data->dev = dev;1298 data->irq = irq;1299 data->odr_ns = KX022A_DEFAULT_PERIOD_NS;1300 mutex_init(&data->mutex);1301 1302 idev->channels = chip_info->channels;1303 idev->num_channels = chip_info->num_channels;1304 idev->name = chip_info->name;1305 idev->info = &kx022a_info;1306 idev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;1307 idev->available_scan_masks = kx022a_scan_masks;1308 1309 /* Read the mounting matrix, if present */1310 ret = iio_read_mount_matrix(dev, &data->orientation);1311 if (ret)1312 return ret;1313 1314 /* The sensor must be turned off for configuration */1315 ret = kx022a_turn_off_lock(data);1316 if (ret)1317 return ret;1318 1319 ret = kx022a_chip_init(data);1320 if (ret) {1321 mutex_unlock(&data->mutex);1322 return ret;1323 }1324 1325 ret = kx022a_turn_on_unlock(data);1326 if (ret)1327 return ret;1328 1329 ret = devm_iio_triggered_buffer_setup_ext(dev, idev,1330 &iio_pollfunc_store_time,1331 kx022a_trigger_handler,1332 IIO_BUFFER_DIRECTION_IN,1333 &kx022a_buffer_ops,1334 kx022a_fifo_attributes);1335 1336 if (ret)1337 return dev_err_probe(data->dev, ret,1338 "iio_triggered_buffer_setup_ext FAIL\n");1339 indio_trig = devm_iio_trigger_alloc(dev, "%sdata-rdy-dev%d", idev->name,1340 iio_device_id(idev));1341 if (!indio_trig)1342 return -ENOMEM;1343 1344 data->trig = indio_trig;1345 1346 indio_trig->ops = &kx022a_trigger_ops;1347 iio_trigger_set_drvdata(indio_trig, data);1348 1349 /*1350 * No need to check for NULL. request_threaded_irq() defaults to1351 * dev_name() should the alloc fail.1352 */1353 name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-kx022a",1354 dev_name(data->dev));1355 1356 ret = devm_request_threaded_irq(data->dev, irq, kx022a_irq_handler,1357 &kx022a_irq_thread_handler,1358 IRQF_ONESHOT, name, idev);1359 if (ret)1360 return dev_err_probe(data->dev, ret, "Could not request IRQ\n");1361 1362 ret = devm_iio_trigger_register(dev, indio_trig);1363 if (ret)1364 return dev_err_probe(data->dev, ret,1365 "Trigger registration failed\n");1366 1367 ret = devm_iio_device_register(data->dev, idev);1368 if (ret < 0)1369 return dev_err_probe(dev, ret,1370 "Unable to register iio device\n");1371 1372 return ret;1373}1374EXPORT_SYMBOL_NS_GPL(kx022a_probe_internal, IIO_KX022A);1375 1376MODULE_DESCRIPTION("ROHM/Kionix KX022A accelerometer driver");1377MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");1378MODULE_LICENSE("GPL");1379