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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * SPI ADC driver for Analog Devices Inc. AD4695 and similar chips4 *5 * https://www.analog.com/en/products/ad4695.html6 * https://www.analog.com/en/products/ad4696.html7 * https://www.analog.com/en/products/ad4697.html8 * https://www.analog.com/en/products/ad4698.html9 *10 * Copyright 2024 Analog Devices Inc.11 * Copyright 2024 BayLibre, SAS12 */13 14#include <linux/align.h>15#include <linux/bitfield.h>16#include <linux/bits.h>17#include <linux/compiler.h>18#include <linux/delay.h>19#include <linux/device.h>20#include <linux/err.h>21#include <linux/gpio/consumer.h>22#include <linux/iio/buffer.h>23#include <linux/iio/iio.h>24#include <linux/iio/triggered_buffer.h>25#include <linux/iio/trigger_consumer.h>26#include <linux/minmax.h>27#include <linux/property.h>28#include <linux/regmap.h>29#include <linux/regulator/consumer.h>30#include <linux/spi/spi.h>31#include <linux/units.h>32 33#include <dt-bindings/iio/adi,ad4695.h>34 35/* AD4695 registers */36#define AD4695_REG_SPI_CONFIG_A 0x000037#define AD4695_REG_SPI_CONFIG_A_SW_RST (BIT(7) | BIT(0))38#define AD4695_REG_SPI_CONFIG_A_ADDR_DIR BIT(5)39#define AD4695_REG_SPI_CONFIG_B 0x000140#define AD4695_REG_SPI_CONFIG_B_INST_MODE BIT(7)41#define AD4695_REG_DEVICE_TYPE 0x000342#define AD4695_REG_SCRATCH_PAD 0x000A43#define AD4695_REG_VENDOR_L 0x000C44#define AD4695_REG_VENDOR_H 0x000D45#define AD4695_REG_LOOP_MODE 0x000E46#define AD4695_REG_SPI_CONFIG_C 0x001047#define AD4695_REG_SPI_CONFIG_C_MB_STRICT BIT(7)48#define AD4695_REG_SPI_STATUS 0x001149#define AD4695_REG_STATUS 0x001450#define AD4695_REG_ALERT_STATUS1 0x001551#define AD4695_REG_ALERT_STATUS2 0x001652#define AD4695_REG_CLAMP_STATUS 0x001A53#define AD4695_REG_SETUP 0x002054#define AD4695_REG_SETUP_LDO_EN BIT(4)55#define AD4695_REG_SETUP_SPI_MODE BIT(2)56#define AD4695_REG_SETUP_SPI_CYC_CTRL BIT(1)57#define AD4695_REG_REF_CTRL 0x002158#define AD4695_REG_REF_CTRL_OV_MODE BIT(7)59#define AD4695_REG_REF_CTRL_VREF_SET GENMASK(4, 2)60#define AD4695_REG_REF_CTRL_REFHIZ_EN BIT(1)61#define AD4695_REG_REF_CTRL_REFBUF_EN BIT(0)62#define AD4695_REG_SEQ_CTRL 0x002263#define AD4695_REG_SEQ_CTRL_STD_SEQ_EN BIT(7)64#define AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS GENMASK(6, 0)65#define AD4695_REG_AC_CTRL 0x002366#define AD4695_REG_STD_SEQ_CONFIG 0x002467#define AD4695_REG_GPIO_CTRL 0x002668#define AD4695_REG_GP_MODE 0x002769#define AD4695_REG_TEMP_CTRL 0x002970#define AD4695_REG_TEMP_CTRL_TEMP_EN BIT(0)71#define AD4695_REG_CONFIG_IN(n) (0x0030 | (n))72#define AD4695_REG_CONFIG_IN_MODE BIT(6)73#define AD4695_REG_CONFIG_IN_PAIR GENMASK(5, 4)74#define AD4695_REG_CONFIG_IN_AINHIGHZ_EN BIT(3)75#define AD4695_REG_UPPER_IN(n) (0x0040 | (2 * (n)))76#define AD4695_REG_LOWER_IN(n) (0x0060 | (2 * (n)))77#define AD4695_REG_HYST_IN(n) (0x0080 | (2 * (n)))78#define AD4695_REG_OFFSET_IN(n) (0x00A0 | (2 * (n)))79#define AD4695_REG_GAIN_IN(n) (0x00C0 | (2 * (n)))80#define AD4695_REG_AS_SLOT(n) (0x0100 | (n))81#define AD4695_REG_AS_SLOT_INX GENMASK(3, 0)82 83/* Conversion mode commands */84#define AD4695_CMD_EXIT_CNV_MODE 0x0A85#define AD4695_CMD_TEMP_CHAN 0x0F86#define AD4695_CMD_VOLTAGE_CHAN(n) (0x10 | (n))87 88/* timing specs */89#define AD4695_T_CONVERT_NS 41590#define AD4695_T_WAKEUP_HW_MS 391#define AD4695_T_WAKEUP_SW_MS 392#define AD4695_T_REFBUF_MS 10093#define AD4695_T_REGCONFIG_NS 2094#define AD4695_REG_ACCESS_SCLK_HZ (10 * MEGA)95 96/* Max number of voltage input channels. */97#define AD4695_MAX_CHANNELS 1698/* Max size of 1 raw sample in bytes. */99#define AD4695_MAX_CHANNEL_SIZE 2100 101enum ad4695_in_pair {102 AD4695_IN_PAIR_REFGND,103 AD4695_IN_PAIR_COM,104 AD4695_IN_PAIR_EVEN_ODD,105};106 107struct ad4695_chip_info {108 const char *name;109 int max_sample_rate;110 u32 t_acq_ns;111 u8 num_voltage_inputs;112};113 114struct ad4695_channel_config {115 unsigned int channel;116 bool highz_en;117 bool bipolar;118 enum ad4695_in_pair pin_pairing;119 unsigned int common_mode_mv;120};121 122struct ad4695_state {123 struct spi_device *spi;124 struct regmap *regmap;125 struct regmap *regmap16;126 struct gpio_desc *reset_gpio;127 /* voltages channels plus temperature and timestamp */128 struct iio_chan_spec iio_chan[AD4695_MAX_CHANNELS + 2];129 struct ad4695_channel_config channels_cfg[AD4695_MAX_CHANNELS];130 const struct ad4695_chip_info *chip_info;131 /* Reference voltage. */132 unsigned int vref_mv;133 /* Common mode input pin voltage. */134 unsigned int com_mv;135 /* 1 per voltage and temperature chan plus 1 xfer to trigger 1st CNV */136 struct spi_transfer buf_read_xfer[AD4695_MAX_CHANNELS + 2];137 struct spi_message buf_read_msg;138 /* Raw conversion data received. */139 u8 buf[ALIGN((AD4695_MAX_CHANNELS + 2) * AD4695_MAX_CHANNEL_SIZE,140 sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);141 u16 raw_data;142 /* Commands to send for single conversion. */143 u16 cnv_cmd;144 u8 cnv_cmd2;145};146 147static const struct regmap_range ad4695_regmap_rd_ranges[] = {148 regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B),149 regmap_reg_range(AD4695_REG_DEVICE_TYPE, AD4695_REG_DEVICE_TYPE),150 regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD),151 regmap_reg_range(AD4695_REG_VENDOR_L, AD4695_REG_LOOP_MODE),152 regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS),153 regmap_reg_range(AD4695_REG_STATUS, AD4695_REG_ALERT_STATUS2),154 regmap_reg_range(AD4695_REG_CLAMP_STATUS, AD4695_REG_CLAMP_STATUS),155 regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL),156 regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL),157 regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)),158 regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)),159};160 161static const struct regmap_access_table ad4695_regmap_rd_table = {162 .yes_ranges = ad4695_regmap_rd_ranges,163 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap_rd_ranges),164};165 166static const struct regmap_range ad4695_regmap_wr_ranges[] = {167 regmap_reg_range(AD4695_REG_SPI_CONFIG_A, AD4695_REG_SPI_CONFIG_B),168 regmap_reg_range(AD4695_REG_SCRATCH_PAD, AD4695_REG_SCRATCH_PAD),169 regmap_reg_range(AD4695_REG_LOOP_MODE, AD4695_REG_LOOP_MODE),170 regmap_reg_range(AD4695_REG_SPI_CONFIG_C, AD4695_REG_SPI_STATUS),171 regmap_reg_range(AD4695_REG_SETUP, AD4695_REG_AC_CTRL),172 regmap_reg_range(AD4695_REG_GPIO_CTRL, AD4695_REG_TEMP_CTRL),173 regmap_reg_range(AD4695_REG_CONFIG_IN(0), AD4695_REG_CONFIG_IN(15)),174 regmap_reg_range(AD4695_REG_AS_SLOT(0), AD4695_REG_AS_SLOT(127)),175};176 177static const struct regmap_access_table ad4695_regmap_wr_table = {178 .yes_ranges = ad4695_regmap_wr_ranges,179 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap_wr_ranges),180};181 182static const struct regmap_config ad4695_regmap_config = {183 .name = "ad4695-8",184 .reg_bits = 16,185 .val_bits = 8,186 .max_register = AD4695_REG_AS_SLOT(127),187 .rd_table = &ad4695_regmap_rd_table,188 .wr_table = &ad4695_regmap_wr_table,189 .can_multi_write = true,190};191 192static const struct regmap_range ad4695_regmap16_rd_ranges[] = {193 regmap_reg_range(AD4695_REG_STD_SEQ_CONFIG, AD4695_REG_STD_SEQ_CONFIG),194 regmap_reg_range(AD4695_REG_UPPER_IN(0), AD4695_REG_GAIN_IN(15)),195};196 197static const struct regmap_access_table ad4695_regmap16_rd_table = {198 .yes_ranges = ad4695_regmap16_rd_ranges,199 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap16_rd_ranges),200};201 202static const struct regmap_range ad4695_regmap16_wr_ranges[] = {203 regmap_reg_range(AD4695_REG_STD_SEQ_CONFIG, AD4695_REG_STD_SEQ_CONFIG),204 regmap_reg_range(AD4695_REG_UPPER_IN(0), AD4695_REG_GAIN_IN(15)),205};206 207static const struct regmap_access_table ad4695_regmap16_wr_table = {208 .yes_ranges = ad4695_regmap16_wr_ranges,209 .n_yes_ranges = ARRAY_SIZE(ad4695_regmap16_wr_ranges),210};211 212static const struct regmap_config ad4695_regmap16_config = {213 .name = "ad4695-16",214 .reg_bits = 16,215 .reg_stride = 2,216 .val_bits = 16,217 .val_format_endian = REGMAP_ENDIAN_LITTLE,218 .max_register = AD4695_REG_GAIN_IN(15),219 .rd_table = &ad4695_regmap16_rd_table,220 .wr_table = &ad4695_regmap16_wr_table,221 .can_multi_write = true,222};223 224static const struct iio_chan_spec ad4695_channel_template = {225 .type = IIO_VOLTAGE,226 .indexed = 1,227 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |228 BIT(IIO_CHAN_INFO_SCALE) |229 BIT(IIO_CHAN_INFO_OFFSET) |230 BIT(IIO_CHAN_INFO_CALIBSCALE) |231 BIT(IIO_CHAN_INFO_CALIBBIAS),232 .info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBSCALE) |233 BIT(IIO_CHAN_INFO_CALIBBIAS),234 .scan_type = {235 .sign = 'u',236 .realbits = 16,237 .storagebits = 16,238 },239};240 241static const struct iio_chan_spec ad4695_temp_channel_template = {242 .address = AD4695_CMD_TEMP_CHAN,243 .type = IIO_TEMP,244 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |245 BIT(IIO_CHAN_INFO_SCALE) |246 BIT(IIO_CHAN_INFO_OFFSET),247 .scan_type = {248 .sign = 's',249 .realbits = 16,250 .storagebits = 16,251 },252};253 254static const struct iio_chan_spec ad4695_soft_timestamp_channel_template =255 IIO_CHAN_SOFT_TIMESTAMP(0);256 257static const char * const ad4695_power_supplies[] = {258 "avdd", "vio"259};260 261static const struct ad4695_chip_info ad4695_chip_info = {262 .name = "ad4695",263 .max_sample_rate = 500 * KILO,264 .t_acq_ns = 1715,265 .num_voltage_inputs = 16,266};267 268static const struct ad4695_chip_info ad4696_chip_info = {269 .name = "ad4696",270 .max_sample_rate = 1 * MEGA,271 .t_acq_ns = 715,272 .num_voltage_inputs = 16,273};274 275static const struct ad4695_chip_info ad4697_chip_info = {276 .name = "ad4697",277 .max_sample_rate = 500 * KILO,278 .t_acq_ns = 1715,279 .num_voltage_inputs = 8,280};281 282static const struct ad4695_chip_info ad4698_chip_info = {283 .name = "ad4698",284 .max_sample_rate = 1 * MEGA,285 .t_acq_ns = 715,286 .num_voltage_inputs = 8,287};288 289/**290 * ad4695_set_single_cycle_mode - Set the device in single cycle mode291 * @st: The AD4695 state292 * @channel: The first channel to read293 *294 * As per the datasheet, to enable single cycle mode, we need to set295 * STD_SEQ_EN=0, NUM_SLOTS_AS=0 and CYC_CTRL=1 (Table 15). Setting SPI_MODE=1296 * triggers the first conversion using the channel in AS_SLOT0.297 *298 * Context: can sleep, must be called with iio_device_claim_direct held299 * Return: 0 on success, a negative error code on failure300 */301static int ad4695_set_single_cycle_mode(struct ad4695_state *st,302 unsigned int channel)303{304 int ret;305 306 ret = regmap_clear_bits(st->regmap, AD4695_REG_SEQ_CTRL,307 AD4695_REG_SEQ_CTRL_STD_SEQ_EN |308 AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS);309 if (ret)310 return ret;311 312 ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(0),313 FIELD_PREP(AD4695_REG_AS_SLOT_INX, channel));314 if (ret)315 return ret;316 317 return regmap_set_bits(st->regmap, AD4695_REG_SETUP,318 AD4695_REG_SETUP_SPI_MODE |319 AD4695_REG_SETUP_SPI_CYC_CTRL);320}321 322/**323 * ad4695_enter_advanced_sequencer_mode - Put the ADC in advanced sequencer mode324 * @st: The driver state325 * @n: The number of slots to use - must be >= 2, <= 128326 *327 * As per the datasheet, to enable advanced sequencer, we need to set328 * STD_SEQ_EN=0, NUM_SLOTS_AS=n-1 and CYC_CTRL=0 (Table 15). Setting SPI_MODE=1329 * triggers the first conversion using the channel in AS_SLOT0.330 *331 * Return: 0 on success, a negative error code on failure332 */333static int ad4695_enter_advanced_sequencer_mode(struct ad4695_state *st, u32 n)334{335 int ret;336 337 ret = regmap_update_bits(st->regmap, AD4695_REG_SEQ_CTRL,338 AD4695_REG_SEQ_CTRL_STD_SEQ_EN |339 AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS,340 FIELD_PREP(AD4695_REG_SEQ_CTRL_STD_SEQ_EN, 0) |341 FIELD_PREP(AD4695_REG_SEQ_CTRL_NUM_SLOTS_AS, n - 1));342 if (ret)343 return ret;344 345 return regmap_update_bits(st->regmap, AD4695_REG_SETUP,346 AD4695_REG_SETUP_SPI_MODE | AD4695_REG_SETUP_SPI_CYC_CTRL,347 FIELD_PREP(AD4695_REG_SETUP_SPI_MODE, 1) |348 FIELD_PREP(AD4695_REG_SETUP_SPI_CYC_CTRL, 0));349}350 351/**352 * ad4695_exit_conversion_mode - Exit conversion mode353 * @st: The AD4695 state354 *355 * Sends SPI command to exit conversion mode.356 *357 * Return: 0 on success, a negative error code on failure358 */359static int ad4695_exit_conversion_mode(struct ad4695_state *st)360{361 struct spi_transfer xfer = {362 .tx_buf = &st->cnv_cmd2,363 .len = 1,364 .delay.value = AD4695_T_REGCONFIG_NS,365 .delay.unit = SPI_DELAY_UNIT_NSECS,366 };367 368 /*369 * Technically, could do a 5-bit transfer, but shifting to start of370 * 8 bits instead for better SPI controller support.371 */372 st->cnv_cmd2 = AD4695_CMD_EXIT_CNV_MODE << 3;373 374 return spi_sync_transfer(st->spi, &xfer, 1);375}376 377static int ad4695_set_ref_voltage(struct ad4695_state *st, int vref_mv)378{379 u8 val;380 381 if (vref_mv >= 2400 && vref_mv <= 2750)382 val = 0;383 else if (vref_mv > 2750 && vref_mv <= 3250)384 val = 1;385 else if (vref_mv > 3250 && vref_mv <= 3750)386 val = 2;387 else if (vref_mv > 3750 && vref_mv <= 4500)388 val = 3;389 else if (vref_mv > 4500 && vref_mv <= 5100)390 val = 4;391 else392 return -EINVAL;393 394 return regmap_update_bits(st->regmap, AD4695_REG_REF_CTRL,395 AD4695_REG_REF_CTRL_VREF_SET,396 FIELD_PREP(AD4695_REG_REF_CTRL_VREF_SET, val));397}398 399static int ad4695_write_chn_cfg(struct ad4695_state *st,400 struct ad4695_channel_config *cfg)401{402 u32 mask, val;403 404 mask = AD4695_REG_CONFIG_IN_MODE;405 val = FIELD_PREP(AD4695_REG_CONFIG_IN_MODE, cfg->bipolar ? 1 : 0);406 407 mask |= AD4695_REG_CONFIG_IN_PAIR;408 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_PAIR, cfg->pin_pairing);409 410 mask |= AD4695_REG_CONFIG_IN_AINHIGHZ_EN;411 val |= FIELD_PREP(AD4695_REG_CONFIG_IN_AINHIGHZ_EN,412 cfg->highz_en ? 1 : 0);413 414 return regmap_update_bits(st->regmap,415 AD4695_REG_CONFIG_IN(cfg->channel),416 mask, val);417}418 419static int ad4695_buffer_preenable(struct iio_dev *indio_dev)420{421 struct ad4695_state *st = iio_priv(indio_dev);422 struct spi_transfer *xfer;423 u8 temp_chan_bit = st->chip_info->num_voltage_inputs;424 u32 bit, num_xfer, num_slots;425 u32 temp_en = 0;426 int ret;427 428 /*429 * We are using the advanced sequencer since it is the only way to read430 * multiple channels that allows individual configuration of each431 * voltage input channel. Slot 0 in the advanced sequencer is used to432 * account for the gap between trigger polls - we don't read data from433 * this slot. Each enabled voltage channel is assigned a slot starting434 * with slot 1.435 */436 num_slots = 1;437 438 memset(st->buf_read_xfer, 0, sizeof(st->buf_read_xfer));439 440 /* First xfer is only to trigger conversion of slot 1, so no rx. */441 xfer = &st->buf_read_xfer[0];442 xfer->cs_change = 1;443 xfer->delay.value = st->chip_info->t_acq_ns;444 xfer->delay.unit = SPI_DELAY_UNIT_NSECS;445 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;446 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;447 num_xfer = 1;448 449 iio_for_each_active_channel(indio_dev, bit) {450 xfer = &st->buf_read_xfer[num_xfer];451 xfer->bits_per_word = 16;452 xfer->rx_buf = &st->buf[(num_xfer - 1) * 2];453 xfer->len = 2;454 xfer->cs_change = 1;455 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;456 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;457 458 if (bit == temp_chan_bit) {459 temp_en = 1;460 } else {461 ret = regmap_write(st->regmap,462 AD4695_REG_AS_SLOT(num_slots),463 FIELD_PREP(AD4695_REG_AS_SLOT_INX, bit));464 if (ret)465 return ret;466 467 num_slots++;468 }469 470 num_xfer++;471 }472 473 /*474 * The advanced sequencer requires that at least 2 slots are enabled.475 * Since slot 0 is always used for other purposes, we need only 1476 * enabled voltage channel to meet this requirement. If the temperature477 * channel is the only enabled channel, we need to add one more slot478 * in the sequence but not read from it.479 */480 if (num_slots < 2) {481 /* move last xfer so we can insert one more xfer before it */482 st->buf_read_xfer[num_xfer] = *xfer;483 num_xfer++;484 485 /* modify 2nd to last xfer for extra slot */486 memset(xfer, 0, sizeof(*xfer));487 xfer->cs_change = 1;488 xfer->delay.value = st->chip_info->t_acq_ns;489 xfer->delay.unit = SPI_DELAY_UNIT_NSECS;490 xfer->cs_change_delay.value = AD4695_T_CONVERT_NS;491 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;492 xfer++;493 494 /* and add the extra slot in the sequencer */495 ret = regmap_write(st->regmap,496 AD4695_REG_AS_SLOT(num_slots),497 FIELD_PREP(AD4695_REG_AS_SLOT_INX, 0));498 if (ret)499 return ret;500 501 num_slots++;502 }503 504 /*505 * Don't keep CS asserted after last xfer. Also triggers conversion of506 * slot 0.507 */508 xfer->cs_change = 0;509 510 /*511 * Temperature channel isn't included in the sequence, but rather512 * controlled by setting a bit in the TEMP_CTRL register.513 */514 515 ret = regmap_update_bits(st->regmap, AD4695_REG_TEMP_CTRL,516 AD4695_REG_TEMP_CTRL_TEMP_EN,517 FIELD_PREP(AD4695_REG_TEMP_CTRL_TEMP_EN, temp_en));518 if (ret)519 return ret;520 521 spi_message_init_with_transfers(&st->buf_read_msg, st->buf_read_xfer,522 num_xfer);523 524 ret = spi_optimize_message(st->spi, &st->buf_read_msg);525 if (ret)526 return ret;527 528 /* This triggers conversion of slot 0. */529 ret = ad4695_enter_advanced_sequencer_mode(st, num_slots);530 if (ret)531 spi_unoptimize_message(&st->buf_read_msg);532 533 return ret;534}535 536static int ad4695_buffer_postdisable(struct iio_dev *indio_dev)537{538 struct ad4695_state *st = iio_priv(indio_dev);539 int ret;540 541 ret = ad4695_exit_conversion_mode(st);542 if (ret)543 return ret;544 545 spi_unoptimize_message(&st->buf_read_msg);546 547 return 0;548}549 550static const struct iio_buffer_setup_ops ad4695_buffer_setup_ops = {551 .preenable = ad4695_buffer_preenable,552 .postdisable = ad4695_buffer_postdisable,553};554 555static irqreturn_t ad4695_trigger_handler(int irq, void *p)556{557 struct iio_poll_func *pf = p;558 struct iio_dev *indio_dev = pf->indio_dev;559 struct ad4695_state *st = iio_priv(indio_dev);560 int ret;561 562 ret = spi_sync(st->spi, &st->buf_read_msg);563 if (ret)564 goto out;565 566 iio_push_to_buffers_with_timestamp(indio_dev, st->buf, pf->timestamp);567 568out:569 iio_trigger_notify_done(indio_dev->trig);570 571 return IRQ_HANDLED;572}573 574/**575 * ad4695_read_one_sample - Read a single sample using single-cycle mode576 * @st: The AD4695 state577 * @address: The address of the channel to read578 *579 * Upon successful return, the sample will be stored in `st->raw_data`.580 *581 * Context: can sleep, must be called with iio_device_claim_direct held582 * Return: 0 on success, a negative error code on failure583 */584static int ad4695_read_one_sample(struct ad4695_state *st, unsigned int address)585{586 struct spi_transfer xfer[2] = { };587 int ret, i = 0;588 589 ret = ad4695_set_single_cycle_mode(st, address);590 if (ret)591 return ret;592 593 /*594 * Setting the first channel to the temperature channel isn't supported595 * in single-cycle mode, so we have to do an extra xfer to read the596 * temperature.597 */598 if (address == AD4695_CMD_TEMP_CHAN) {599 /* We aren't reading, so we can make this a short xfer. */600 st->cnv_cmd2 = AD4695_CMD_TEMP_CHAN << 3;601 xfer[0].tx_buf = &st->cnv_cmd2;602 xfer[0].len = 1;603 xfer[0].cs_change = 1;604 xfer[0].cs_change_delay.value = AD4695_T_CONVERT_NS;605 xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;606 607 i = 1;608 }609 610 /* Then read the result and exit conversion mode. */611 st->cnv_cmd = AD4695_CMD_EXIT_CNV_MODE << 11;612 xfer[i].bits_per_word = 16;613 xfer[i].tx_buf = &st->cnv_cmd;614 xfer[i].rx_buf = &st->raw_data;615 xfer[i].len = 2;616 617 return spi_sync_transfer(st->spi, xfer, i + 1);618}619 620static int ad4695_read_raw(struct iio_dev *indio_dev,621 struct iio_chan_spec const *chan,622 int *val, int *val2, long mask)623{624 struct ad4695_state *st = iio_priv(indio_dev);625 struct ad4695_channel_config *cfg = &st->channels_cfg[chan->scan_index];626 u8 realbits = chan->scan_type.realbits;627 unsigned int reg_val;628 int ret, tmp;629 630 switch (mask) {631 case IIO_CHAN_INFO_RAW:632 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {633 ret = ad4695_read_one_sample(st, chan->address);634 if (ret)635 return ret;636 637 if (chan->scan_type.sign == 's')638 *val = sign_extend32(st->raw_data, realbits - 1);639 else640 *val = st->raw_data;641 642 return IIO_VAL_INT;643 }644 unreachable();645 case IIO_CHAN_INFO_SCALE:646 switch (chan->type) {647 case IIO_VOLTAGE:648 *val = st->vref_mv;649 *val2 = chan->scan_type.realbits;650 return IIO_VAL_FRACTIONAL_LOG2;651 case IIO_TEMP:652 /* T_scale (°C) = raw * V_REF (mV) / (-1.8 mV/°C * 2^16) */653 *val = st->vref_mv * -556;654 *val2 = 16;655 return IIO_VAL_FRACTIONAL_LOG2;656 default:657 return -EINVAL;658 }659 case IIO_CHAN_INFO_OFFSET:660 switch (chan->type) {661 case IIO_VOLTAGE:662 if (cfg->pin_pairing == AD4695_IN_PAIR_COM)663 *val = st->com_mv * (1 << realbits) / st->vref_mv;664 else if (cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD)665 *val = cfg->common_mode_mv * (1 << realbits) / st->vref_mv;666 else667 *val = 0;668 669 return IIO_VAL_INT;670 case IIO_TEMP:671 /* T_offset (°C) = -725 mV / (-1.8 mV/°C) */672 /* T_offset (raw) = T_offset (°C) * (-1.8 mV/°C) * 2^16 / V_REF (mV) */673 *val = -47513600;674 *val2 = st->vref_mv;675 return IIO_VAL_FRACTIONAL;676 default:677 return -EINVAL;678 }679 case IIO_CHAN_INFO_CALIBSCALE:680 switch (chan->type) {681 case IIO_VOLTAGE:682 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {683 ret = regmap_read(st->regmap16,684 AD4695_REG_GAIN_IN(chan->scan_index),685 ®_val);686 if (ret)687 return ret;688 689 *val = reg_val;690 *val2 = 15;691 692 return IIO_VAL_FRACTIONAL_LOG2;693 }694 unreachable();695 default:696 return -EINVAL;697 }698 case IIO_CHAN_INFO_CALIBBIAS:699 switch (chan->type) {700 case IIO_VOLTAGE:701 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {702 ret = regmap_read(st->regmap16,703 AD4695_REG_OFFSET_IN(chan->scan_index),704 ®_val);705 if (ret)706 return ret;707 708 tmp = sign_extend32(reg_val, 15);709 710 *val = tmp / 4;711 *val2 = abs(tmp) % 4 * MICRO / 4;712 713 if (tmp < 0 && *val2) {714 *val *= -1;715 *val2 *= -1;716 }717 718 return IIO_VAL_INT_PLUS_MICRO;719 }720 unreachable();721 default:722 return -EINVAL;723 }724 default:725 return -EINVAL;726 }727}728 729static int ad4695_write_raw(struct iio_dev *indio_dev,730 struct iio_chan_spec const *chan,731 int val, int val2, long mask)732{733 struct ad4695_state *st = iio_priv(indio_dev);734 unsigned int reg_val;735 736 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {737 switch (mask) {738 case IIO_CHAN_INFO_CALIBSCALE:739 switch (chan->type) {740 case IIO_VOLTAGE:741 if (val < 0 || val2 < 0)742 reg_val = 0;743 else if (val > 1)744 reg_val = U16_MAX;745 else746 reg_val = (val * (1 << 16) +747 mul_u64_u32_div(val2, 1 << 16,748 MICRO)) / 2;749 750 return regmap_write(st->regmap16,751 AD4695_REG_GAIN_IN(chan->scan_index),752 reg_val);753 default:754 return -EINVAL;755 }756 case IIO_CHAN_INFO_CALIBBIAS:757 switch (chan->type) {758 case IIO_VOLTAGE:759 if (val2 >= 0 && val > S16_MAX / 4)760 reg_val = S16_MAX;761 else if ((val2 < 0 ? -val : val) < S16_MIN / 4)762 reg_val = S16_MIN;763 else if (val2 < 0)764 reg_val = clamp_t(int,765 -(val * 4 + -val2 * 4 / MICRO),766 S16_MIN, S16_MAX);767 else if (val < 0)768 reg_val = clamp_t(int,769 val * 4 - val2 * 4 / MICRO,770 S16_MIN, S16_MAX);771 else772 reg_val = clamp_t(int,773 val * 4 + val2 * 4 / MICRO,774 S16_MIN, S16_MAX);775 776 return regmap_write(st->regmap16,777 AD4695_REG_OFFSET_IN(chan->scan_index),778 reg_val);779 default:780 return -EINVAL;781 }782 default:783 return -EINVAL;784 }785 }786 unreachable();787}788 789static int ad4695_read_avail(struct iio_dev *indio_dev,790 struct iio_chan_spec const *chan,791 const int **vals, int *type, int *length,792 long mask)793{794 static const int ad4695_calibscale_available[6] = {795 /* Range of 0 (inclusive) to 2 (exclusive) */796 0, 15, 1, 15, U16_MAX, 15797 };798 static const int ad4695_calibbias_available[6] = {799 /*800 * Datasheet says FSR/8 which translates to signed/4. The step801 * depends on oversampling ratio which is always 1 for now.802 */803 S16_MIN / 4, 0, 0, MICRO / 4, S16_MAX / 4, S16_MAX % 4 * MICRO / 4804 };805 806 switch (mask) {807 case IIO_CHAN_INFO_CALIBSCALE:808 switch (chan->type) {809 case IIO_VOLTAGE:810 *vals = ad4695_calibscale_available;811 *type = IIO_VAL_FRACTIONAL_LOG2;812 return IIO_AVAIL_RANGE;813 default:814 return -EINVAL;815 }816 case IIO_CHAN_INFO_CALIBBIAS:817 switch (chan->type) {818 case IIO_VOLTAGE:819 *vals = ad4695_calibbias_available;820 *type = IIO_VAL_INT_PLUS_MICRO;821 return IIO_AVAIL_RANGE;822 default:823 return -EINVAL;824 }825 default:826 return -EINVAL;827 }828}829 830static int ad4695_debugfs_reg_access(struct iio_dev *indio_dev,831 unsigned int reg,832 unsigned int writeval,833 unsigned int *readval)834{835 struct ad4695_state *st = iio_priv(indio_dev);836 837 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {838 if (readval) {839 if (regmap_check_range_table(st->regmap, reg,840 &ad4695_regmap_rd_table))841 return regmap_read(st->regmap, reg, readval);842 if (regmap_check_range_table(st->regmap16, reg,843 &ad4695_regmap16_rd_table))844 return regmap_read(st->regmap16, reg, readval);845 } else {846 if (regmap_check_range_table(st->regmap, reg,847 &ad4695_regmap_wr_table))848 return regmap_write(st->regmap, reg, writeval);849 if (regmap_check_range_table(st->regmap16, reg,850 &ad4695_regmap16_wr_table))851 return regmap_write(st->regmap16, reg, writeval);852 }853 }854 855 return -EINVAL;856}857 858static const struct iio_info ad4695_info = {859 .read_raw = &ad4695_read_raw,860 .write_raw = &ad4695_write_raw,861 .read_avail = &ad4695_read_avail,862 .debugfs_reg_access = &ad4695_debugfs_reg_access,863};864 865static int ad4695_parse_channel_cfg(struct ad4695_state *st)866{867 struct device *dev = &st->spi->dev;868 struct ad4695_channel_config *chan_cfg;869 struct iio_chan_spec *iio_chan;870 int ret, i;871 872 /* populate defaults */873 for (i = 0; i < st->chip_info->num_voltage_inputs; i++) {874 chan_cfg = &st->channels_cfg[i];875 iio_chan = &st->iio_chan[i];876 877 chan_cfg->highz_en = true;878 chan_cfg->channel = i;879 880 *iio_chan = ad4695_channel_template;881 iio_chan->channel = i;882 iio_chan->scan_index = i;883 iio_chan->address = AD4695_CMD_VOLTAGE_CHAN(i);884 }885 886 /* modify based on firmware description */887 device_for_each_child_node_scoped(dev, child) {888 u32 reg, val;889 890 ret = fwnode_property_read_u32(child, "reg", ®);891 if (ret)892 return dev_err_probe(dev, ret,893 "failed to read reg property (%s)\n",894 fwnode_get_name(child));895 896 if (reg >= st->chip_info->num_voltage_inputs)897 return dev_err_probe(dev, -EINVAL,898 "reg out of range (%s)\n",899 fwnode_get_name(child));900 901 iio_chan = &st->iio_chan[reg];902 chan_cfg = &st->channels_cfg[reg];903 904 chan_cfg->highz_en =905 !fwnode_property_read_bool(child, "adi,no-high-z");906 chan_cfg->bipolar = fwnode_property_read_bool(child, "bipolar");907 908 ret = fwnode_property_read_u32(child, "common-mode-channel",909 &val);910 if (ret && ret != -EINVAL)911 return dev_err_probe(dev, ret,912 "failed to read common-mode-channel (%s)\n",913 fwnode_get_name(child));914 915 if (ret == -EINVAL || val == AD4695_COMMON_MODE_REFGND)916 chan_cfg->pin_pairing = AD4695_IN_PAIR_REFGND;917 else if (val == AD4695_COMMON_MODE_COM)918 chan_cfg->pin_pairing = AD4695_IN_PAIR_COM;919 else920 chan_cfg->pin_pairing = AD4695_IN_PAIR_EVEN_ODD;921 922 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD &&923 val % 2 == 0)924 return dev_err_probe(dev, -EINVAL,925 "common-mode-channel must be odd number (%s)\n",926 fwnode_get_name(child));927 928 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD &&929 val != reg + 1)930 return dev_err_probe(dev, -EINVAL,931 "common-mode-channel must be next consecutive channel (%s)\n",932 fwnode_get_name(child));933 934 if (chan_cfg->pin_pairing == AD4695_IN_PAIR_EVEN_ODD) {935 char name[5];936 937 snprintf(name, sizeof(name), "in%d", reg + 1);938 939 ret = devm_regulator_get_enable_read_voltage(dev, name);940 if (ret < 0)941 return dev_err_probe(dev, ret,942 "failed to get %s voltage (%s)\n",943 name, fwnode_get_name(child));944 945 chan_cfg->common_mode_mv = ret / 1000;946 }947 948 if (chan_cfg->bipolar &&949 chan_cfg->pin_pairing == AD4695_IN_PAIR_REFGND)950 return dev_err_probe(dev, -EINVAL,951 "bipolar mode is not available for inputs paired with REFGND (%s).\n",952 fwnode_get_name(child));953 954 if (chan_cfg->bipolar)955 iio_chan->scan_type.sign = 's';956 957 ret = ad4695_write_chn_cfg(st, chan_cfg);958 if (ret)959 return ret;960 }961 962 /* Temperature channel must be next scan index after voltage channels. */963 st->iio_chan[i] = ad4695_temp_channel_template;964 st->iio_chan[i].scan_index = i;965 i++;966 967 st->iio_chan[i] = ad4695_soft_timestamp_channel_template;968 st->iio_chan[i].scan_index = i;969 970 return 0;971}972 973static int ad4695_probe(struct spi_device *spi)974{975 struct device *dev = &spi->dev;976 struct ad4695_state *st;977 struct iio_dev *indio_dev;978 struct gpio_desc *cnv_gpio;979 bool use_internal_ldo_supply;980 bool use_internal_ref_buffer;981 int ret;982 983 cnv_gpio = devm_gpiod_get_optional(dev, "cnv", GPIOD_OUT_LOW);984 if (IS_ERR(cnv_gpio))985 return dev_err_probe(dev, PTR_ERR(cnv_gpio),986 "Failed to get CNV GPIO\n");987 988 /* Driver currently requires CNV pin to be connected to SPI CS */989 if (cnv_gpio)990 return dev_err_probe(dev, -ENODEV,991 "CNV GPIO is not supported\n");992 993 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));994 if (!indio_dev)995 return -ENOMEM;996 997 st = iio_priv(indio_dev);998 st->spi = spi;999 1000 st->chip_info = spi_get_device_match_data(spi);1001 if (!st->chip_info)1002 return -EINVAL;1003 1004 /* Registers cannot be read at the max allowable speed */1005 spi->max_speed_hz = AD4695_REG_ACCESS_SCLK_HZ;1006 1007 st->regmap = devm_regmap_init_spi(spi, &ad4695_regmap_config);1008 if (IS_ERR(st->regmap))1009 return dev_err_probe(dev, PTR_ERR(st->regmap),1010 "Failed to initialize regmap\n");1011 1012 st->regmap16 = devm_regmap_init_spi(spi, &ad4695_regmap16_config);1013 if (IS_ERR(st->regmap16))1014 return dev_err_probe(dev, PTR_ERR(st->regmap16),1015 "Failed to initialize regmap16\n");1016 1017 ret = devm_regulator_bulk_get_enable(dev,1018 ARRAY_SIZE(ad4695_power_supplies),1019 ad4695_power_supplies);1020 if (ret)1021 return dev_err_probe(dev, ret,1022 "Failed to enable power supplies\n");1023 1024 /* If LDO_IN supply is present, then we are using internal LDO. */1025 ret = devm_regulator_get_enable_optional(dev, "ldo-in");1026 if (ret < 0 && ret != -ENODEV)1027 return dev_err_probe(dev, ret,1028 "Failed to enable LDO_IN supply\n");1029 1030 use_internal_ldo_supply = ret == 0;1031 1032 if (!use_internal_ldo_supply) {1033 /* Otherwise we need an external VDD supply. */1034 ret = devm_regulator_get_enable(dev, "vdd");1035 if (ret < 0)1036 return dev_err_probe(dev, ret,1037 "Failed to enable VDD supply\n");1038 }1039 1040 /* If REFIN supply is given, then we are using internal buffer */1041 ret = devm_regulator_get_enable_read_voltage(dev, "refin");1042 if (ret < 0 && ret != -ENODEV)1043 return dev_err_probe(dev, ret, "Failed to get REFIN voltage\n");1044 1045 if (ret != -ENODEV) {1046 st->vref_mv = ret / 1000;1047 use_internal_ref_buffer = true;1048 } else {1049 /* Otherwise, we need an external reference. */1050 ret = devm_regulator_get_enable_read_voltage(dev, "ref");1051 if (ret < 0)1052 return dev_err_probe(dev, ret,1053 "Failed to get REF voltage\n");1054 1055 st->vref_mv = ret / 1000;1056 use_internal_ref_buffer = false;1057 }1058 1059 ret = devm_regulator_get_enable_read_voltage(dev, "com");1060 if (ret < 0 && ret != -ENODEV)1061 return dev_err_probe(dev, ret, "Failed to get COM voltage\n");1062 1063 st->com_mv = ret == -ENODEV ? 0 : ret / 1000;1064 1065 /*1066 * Reset the device using hardware reset if available or fall back to1067 * software reset.1068 */1069 1070 st->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);1071 if (IS_ERR(st->reset_gpio))1072 return PTR_ERR(st->reset_gpio);1073 1074 if (st->reset_gpio) {1075 gpiod_set_value(st->reset_gpio, 0);1076 msleep(AD4695_T_WAKEUP_HW_MS);1077 } else {1078 ret = regmap_write(st->regmap, AD4695_REG_SPI_CONFIG_A,1079 AD4695_REG_SPI_CONFIG_A_SW_RST);1080 if (ret)1081 return ret;1082 1083 msleep(AD4695_T_WAKEUP_SW_MS);1084 }1085 1086 /* Needed for regmap16 to be able to work correctly. */1087 ret = regmap_set_bits(st->regmap, AD4695_REG_SPI_CONFIG_A,1088 AD4695_REG_SPI_CONFIG_A_ADDR_DIR);1089 if (ret)1090 return ret;1091 1092 /* Disable internal LDO if it isn't needed. */1093 ret = regmap_update_bits(st->regmap, AD4695_REG_SETUP,1094 AD4695_REG_SETUP_LDO_EN,1095 FIELD_PREP(AD4695_REG_SETUP_LDO_EN,1096 use_internal_ldo_supply ? 1 : 0));1097 if (ret)1098 return ret;1099 1100 /* configure reference supply */1101 1102 if (device_property_present(dev, "adi,no-ref-current-limit")) {1103 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL,1104 AD4695_REG_REF_CTRL_OV_MODE);1105 if (ret)1106 return ret;1107 }1108 1109 if (device_property_present(dev, "adi,no-ref-high-z")) {1110 if (use_internal_ref_buffer)1111 return dev_err_probe(dev, -EINVAL,1112 "Cannot disable high-Z mode for internal reference buffer\n");1113 1114 ret = regmap_clear_bits(st->regmap, AD4695_REG_REF_CTRL,1115 AD4695_REG_REF_CTRL_REFHIZ_EN);1116 if (ret)1117 return ret;1118 }1119 1120 ret = ad4695_set_ref_voltage(st, st->vref_mv);1121 if (ret)1122 return ret;1123 1124 if (use_internal_ref_buffer) {1125 ret = regmap_set_bits(st->regmap, AD4695_REG_REF_CTRL,1126 AD4695_REG_REF_CTRL_REFBUF_EN);1127 if (ret)1128 return ret;1129 1130 /* Give the capacitor some time to charge up. */1131 msleep(AD4695_T_REFBUF_MS);1132 }1133 1134 ret = ad4695_parse_channel_cfg(st);1135 if (ret)1136 return ret;1137 1138 indio_dev->name = st->chip_info->name;1139 indio_dev->info = &ad4695_info;1140 indio_dev->modes = INDIO_DIRECT_MODE;1141 indio_dev->channels = st->iio_chan;1142 indio_dev->num_channels = st->chip_info->num_voltage_inputs + 2;1143 1144 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,1145 iio_pollfunc_store_time,1146 ad4695_trigger_handler,1147 &ad4695_buffer_setup_ops);1148 if (ret)1149 return ret;1150 1151 return devm_iio_device_register(dev, indio_dev);1152}1153 1154static const struct spi_device_id ad4695_spi_id_table[] = {1155 { .name = "ad4695", .driver_data = (kernel_ulong_t)&ad4695_chip_info },1156 { .name = "ad4696", .driver_data = (kernel_ulong_t)&ad4696_chip_info },1157 { .name = "ad4697", .driver_data = (kernel_ulong_t)&ad4697_chip_info },1158 { .name = "ad4698", .driver_data = (kernel_ulong_t)&ad4698_chip_info },1159 { }1160};1161MODULE_DEVICE_TABLE(spi, ad4695_spi_id_table);1162 1163static const struct of_device_id ad4695_of_match_table[] = {1164 { .compatible = "adi,ad4695", .data = &ad4695_chip_info, },1165 { .compatible = "adi,ad4696", .data = &ad4696_chip_info, },1166 { .compatible = "adi,ad4697", .data = &ad4697_chip_info, },1167 { .compatible = "adi,ad4698", .data = &ad4698_chip_info, },1168 { }1169};1170MODULE_DEVICE_TABLE(of, ad4695_of_match_table);1171 1172static struct spi_driver ad4695_driver = {1173 .driver = {1174 .name = "ad4695",1175 .of_match_table = ad4695_of_match_table,1176 },1177 .probe = ad4695_probe,1178 .id_table = ad4695_spi_id_table,1179};1180module_spi_driver(ad4695_driver);1181 1182MODULE_AUTHOR("Ramona Gradinariu <ramona.gradinariu@analog.com>");1183MODULE_AUTHOR("David Lechner <dlechner@baylibre.com>");1184MODULE_DESCRIPTION("Analog Devices AD4695 ADC driver");1185MODULE_LICENSE("GPL");1186