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1// SPDX-License-Identifier: GPL-2.02/*3 * AD7192 and similar SPI ADC driver4 *5 * Copyright 2011-2015 Analog Devices Inc.6 */7 8#include <linux/interrupt.h>9#include <linux/bitfield.h>10#include <linux/clk.h>11#include <linux/clk-provider.h>12#include <linux/device.h>13#include <linux/kernel.h>14#include <linux/slab.h>15#include <linux/sysfs.h>16#include <linux/spi/spi.h>17#include <linux/regulator/consumer.h>18#include <linux/err.h>19#include <linux/sched.h>20#include <linux/delay.h>21#include <linux/module.h>22#include <linux/mod_devicetable.h>23#include <linux/property.h>24#include <linux/units.h>25 26#include <linux/iio/iio.h>27#include <linux/iio/sysfs.h>28#include <linux/iio/buffer.h>29#include <linux/iio/trigger.h>30#include <linux/iio/trigger_consumer.h>31#include <linux/iio/triggered_buffer.h>32#include <linux/iio/adc/ad_sigma_delta.h>33 34/* Registers */35#define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */36#define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */37#define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */38#define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */39#define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */40#define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */41#define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */42#define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */43 /* (AD7792)/24-bit (AD7192)) */44#define AD7192_REG_FULLSALE 7 /* Full-Scale Register */45 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */46 47/* Communications Register Bit Designations (AD7192_REG_COMM) */48#define AD7192_COMM_WEN BIT(7) /* Write Enable */49#define AD7192_COMM_WRITE 0 /* Write Operation */50#define AD7192_COMM_READ BIT(6) /* Read Operation */51#define AD7192_COMM_ADDR_MASK GENMASK(5, 3) /* Register Address Mask */52#define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */53 54/* Status Register Bit Designations (AD7192_REG_STAT) */55#define AD7192_STAT_RDY BIT(7) /* Ready */56#define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */57#define AD7192_STAT_NOREF BIT(5) /* Error no external reference */58#define AD7192_STAT_PARITY BIT(4) /* Parity */59#define AD7192_STAT_CH3 BIT(2) /* Channel 3 */60#define AD7192_STAT_CH2 BIT(1) /* Channel 2 */61#define AD7192_STAT_CH1 BIT(0) /* Channel 1 */62 63/* Mode Register Bit Designations (AD7192_REG_MODE) */64#define AD7192_MODE_SEL_MASK GENMASK(23, 21) /* Operation Mode Select Mask */65#define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */66#define AD7192_MODE_CLKSRC_MASK GENMASK(19, 18) /* Clock Source Select Mask */67#define AD7192_MODE_AVG_MASK GENMASK(17, 16)68 /* Fast Settling Filter Average Select Mask (AD7193 only) */69#define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */70#define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */71#define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/72#define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */73#define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */74 /* Filter Update Rate Select Mask */75#define AD7192_MODE_RATE_MASK GENMASK(9, 0)76 77/* Mode Register: AD7192_MODE_SEL options */78#define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */79#define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */80#define AD7192_MODE_IDLE 2 /* Idle Mode */81#define AD7192_MODE_PWRDN 3 /* Power-Down Mode */82#define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */83#define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */84#define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */85#define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */86 87/* Mode Register: AD7192_MODE_CLKSRC options */88#define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/89 /* from MCLK1 to MCLK2 */90#define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */91#define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */92 /* available at the MCLK2 pin */93#define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/94 /* at the MCLK2 pin */95 96/* Configuration Register Bit Designations (AD7192_REG_CONF) */97 98#define AD7192_CONF_CHOP BIT(23) /* CHOP enable */99#define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */100#define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */101#define AD7192_CONF_CHAN_MASK GENMASK(18, 8) /* Channel select mask */102#define AD7192_CONF_BURN BIT(7) /* Burnout current enable */103#define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */104#define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */105#define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */106#define AD7192_CONF_GAIN_MASK GENMASK(2, 0) /* Gain Select */107 108#define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */109#define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */110#define AD7192_CH_TEMP BIT(2) /* Temp Sensor */111#define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */112#define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */113#define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */114#define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */115#define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */116 117#define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */118#define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */119#define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */120#define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */121#define AD7193_CH_TEMP 0x100 /* Temp senseor */122#define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */123#define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */124#define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */125#define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */126#define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */127#define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */128#define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */129#define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */130#define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */131#define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */132 133#define AD7194_CH_POS(x) (((x) - 1) << 4)134#define AD7194_CH_NEG(x) ((x) - 1)135 136/* 10th bit corresponds to CON18(Pseudo) */137#define AD7194_CH(p) (BIT(10) | AD7194_CH_POS(p))138 139#define AD7194_DIFF_CH(p, n) (AD7194_CH_POS(p) | AD7194_CH_NEG(n))140#define AD7194_CH_TEMP 0x100141#define AD7194_CH_BASE_NR 2142#define AD7194_CH_AIN_START 1143#define AD7194_CH_AIN_NR 16144#define AD7194_CH_MAX_NR 272145 146/* ID Register Bit Designations (AD7192_REG_ID) */147#define CHIPID_AD7190 0x4148#define CHIPID_AD7192 0x0149#define CHIPID_AD7193 0x2150#define CHIPID_AD7194 0x3151#define CHIPID_AD7195 0x6152#define AD7192_ID_MASK GENMASK(3, 0)153 154/* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */155#define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */156#define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */157#define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */158#define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */159#define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */160#define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */161#define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */162 163#define AD7192_EXT_FREQ_MHZ_MIN 2457600164#define AD7192_EXT_FREQ_MHZ_MAX 5120000165#define AD7192_INT_FREQ_MHZ 4915200166 167#define AD7192_NO_SYNC_FILTER 1168#define AD7192_SYNC3_FILTER 3169#define AD7192_SYNC4_FILTER 4170 171/* NOTE:172 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.173 * In order to avoid contentions on the SPI bus, it's therefore necessary174 * to use spi bus locking.175 *176 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.177 */178 179enum {180 AD7192_SYSCALIB_ZERO_SCALE,181 AD7192_SYSCALIB_FULL_SCALE,182};183 184enum {185 ID_AD7190,186 ID_AD7192,187 ID_AD7193,188 ID_AD7194,189 ID_AD7195,190};191 192struct ad7192_chip_info {193 unsigned int chip_id;194 const char *name;195 const struct iio_chan_spec *channels;196 u8 num_channels;197 const struct ad_sigma_delta_info *sigma_delta_info;198 const struct iio_info *info;199 int (*parse_channels)(struct iio_dev *indio_dev);200};201 202struct ad7192_state {203 const struct ad7192_chip_info *chip_info;204 struct clk *mclk;205 struct clk_hw int_clk_hw;206 u16 int_vref_mv;207 u32 aincom_mv;208 u32 fclk;209 u32 mode;210 u32 conf;211 u32 scale_avail[8][2];212 u32 filter_freq_avail[4][2];213 u32 oversampling_ratio_avail[4];214 u8 gpocon;215 u8 clock_sel;216 struct mutex lock; /* protect sensor state */217 u8 syscalib_mode[8];218 219 struct ad_sigma_delta sd;220};221 222static const char * const ad7192_syscalib_modes[] = {223 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",224 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",225};226 227static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,228 const struct iio_chan_spec *chan,229 unsigned int mode)230{231 struct ad7192_state *st = iio_priv(indio_dev);232 233 st->syscalib_mode[chan->channel] = mode;234 235 return 0;236}237 238static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,239 const struct iio_chan_spec *chan)240{241 struct ad7192_state *st = iio_priv(indio_dev);242 243 return st->syscalib_mode[chan->channel];244}245 246static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,247 uintptr_t private,248 const struct iio_chan_spec *chan,249 const char *buf, size_t len)250{251 struct ad7192_state *st = iio_priv(indio_dev);252 bool sys_calib;253 int ret, temp;254 255 ret = kstrtobool(buf, &sys_calib);256 if (ret)257 return ret;258 259 temp = st->syscalib_mode[chan->channel];260 if (sys_calib) {261 if (temp == AD7192_SYSCALIB_ZERO_SCALE)262 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,263 chan->address);264 else265 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,266 chan->address);267 }268 269 return ret ? ret : len;270}271 272static const struct iio_enum ad7192_syscalib_mode_enum = {273 .items = ad7192_syscalib_modes,274 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),275 .set = ad7192_set_syscalib_mode,276 .get = ad7192_get_syscalib_mode277};278 279static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {280 {281 .name = "sys_calibration",282 .write = ad7192_write_syscalib,283 .shared = IIO_SEPARATE,284 },285 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,286 &ad7192_syscalib_mode_enum),287 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,288 &ad7192_syscalib_mode_enum),289 { }290};291 292static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)293{294 return container_of(sd, struct ad7192_state, sd);295}296 297static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)298{299 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);300 301 st->conf &= ~AD7192_CONF_CHAN_MASK;302 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel);303 304 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);305}306 307static int ad7192_set_mode(struct ad_sigma_delta *sd,308 enum ad_sigma_delta_mode mode)309{310 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);311 312 st->mode &= ~AD7192_MODE_SEL_MASK;313 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode);314 315 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);316}317 318static int ad7192_append_status(struct ad_sigma_delta *sd, bool append)319{320 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);321 unsigned int mode = st->mode;322 int ret;323 324 mode &= ~AD7192_MODE_STA_MASK;325 mode |= FIELD_PREP(AD7192_MODE_STA_MASK, append);326 327 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode);328 if (ret < 0)329 return ret;330 331 st->mode = mode;332 333 return 0;334}335 336static int ad7192_disable_all(struct ad_sigma_delta *sd)337{338 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);339 u32 conf = st->conf;340 int ret;341 342 conf &= ~AD7192_CONF_CHAN_MASK;343 344 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);345 if (ret < 0)346 return ret;347 348 st->conf = conf;349 350 return 0;351}352 353static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {354 .set_channel = ad7192_set_channel,355 .append_status = ad7192_append_status,356 .disable_all = ad7192_disable_all,357 .set_mode = ad7192_set_mode,358 .has_registers = true,359 .addr_shift = 3,360 .read_mask = BIT(6),361 .status_ch_mask = GENMASK(3, 0),362 .num_slots = 4,363 .irq_flags = IRQF_TRIGGER_FALLING,364};365 366static const struct ad_sigma_delta_info ad7194_sigma_delta_info = {367 .set_channel = ad7192_set_channel,368 .append_status = ad7192_append_status,369 .disable_all = ad7192_disable_all,370 .set_mode = ad7192_set_mode,371 .has_registers = true,372 .addr_shift = 3,373 .read_mask = BIT(6),374 .status_ch_mask = GENMASK(3, 0),375 .irq_flags = IRQF_TRIGGER_FALLING,376};377 378static const struct ad_sd_calib_data ad7192_calib_arr[8] = {379 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},380 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},381 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},382 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},383 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},384 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},385 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},386 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}387};388 389static int ad7192_calibrate_all(struct ad7192_state *st)390{391 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,392 ARRAY_SIZE(ad7192_calib_arr));393}394 395static inline bool ad7192_valid_external_frequency(u32 freq)396{397 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&398 freq <= AD7192_EXT_FREQ_MHZ_MAX);399}400 401/*402 * Position 0 of ad7192_clock_names, xtal, corresponds to clock source403 * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to404 * AD7192_CLK_EXT_MCLK2405 */406static const char *const ad7192_clock_names[] = {407 "xtal",408 "mclk"409};410 411static struct ad7192_state *clk_hw_to_ad7192(struct clk_hw *hw)412{413 return container_of(hw, struct ad7192_state, int_clk_hw);414}415 416static unsigned long ad7192_clk_recalc_rate(struct clk_hw *hw,417 unsigned long parent_rate)418{419 return AD7192_INT_FREQ_MHZ;420}421 422static int ad7192_clk_output_is_enabled(struct clk_hw *hw)423{424 struct ad7192_state *st = clk_hw_to_ad7192(hw);425 426 return st->clock_sel == AD7192_CLK_INT_CO;427}428 429static int ad7192_clk_prepare(struct clk_hw *hw)430{431 struct ad7192_state *st = clk_hw_to_ad7192(hw);432 int ret;433 434 st->mode &= ~AD7192_MODE_CLKSRC_MASK;435 st->mode |= AD7192_CLK_INT_CO;436 437 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);438 if (ret)439 return ret;440 441 st->clock_sel = AD7192_CLK_INT_CO;442 443 return 0;444}445 446static void ad7192_clk_unprepare(struct clk_hw *hw)447{448 struct ad7192_state *st = clk_hw_to_ad7192(hw);449 int ret;450 451 st->mode &= ~AD7192_MODE_CLKSRC_MASK;452 st->mode |= AD7192_CLK_INT;453 454 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);455 if (ret)456 return;457 458 st->clock_sel = AD7192_CLK_INT;459}460 461static const struct clk_ops ad7192_int_clk_ops = {462 .recalc_rate = ad7192_clk_recalc_rate,463 .is_enabled = ad7192_clk_output_is_enabled,464 .prepare = ad7192_clk_prepare,465 .unprepare = ad7192_clk_unprepare,466};467 468static int ad7192_register_clk_provider(struct ad7192_state *st)469{470 struct device *dev = &st->sd.spi->dev;471 struct clk_init_data init = {};472 int ret;473 474 if (!IS_ENABLED(CONFIG_COMMON_CLK))475 return 0;476 477 if (!device_property_present(dev, "#clock-cells"))478 return 0;479 480 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk",481 fwnode_get_name(dev_fwnode(dev)));482 if (!init.name)483 return -ENOMEM;484 485 init.ops = &ad7192_int_clk_ops;486 487 st->int_clk_hw.init = &init;488 ret = devm_clk_hw_register(dev, &st->int_clk_hw);489 if (ret)490 return ret;491 492 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,493 &st->int_clk_hw);494}495 496static int ad7192_clock_setup(struct ad7192_state *st)497{498 struct device *dev = &st->sd.spi->dev;499 int ret;500 501 /*502 * The following two if branches are kept for backward compatibility but503 * the use of the two devicetree properties is highly discouraged. Clock504 * configuration should be done according to the bindings.505 */506 507 if (device_property_read_bool(dev, "adi,int-clock-output-enable")) {508 st->clock_sel = AD7192_CLK_INT_CO;509 st->fclk = AD7192_INT_FREQ_MHZ;510 dev_warn(dev, "Property adi,int-clock-output-enable is deprecated! Check bindings!\n");511 return 0;512 }513 514 if (device_property_read_bool(dev, "adi,clock-xtal")) {515 st->clock_sel = AD7192_CLK_EXT_MCLK1_2;516 st->mclk = devm_clk_get_enabled(dev, "mclk");517 if (IS_ERR(st->mclk))518 return dev_err_probe(dev, PTR_ERR(st->mclk),519 "Failed to get mclk\n");520 521 st->fclk = clk_get_rate(st->mclk);522 if (!ad7192_valid_external_frequency(st->fclk))523 return dev_err_probe(dev, -EINVAL,524 "External clock frequency out of bounds\n");525 526 dev_warn(dev, "Property adi,clock-xtal is deprecated! Check bindings!\n");527 return 0;528 }529 530 ret = device_property_match_property_string(dev, "clock-names",531 ad7192_clock_names,532 ARRAY_SIZE(ad7192_clock_names));533 if (ret < 0) {534 st->clock_sel = AD7192_CLK_INT;535 st->fclk = AD7192_INT_FREQ_MHZ;536 537 ret = ad7192_register_clk_provider(st);538 if (ret)539 return dev_err_probe(dev, ret,540 "Failed to register clock provider\n");541 return 0;542 }543 544 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret;545 546 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]);547 if (IS_ERR(st->mclk))548 return dev_err_probe(dev, PTR_ERR(st->mclk),549 "Failed to get clock source\n");550 551 st->fclk = clk_get_rate(st->mclk);552 if (!ad7192_valid_external_frequency(st->fclk))553 return dev_err_probe(dev, -EINVAL,554 "External clock frequency out of bounds\n");555 556 return 0;557}558 559static int ad7192_setup(struct iio_dev *indio_dev, struct device *dev)560{561 struct ad7192_state *st = iio_priv(indio_dev);562 bool rej60_en, refin2_en;563 bool buf_en, bipolar, burnout_curr_en;564 unsigned long long scale_uv;565 int i, ret, id;566 567 /* reset the serial interface */568 ret = ad_sd_reset(&st->sd, 48);569 if (ret < 0)570 return ret;571 usleep_range(500, 1000); /* Wait for at least 500us */572 573 /* write/read test for device presence */574 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);575 if (ret)576 return ret;577 578 id = FIELD_GET(AD7192_ID_MASK, id);579 580 if (id != st->chip_info->chip_id)581 dev_warn(dev, "device ID query failed (0x%X != 0x%X)\n",582 id, st->chip_info->chip_id);583 584 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) |585 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) |586 FIELD_PREP(AD7192_MODE_RATE_MASK, 480);587 588 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0);589 590 rej60_en = device_property_read_bool(dev, "adi,rejection-60-Hz-enable");591 if (rej60_en)592 st->mode |= AD7192_MODE_REJ60;593 594 refin2_en = device_property_read_bool(dev, "adi,refin2-pins-enable");595 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)596 st->conf |= AD7192_CONF_REFSEL;597 598 st->conf &= ~AD7192_CONF_CHOP;599 600 buf_en = device_property_read_bool(dev, "adi,buffer-enable");601 if (buf_en)602 st->conf |= AD7192_CONF_BUF;603 604 bipolar = device_property_read_bool(dev, "bipolar");605 if (!bipolar)606 st->conf |= AD7192_CONF_UNIPOLAR;607 608 burnout_curr_en = device_property_read_bool(dev,609 "adi,burnout-currents-enable");610 if (burnout_curr_en && buf_en) {611 st->conf |= AD7192_CONF_BURN;612 } else if (burnout_curr_en) {613 dev_warn(dev,614 "Can't enable burnout currents: see CHOP or buffer\n");615 }616 617 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);618 if (ret)619 return ret;620 621 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);622 if (ret)623 return ret;624 625 ret = ad7192_calibrate_all(st);626 if (ret)627 return ret;628 629 /* Populate available ADC input ranges */630 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {631 scale_uv = ((u64)st->int_vref_mv * 100000000)632 >> (indio_dev->channels[0].scan_type.realbits -633 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf));634 scale_uv >>= i;635 636 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;637 st->scale_avail[i][0] = scale_uv;638 }639 640 st->oversampling_ratio_avail[0] = 1;641 st->oversampling_ratio_avail[1] = 2;642 st->oversampling_ratio_avail[2] = 8;643 st->oversampling_ratio_avail[3] = 16;644 645 st->filter_freq_avail[0][0] = 600;646 st->filter_freq_avail[1][0] = 800;647 st->filter_freq_avail[2][0] = 2300;648 st->filter_freq_avail[3][0] = 2720;649 650 st->filter_freq_avail[0][1] = 1000;651 st->filter_freq_avail[1][1] = 1000;652 st->filter_freq_avail[2][1] = 1000;653 st->filter_freq_avail[3][1] = 1000;654 655 return 0;656}657 658static ssize_t ad7192_show_ac_excitation(struct device *dev,659 struct device_attribute *attr,660 char *buf)661{662 struct iio_dev *indio_dev = dev_to_iio_dev(dev);663 struct ad7192_state *st = iio_priv(indio_dev);664 665 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf));666}667 668static ssize_t ad7192_show_bridge_switch(struct device *dev,669 struct device_attribute *attr,670 char *buf)671{672 struct iio_dev *indio_dev = dev_to_iio_dev(dev);673 struct ad7192_state *st = iio_priv(indio_dev);674 675 return sysfs_emit(buf, "%ld\n",676 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon));677}678 679static ssize_t ad7192_set(struct device *dev,680 struct device_attribute *attr,681 const char *buf,682 size_t len)683{684 struct iio_dev *indio_dev = dev_to_iio_dev(dev);685 struct ad7192_state *st = iio_priv(indio_dev);686 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);687 int ret;688 bool val;689 690 ret = kstrtobool(buf, &val);691 if (ret < 0)692 return ret;693 694 ret = iio_device_claim_direct_mode(indio_dev);695 if (ret)696 return ret;697 698 switch ((u32)this_attr->address) {699 case AD7192_REG_GPOCON:700 if (val)701 st->gpocon |= AD7192_GPOCON_BPDSW;702 else703 st->gpocon &= ~AD7192_GPOCON_BPDSW;704 705 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);706 break;707 case AD7192_REG_CONF:708 if (val)709 st->conf |= AD7192_CONF_ACX;710 else711 st->conf &= ~AD7192_CONF_ACX;712 713 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);714 break;715 default:716 ret = -EINVAL;717 }718 719 iio_device_release_direct_mode(indio_dev);720 721 return ret ? ret : len;722}723 724static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en)725{726 u8 avg_factor_selected, oversampling_ratio;727 728 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode);729 730 if (!avg_factor_selected && !chop_en)731 return 1;732 733 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected];734 735 if (sinc3_en)736 return AD7192_SYNC3_FILTER + oversampling_ratio - 1;737 738 return AD7192_SYNC4_FILTER + oversampling_ratio - 1;739}740 741static int ad7192_get_f_order(struct ad7192_state *st)742{743 bool sinc3_en, chop_en;744 745 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode);746 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf);747 748 return ad7192_compute_f_order(st, sinc3_en, chop_en);749}750 751static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en,752 bool chop_en)753{754 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en);755 756 return DIV_ROUND_CLOSEST(st->fclk,757 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));758}759 760static int ad7192_get_f_adc(struct ad7192_state *st)761{762 unsigned int f_order = ad7192_get_f_order(st);763 764 return DIV_ROUND_CLOSEST(st->fclk,765 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode));766}767 768static void ad7192_update_filter_freq_avail(struct ad7192_state *st)769{770 unsigned int fadc;771 772 /* Formulas for filter at page 25 of the datasheet */773 fadc = ad7192_compute_f_adc(st, false, true);774 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);775 776 fadc = ad7192_compute_f_adc(st, true, true);777 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);778 779 fadc = ad7192_compute_f_adc(st, false, false);780 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024);781 782 fadc = ad7192_compute_f_adc(st, true, false);783 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024);784}785 786static IIO_DEVICE_ATTR(bridge_switch_en, 0644,787 ad7192_show_bridge_switch, ad7192_set,788 AD7192_REG_GPOCON);789 790static IIO_DEVICE_ATTR(ac_excitation_en, 0644,791 ad7192_show_ac_excitation, ad7192_set,792 AD7192_REG_CONF);793 794static struct attribute *ad7192_attributes[] = {795 &iio_dev_attr_bridge_switch_en.dev_attr.attr,796 NULL797};798 799static const struct attribute_group ad7192_attribute_group = {800 .attrs = ad7192_attributes,801};802 803static struct attribute *ad7195_attributes[] = {804 &iio_dev_attr_bridge_switch_en.dev_attr.attr,805 &iio_dev_attr_ac_excitation_en.dev_attr.attr,806 NULL807};808 809static const struct attribute_group ad7195_attribute_group = {810 .attrs = ad7195_attributes,811};812 813static unsigned int ad7192_get_temp_scale(bool unipolar)814{815 return unipolar ? 2815 * 2 : 2815;816}817 818static int ad7192_set_3db_filter_freq(struct ad7192_state *st,819 int val, int val2)820{821 int i, ret, freq;822 unsigned int diff_new, diff_old;823 int idx = 0;824 825 diff_old = U32_MAX;826 freq = val * 1000 + val2;827 828 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) {829 diff_new = abs(freq - st->filter_freq_avail[i][0]);830 if (diff_new < diff_old) {831 diff_old = diff_new;832 idx = i;833 }834 }835 836 switch (idx) {837 case 0:838 st->mode &= ~AD7192_MODE_SINC3;839 840 st->conf |= AD7192_CONF_CHOP;841 break;842 case 1:843 st->mode |= AD7192_MODE_SINC3;844 845 st->conf |= AD7192_CONF_CHOP;846 break;847 case 2:848 st->mode &= ~AD7192_MODE_SINC3;849 850 st->conf &= ~AD7192_CONF_CHOP;851 break;852 case 3:853 st->mode |= AD7192_MODE_SINC3;854 855 st->conf &= ~AD7192_CONF_CHOP;856 break;857 }858 859 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);860 if (ret < 0)861 return ret;862 863 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);864}865 866static int ad7192_get_3db_filter_freq(struct ad7192_state *st)867{868 unsigned int fadc;869 870 fadc = ad7192_get_f_adc(st);871 872 if (FIELD_GET(AD7192_CONF_CHOP, st->conf))873 return DIV_ROUND_CLOSEST(fadc * 240, 1024);874 if (FIELD_GET(AD7192_MODE_SINC3, st->mode))875 return DIV_ROUND_CLOSEST(fadc * 272, 1024);876 else877 return DIV_ROUND_CLOSEST(fadc * 230, 1024);878}879 880static int ad7192_read_raw(struct iio_dev *indio_dev,881 struct iio_chan_spec const *chan,882 int *val,883 int *val2,884 long m)885{886 struct ad7192_state *st = iio_priv(indio_dev);887 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf);888 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf);889 890 switch (m) {891 case IIO_CHAN_INFO_RAW:892 return ad_sigma_delta_single_conversion(indio_dev, chan, val);893 case IIO_CHAN_INFO_SCALE:894 switch (chan->type) {895 case IIO_VOLTAGE:896 mutex_lock(&st->lock);897 *val = st->scale_avail[gain][0];898 *val2 = st->scale_avail[gain][1];899 mutex_unlock(&st->lock);900 return IIO_VAL_INT_PLUS_NANO;901 case IIO_TEMP:902 *val = 0;903 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);904 return IIO_VAL_INT_PLUS_NANO;905 default:906 return -EINVAL;907 }908 case IIO_CHAN_INFO_OFFSET:909 if (!unipolar)910 *val = -(1 << (chan->scan_type.realbits - 1));911 else912 *val = 0;913 914 switch (chan->type) {915 case IIO_VOLTAGE:916 /*917 * Only applies to pseudo-differential inputs.918 * AINCOM voltage has to be converted to "raw" units.919 */920 if (st->aincom_mv && !chan->differential)921 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO,922 st->scale_avail[gain][1]);923 return IIO_VAL_INT;924 /* Kelvin to Celsius */925 case IIO_TEMP:926 *val -= 273 * ad7192_get_temp_scale(unipolar);927 return IIO_VAL_INT;928 default:929 return -EINVAL;930 }931 case IIO_CHAN_INFO_SAMP_FREQ:932 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024);933 return IIO_VAL_INT;934 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:935 *val = ad7192_get_3db_filter_freq(st);936 *val2 = 1000;937 return IIO_VAL_FRACTIONAL;938 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:939 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)];940 return IIO_VAL_INT;941 }942 943 return -EINVAL;944}945 946static int ad7192_write_raw(struct iio_dev *indio_dev,947 struct iio_chan_spec const *chan,948 int val,949 int val2,950 long mask)951{952 struct ad7192_state *st = iio_priv(indio_dev);953 int ret, i, div;954 unsigned int tmp;955 956 ret = iio_device_claim_direct_mode(indio_dev);957 if (ret)958 return ret;959 960 mutex_lock(&st->lock);961 962 switch (mask) {963 case IIO_CHAN_INFO_SCALE:964 ret = -EINVAL;965 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)966 if (val2 == st->scale_avail[i][1]) {967 ret = 0;968 tmp = st->conf;969 st->conf &= ~AD7192_CONF_GAIN_MASK;970 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i);971 if (tmp == st->conf)972 break;973 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,974 3, st->conf);975 ad7192_calibrate_all(st);976 break;977 }978 break;979 case IIO_CHAN_INFO_SAMP_FREQ:980 if (!val) {981 ret = -EINVAL;982 break;983 }984 985 div = st->fclk / (val * ad7192_get_f_order(st) * 1024);986 if (div < 1 || div > 1023) {987 ret = -EINVAL;988 break;989 }990 991 st->mode &= ~AD7192_MODE_RATE_MASK;992 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div);993 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);994 ad7192_update_filter_freq_avail(st);995 break;996 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:997 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);998 break;999 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:1000 ret = -EINVAL;1001 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++)1002 if (val == st->oversampling_ratio_avail[i]) {1003 ret = 0;1004 tmp = st->mode;1005 st->mode &= ~AD7192_MODE_AVG_MASK;1006 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i);1007 if (tmp == st->mode)1008 break;1009 ad_sd_write_reg(&st->sd, AD7192_REG_MODE,1010 3, st->mode);1011 break;1012 }1013 ad7192_update_filter_freq_avail(st);1014 break;1015 default:1016 ret = -EINVAL;1017 }1018 1019 mutex_unlock(&st->lock);1020 1021 iio_device_release_direct_mode(indio_dev);1022 1023 return ret;1024}1025 1026static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,1027 struct iio_chan_spec const *chan,1028 long mask)1029{1030 switch (mask) {1031 case IIO_CHAN_INFO_SCALE:1032 return IIO_VAL_INT_PLUS_NANO;1033 case IIO_CHAN_INFO_SAMP_FREQ:1034 return IIO_VAL_INT;1035 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:1036 return IIO_VAL_INT_PLUS_MICRO;1037 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:1038 return IIO_VAL_INT;1039 default:1040 return -EINVAL;1041 }1042}1043 1044static int ad7192_read_avail(struct iio_dev *indio_dev,1045 struct iio_chan_spec const *chan,1046 const int **vals, int *type, int *length,1047 long mask)1048{1049 struct ad7192_state *st = iio_priv(indio_dev);1050 1051 switch (mask) {1052 case IIO_CHAN_INFO_SCALE:1053 *vals = (int *)st->scale_avail;1054 *type = IIO_VAL_INT_PLUS_NANO;1055 /* Values are stored in a 2D matrix */1056 *length = ARRAY_SIZE(st->scale_avail) * 2;1057 1058 return IIO_AVAIL_LIST;1059 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:1060 *vals = (int *)st->filter_freq_avail;1061 *type = IIO_VAL_FRACTIONAL;1062 *length = ARRAY_SIZE(st->filter_freq_avail) * 2;1063 1064 return IIO_AVAIL_LIST;1065 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:1066 *vals = (int *)st->oversampling_ratio_avail;1067 *type = IIO_VAL_INT;1068 *length = ARRAY_SIZE(st->oversampling_ratio_avail);1069 1070 return IIO_AVAIL_LIST;1071 }1072 1073 return -EINVAL;1074}1075 1076static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask)1077{1078 struct ad7192_state *st = iio_priv(indio_dev);1079 u32 conf = st->conf;1080 int ret;1081 int i;1082 1083 conf &= ~AD7192_CONF_CHAN_MASK;1084 for_each_set_bit(i, scan_mask, 8)1085 conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, i);1086 1087 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf);1088 if (ret < 0)1089 return ret;1090 1091 st->conf = conf;1092 1093 return 0;1094}1095 1096static const struct iio_info ad7192_info = {1097 .read_raw = ad7192_read_raw,1098 .write_raw = ad7192_write_raw,1099 .write_raw_get_fmt = ad7192_write_raw_get_fmt,1100 .read_avail = ad7192_read_avail,1101 .attrs = &ad7192_attribute_group,1102 .validate_trigger = ad_sd_validate_trigger,1103 .update_scan_mode = ad7192_update_scan_mode,1104};1105 1106static const struct iio_info ad7194_info = {1107 .read_raw = ad7192_read_raw,1108 .write_raw = ad7192_write_raw,1109 .write_raw_get_fmt = ad7192_write_raw_get_fmt,1110 .read_avail = ad7192_read_avail,1111 .validate_trigger = ad_sd_validate_trigger,1112};1113 1114static const struct iio_info ad7195_info = {1115 .read_raw = ad7192_read_raw,1116 .write_raw = ad7192_write_raw,1117 .write_raw_get_fmt = ad7192_write_raw_get_fmt,1118 .read_avail = ad7192_read_avail,1119 .attrs = &ad7195_attribute_group,1120 .validate_trigger = ad_sd_validate_trigger,1121 .update_scan_mode = ad7192_update_scan_mode,1122};1123 1124#define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _type, \1125 _mask_all, _mask_type_av, _mask_all_av, _ext_info) \1126 { \1127 .type = (_type), \1128 .differential = ((_channel2) == -1 ? 0 : 1), \1129 .indexed = 1, \1130 .channel = (_channel1), \1131 .channel2 = (_channel2), \1132 .address = (_address), \1133 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \1134 BIT(IIO_CHAN_INFO_OFFSET), \1135 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \1136 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \1137 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \1138 (_mask_all), \1139 .info_mask_shared_by_type_available = (_mask_type_av), \1140 .info_mask_shared_by_all_available = \1141 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \1142 (_mask_all_av), \1143 .ext_info = (_ext_info), \1144 .scan_index = (_si), \1145 .scan_type = { \1146 .sign = 'u', \1147 .realbits = 24, \1148 .storagebits = 32, \1149 .endianness = IIO_BE, \1150 }, \1151 }1152 1153#define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \1154 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, IIO_VOLTAGE, 0, \1155 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)1156 1157#define AD719x_CHANNEL(_si, _channel1, _address) \1158 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \1159 BIT(IIO_CHAN_INFO_SCALE), 0, ad7192_calibsys_ext_info)1160 1161#define AD719x_TEMP_CHANNEL(_si, _address) \1162 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)1163 1164#define AD7193_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \1165 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, \1166 IIO_VOLTAGE, \1167 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \1168 BIT(IIO_CHAN_INFO_SCALE), \1169 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \1170 ad7192_calibsys_ext_info)1171 1172#define AD7193_CHANNEL(_si, _channel1, _address) \1173 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)1174 1175static const struct iio_chan_spec ad7192_channels[] = {1176 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),1177 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),1178 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),1179 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M),1180 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),1181 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),1182 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),1183 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),1184 IIO_CHAN_SOFT_TIMESTAMP(8),1185};1186 1187static const struct iio_chan_spec ad7193_channels[] = {1188 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),1189 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),1190 AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),1191 AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),1192 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),1193 AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),1194 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),1195 AD7193_CHANNEL(7, 2, AD7193_CH_AIN2),1196 AD7193_CHANNEL(8, 3, AD7193_CH_AIN3),1197 AD7193_CHANNEL(9, 4, AD7193_CH_AIN4),1198 AD7193_CHANNEL(10, 5, AD7193_CH_AIN5),1199 AD7193_CHANNEL(11, 6, AD7193_CH_AIN6),1200 AD7193_CHANNEL(12, 7, AD7193_CH_AIN7),1201 AD7193_CHANNEL(13, 8, AD7193_CH_AIN8),1202 IIO_CHAN_SOFT_TIMESTAMP(14),1203};1204 1205static bool ad7194_validate_ain_channel(struct device *dev, u32 ain)1206{1207 return in_range(ain, AD7194_CH_AIN_START, AD7194_CH_AIN_NR);1208}1209 1210static int ad7194_parse_channels(struct iio_dev *indio_dev)1211{1212 struct device *dev = indio_dev->dev.parent;1213 struct iio_chan_spec *ad7194_channels;1214 const struct iio_chan_spec ad7194_chan = AD7193_CHANNEL(0, 0, 0);1215 const struct iio_chan_spec ad7194_chan_diff = AD7193_DIFF_CHANNEL(0, 0, 0, 0);1216 const struct iio_chan_spec ad7194_chan_temp = AD719x_TEMP_CHANNEL(0, 0);1217 const struct iio_chan_spec ad7194_chan_timestamp = IIO_CHAN_SOFT_TIMESTAMP(0);1218 unsigned int num_channels, index = 0;1219 u32 ain[2];1220 int ret;1221 1222 num_channels = device_get_child_node_count(dev);1223 if (num_channels > AD7194_CH_MAX_NR)1224 return dev_err_probe(dev, -EINVAL, "Too many channels: %u\n",1225 num_channels);1226 1227 num_channels += AD7194_CH_BASE_NR;1228 1229 ad7194_channels = devm_kcalloc(dev, num_channels,1230 sizeof(*ad7194_channels), GFP_KERNEL);1231 if (!ad7194_channels)1232 return -ENOMEM;1233 1234 indio_dev->channels = ad7194_channels;1235 indio_dev->num_channels = num_channels;1236 1237 device_for_each_child_node_scoped(dev, child) {1238 ret = fwnode_property_read_u32_array(child, "diff-channels",1239 ain, ARRAY_SIZE(ain));1240 if (ret == 0) {1241 if (!ad7194_validate_ain_channel(dev, ain[0]))1242 return dev_err_probe(dev, -EINVAL,1243 "Invalid AIN channel: %u\n",1244 ain[0]);1245 1246 if (!ad7194_validate_ain_channel(dev, ain[1]))1247 return dev_err_probe(dev, -EINVAL,1248 "Invalid AIN channel: %u\n",1249 ain[1]);1250 1251 *ad7194_channels = ad7194_chan_diff;1252 ad7194_channels->scan_index = index++;1253 ad7194_channels->channel = ain[0];1254 ad7194_channels->channel2 = ain[1];1255 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]);1256 } else {1257 ret = fwnode_property_read_u32(child, "single-channel",1258 &ain[0]);1259 if (ret)1260 return dev_err_probe(dev, ret,1261 "Missing channel property\n");1262 1263 if (!ad7194_validate_ain_channel(dev, ain[0]))1264 return dev_err_probe(dev, -EINVAL,1265 "Invalid AIN channel: %u\n",1266 ain[0]);1267 1268 *ad7194_channels = ad7194_chan;1269 ad7194_channels->scan_index = index++;1270 ad7194_channels->channel = ain[0];1271 ad7194_channels->address = AD7194_CH(ain[0]);1272 }1273 ad7194_channels++;1274 }1275 1276 *ad7194_channels = ad7194_chan_temp;1277 ad7194_channels->scan_index = index++;1278 ad7194_channels->address = AD7194_CH_TEMP;1279 ad7194_channels++;1280 1281 *ad7194_channels = ad7194_chan_timestamp;1282 ad7194_channels->scan_index = index;1283 1284 return 0;1285}1286 1287static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {1288 [ID_AD7190] = {1289 .chip_id = CHIPID_AD7190,1290 .name = "ad7190",1291 .channels = ad7192_channels,1292 .num_channels = ARRAY_SIZE(ad7192_channels),1293 .sigma_delta_info = &ad7192_sigma_delta_info,1294 .info = &ad7192_info,1295 },1296 [ID_AD7192] = {1297 .chip_id = CHIPID_AD7192,1298 .name = "ad7192",1299 .channels = ad7192_channels,1300 .num_channels = ARRAY_SIZE(ad7192_channels),1301 .sigma_delta_info = &ad7192_sigma_delta_info,1302 .info = &ad7192_info,1303 },1304 [ID_AD7193] = {1305 .chip_id = CHIPID_AD7193,1306 .name = "ad7193",1307 .channels = ad7193_channels,1308 .num_channels = ARRAY_SIZE(ad7193_channels),1309 .sigma_delta_info = &ad7192_sigma_delta_info,1310 .info = &ad7192_info,1311 },1312 [ID_AD7194] = {1313 .chip_id = CHIPID_AD7194,1314 .name = "ad7194",1315 .info = &ad7194_info,1316 .sigma_delta_info = &ad7194_sigma_delta_info,1317 .parse_channels = ad7194_parse_channels,1318 },1319 [ID_AD7195] = {1320 .chip_id = CHIPID_AD7195,1321 .name = "ad7195",1322 .channels = ad7192_channels,1323 .num_channels = ARRAY_SIZE(ad7192_channels),1324 .sigma_delta_info = &ad7192_sigma_delta_info,1325 .info = &ad7195_info,1326 },1327};1328 1329static int ad7192_probe(struct spi_device *spi)1330{1331 struct device *dev = &spi->dev;1332 struct ad7192_state *st;1333 struct iio_dev *indio_dev;1334 int ret, avdd_mv;1335 1336 if (!spi->irq)1337 return dev_err_probe(dev, -ENODEV, "Failed to get IRQ\n");1338 1339 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));1340 if (!indio_dev)1341 return -ENOMEM;1342 1343 st = iio_priv(indio_dev);1344 1345 mutex_init(&st->lock);1346 1347 /*1348 * Regulator aincom is optional to maintain compatibility with older DT.1349 * Newer firmware should provide a zero volt fixed supply if wired to1350 * ground.1351 */1352 ret = devm_regulator_get_enable_read_voltage(dev, "aincom");1353 if (ret < 0 && ret != -ENODEV)1354 return dev_err_probe(dev, ret, "Failed to get AINCOM voltage\n");1355 1356 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI;1357 1358 /* AVDD can optionally be used as reference voltage */1359 ret = devm_regulator_get_enable_read_voltage(dev, "avdd");1360 if (ret == -ENODEV || ret == -EINVAL) {1361 int ret2;1362 1363 /*1364 * We get -EINVAL if avdd is a supply with unknown voltage. We1365 * still need to enable it since it is also a power supply.1366 */1367 ret2 = devm_regulator_get_enable(dev, "avdd");1368 if (ret2)1369 return dev_err_probe(dev, ret2,1370 "Failed to enable AVDD supply\n");1371 } else if (ret < 0) {1372 return dev_err_probe(dev, ret, "Failed to get AVDD voltage\n");1373 }1374 1375 avdd_mv = ret == -ENODEV || ret == -EINVAL ? 0 : ret / MILLI;1376 1377 ret = devm_regulator_get_enable(dev, "dvdd");1378 if (ret)1379 return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n");1380 1381 /*1382 * This is either REFIN1 or REFIN2 depending on adi,refin2-pins-enable.1383 * If this supply is not present, fall back to AVDD as reference.1384 */1385 ret = devm_regulator_get_enable_read_voltage(dev, "vref");1386 if (ret == -ENODEV) {1387 if (avdd_mv == 0)1388 return dev_err_probe(dev, -ENODEV,1389 "No reference voltage available\n");1390 } else if (ret < 0) {1391 return ret;1392 }1393 1394 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI;1395 1396 st->chip_info = spi_get_device_match_data(spi);1397 indio_dev->name = st->chip_info->name;1398 indio_dev->modes = INDIO_DIRECT_MODE;1399 indio_dev->info = st->chip_info->info;1400 if (st->chip_info->parse_channels) {1401 ret = st->chip_info->parse_channels(indio_dev);1402 if (ret)1403 return ret;1404 } else {1405 indio_dev->channels = st->chip_info->channels;1406 indio_dev->num_channels = st->chip_info->num_channels;1407 }1408 1409 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info);1410 if (ret)1411 return ret;1412 1413 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);1414 if (ret)1415 return ret;1416 1417 ret = ad7192_clock_setup(st);1418 if (ret)1419 return ret;1420 1421 ret = ad7192_setup(indio_dev, dev);1422 if (ret)1423 return ret;1424 1425 return devm_iio_device_register(dev, indio_dev);1426}1427 1428static const struct of_device_id ad7192_of_match[] = {1429 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },1430 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },1431 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },1432 { .compatible = "adi,ad7194", .data = &ad7192_chip_info_tbl[ID_AD7194] },1433 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },1434 { }1435};1436MODULE_DEVICE_TABLE(of, ad7192_of_match);1437 1438static const struct spi_device_id ad7192_ids[] = {1439 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] },1440 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] },1441 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] },1442 { "ad7194", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7194] },1443 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] },1444 { }1445};1446MODULE_DEVICE_TABLE(spi, ad7192_ids);1447 1448static struct spi_driver ad7192_driver = {1449 .driver = {1450 .name = "ad7192",1451 .of_match_table = ad7192_of_match,1452 },1453 .probe = ad7192_probe,1454 .id_table = ad7192_ids,1455};1456module_spi_driver(ad7192_driver);1457 1458MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");1459MODULE_DESCRIPTION("Analog Devices AD7192 and similar ADC");1460MODULE_LICENSE("GPL v2");1461MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA);1462