1215 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Analog Devices AD738x Simultaneous Sampling SAR ADCs4 *5 * Copyright 2017 Analog Devices Inc.6 * Copyright 2024 BayLibre, SAS7 *8 * Datasheets of supported parts:9 * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf10 * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf11 * ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386-7387-7388.pdf12 * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf13 * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf14 * ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384-4.pdf15 * ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7386-4-7387-4-7388-4.pdf16 */17 18#include <linux/align.h>19#include <linux/bitfield.h>20#include <linux/bitops.h>21#include <linux/cleanup.h>22#include <linux/device.h>23#include <linux/err.h>24#include <linux/kernel.h>25#include <linux/module.h>26#include <linux/regmap.h>27#include <linux/regulator/consumer.h>28#include <linux/slab.h>29#include <linux/spi/spi.h>30 31#include <linux/iio/buffer.h>32#include <linux/iio/iio.h>33#include <linux/iio/trigger_consumer.h>34#include <linux/iio/triggered_buffer.h>35 36#define MAX_NUM_CHANNELS 837/* 2.5V internal reference voltage */38#define AD7380_INTERNAL_REF_MV 250039 40/* reading and writing registers is more reliable at lower than max speed */41#define AD7380_REG_WR_SPEED_HZ 1000000042 43#define AD7380_REG_WR BIT(15)44#define AD7380_REG_REGADDR GENMASK(14, 12)45#define AD7380_REG_DATA GENMASK(11, 0)46 47#define AD7380_REG_ADDR_NOP 0x048#define AD7380_REG_ADDR_CONFIG1 0x149#define AD7380_REG_ADDR_CONFIG2 0x250#define AD7380_REG_ADDR_ALERT 0x351#define AD7380_REG_ADDR_ALERT_LOW_TH 0x452#define AD7380_REG_ADDR_ALERT_HIGH_TH 0x553 54#define AD7380_CONFIG1_CH BIT(11)55#define AD7380_CONFIG1_SEQ BIT(10)56#define AD7380_CONFIG1_OS_MODE BIT(9)57#define AD7380_CONFIG1_OSR GENMASK(8, 6)58#define AD7380_CONFIG1_CRC_W BIT(5)59#define AD7380_CONFIG1_CRC_R BIT(4)60#define AD7380_CONFIG1_ALERTEN BIT(3)61#define AD7380_CONFIG1_RES BIT(2)62#define AD7380_CONFIG1_REFSEL BIT(1)63#define AD7380_CONFIG1_PMODE BIT(0)64 65#define AD7380_CONFIG2_SDO2 GENMASK(9, 8)66#define AD7380_CONFIG2_SDO BIT(8)67#define AD7380_CONFIG2_RESET GENMASK(7, 0)68 69#define AD7380_CONFIG2_RESET_SOFT 0x3C70#define AD7380_CONFIG2_RESET_HARD 0xFF71 72#define AD7380_ALERT_LOW_TH GENMASK(11, 0)73#define AD7380_ALERT_HIGH_TH GENMASK(11, 0)74 75#define T_CONVERT_NS 190 /* conversion time */76#define T_CONVERT_0_NS 10 /* 1st conversion start time (oversampling) */77#define T_CONVERT_X_NS 500 /* xth conversion start time (oversampling) */78#define T_POWERUP_US 5000 /* Power up */79 80struct ad7380_timing_specs {81 const unsigned int t_csh_ns; /* CS minimum high time */82};83 84struct ad7380_chip_info {85 const char *name;86 const struct iio_chan_spec *channels;87 unsigned int num_channels;88 unsigned int num_simult_channels;89 bool has_mux;90 const char * const *supplies;91 unsigned int num_supplies;92 bool external_ref_only;93 const char * const *vcm_supplies;94 unsigned int num_vcm_supplies;95 const unsigned long *available_scan_masks;96 const struct ad7380_timing_specs *timing_specs;97};98 99enum {100 AD7380_SCAN_TYPE_NORMAL,101 AD7380_SCAN_TYPE_RESOLUTION_BOOST,102};103 104/* Extended scan types for 12-bit unsigned chips. */105static const struct iio_scan_type ad7380_scan_type_12_u[] = {106 [AD7380_SCAN_TYPE_NORMAL] = {107 .sign = 'u',108 .realbits = 12,109 .storagebits = 16,110 .endianness = IIO_CPU,111 },112 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {113 .sign = 'u',114 .realbits = 14,115 .storagebits = 16,116 .endianness = IIO_CPU,117 },118};119 120/* Extended scan types for 14-bit signed chips. */121static const struct iio_scan_type ad7380_scan_type_14_s[] = {122 [AD7380_SCAN_TYPE_NORMAL] = {123 .sign = 's',124 .realbits = 14,125 .storagebits = 16,126 .endianness = IIO_CPU,127 },128 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {129 .sign = 's',130 .realbits = 16,131 .storagebits = 16,132 .endianness = IIO_CPU,133 },134};135 136/* Extended scan types for 14-bit unsigned chips. */137static const struct iio_scan_type ad7380_scan_type_14_u[] = {138 [AD7380_SCAN_TYPE_NORMAL] = {139 .sign = 'u',140 .realbits = 14,141 .storagebits = 16,142 .endianness = IIO_CPU,143 },144 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {145 .sign = 'u',146 .realbits = 16,147 .storagebits = 16,148 .endianness = IIO_CPU,149 },150};151 152/* Extended scan types for 16-bit signed_chips. */153static const struct iio_scan_type ad7380_scan_type_16_s[] = {154 [AD7380_SCAN_TYPE_NORMAL] = {155 .sign = 's',156 .realbits = 16,157 .storagebits = 16,158 .endianness = IIO_CPU,159 },160 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {161 .sign = 's',162 .realbits = 18,163 .storagebits = 32,164 .endianness = IIO_CPU,165 },166};167 168/* Extended scan types for 16-bit unsigned chips. */169static const struct iio_scan_type ad7380_scan_type_16_u[] = {170 [AD7380_SCAN_TYPE_NORMAL] = {171 .sign = 'u',172 .realbits = 16,173 .storagebits = 16,174 .endianness = IIO_CPU,175 },176 [AD7380_SCAN_TYPE_RESOLUTION_BOOST] = {177 .sign = 'u',178 .realbits = 18,179 .storagebits = 32,180 .endianness = IIO_CPU,181 },182};183 184#define AD7380_CHANNEL(index, bits, diff, sign) { \185 .type = IIO_VOLTAGE, \186 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \187 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \188 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \189 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \190 .info_mask_shared_by_type_available = \191 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \192 .indexed = 1, \193 .differential = (diff), \194 .channel = (diff) ? (2 * (index)) : (index), \195 .channel2 = (diff) ? (2 * (index) + 1) : 0, \196 .scan_index = (index), \197 .has_ext_scan_type = 1, \198 .ext_scan_type = ad7380_scan_type_##bits##_##sign, \199 .num_ext_scan_type = ARRAY_SIZE(ad7380_scan_type_##bits##_##sign), \200}201 202#define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \203static const struct iio_chan_spec name[] = { \204 AD7380_CHANNEL(0, bits, diff, sign), \205 AD7380_CHANNEL(1, bits, diff, sign), \206 IIO_CHAN_SOFT_TIMESTAMP(2), \207}208 209#define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \210static const struct iio_chan_spec name[] = { \211 AD7380_CHANNEL(0, bits, diff, sign), \212 AD7380_CHANNEL(1, bits, diff, sign), \213 AD7380_CHANNEL(2, bits, diff, sign), \214 AD7380_CHANNEL(3, bits, diff, sign), \215 IIO_CHAN_SOFT_TIMESTAMP(4), \216}217 218#define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \219static const struct iio_chan_spec name[] = { \220 AD7380_CHANNEL(0, bits, diff, sign), \221 AD7380_CHANNEL(1, bits, diff, sign), \222 AD7380_CHANNEL(2, bits, diff, sign), \223 AD7380_CHANNEL(3, bits, diff, sign), \224 AD7380_CHANNEL(4, bits, diff, sign), \225 AD7380_CHANNEL(5, bits, diff, sign), \226 AD7380_CHANNEL(6, bits, diff, sign), \227 AD7380_CHANNEL(7, bits, diff, sign), \228 IIO_CHAN_SOFT_TIMESTAMP(8), \229}230 231/* fully differential */232DEFINE_AD7380_2_CHANNEL(ad7380_channels, 16, 1, s);233DEFINE_AD7380_2_CHANNEL(ad7381_channels, 14, 1, s);234DEFINE_AD7380_4_CHANNEL(ad7380_4_channels, 16, 1, s);235DEFINE_AD7380_4_CHANNEL(ad7381_4_channels, 14, 1, s);236/* pseudo differential */237DEFINE_AD7380_2_CHANNEL(ad7383_channels, 16, 0, s);238DEFINE_AD7380_2_CHANNEL(ad7384_channels, 14, 0, s);239DEFINE_AD7380_4_CHANNEL(ad7383_4_channels, 16, 0, s);240DEFINE_AD7380_4_CHANNEL(ad7384_4_channels, 14, 0, s);241 242/* Single ended */243DEFINE_AD7380_4_CHANNEL(ad7386_channels, 16, 0, u);244DEFINE_AD7380_4_CHANNEL(ad7387_channels, 14, 0, u);245DEFINE_AD7380_4_CHANNEL(ad7388_channels, 12, 0, u);246DEFINE_AD7380_8_CHANNEL(ad7386_4_channels, 16, 0, u);247DEFINE_AD7380_8_CHANNEL(ad7387_4_channels, 14, 0, u);248DEFINE_AD7380_8_CHANNEL(ad7388_4_channels, 12, 0, u);249 250static const char * const ad7380_supplies[] = {251 "vcc", "vlogic",252};253 254static const char * const ad7380_2_channel_vcm_supplies[] = {255 "aina", "ainb",256};257 258static const char * const ad7380_4_channel_vcm_supplies[] = {259 "aina", "ainb", "ainc", "aind",260};261 262/* Since this is simultaneous sampling, we don't allow individual channels. */263static const unsigned long ad7380_2_channel_scan_masks[] = {264 GENMASK(1, 0),265 0266};267 268static const unsigned long ad7380_4_channel_scan_masks[] = {269 GENMASK(3, 0),270 0271};272 273/*274 * Single ended parts have a 2:1 multiplexer in front of each ADC.275 *276 * From an IIO point of view, all inputs are exported, i.e ad7386/7/8277 * export 4 channels and ad7386-4/7-4/8-4 export 8 channels.278 *279 * Inputs AinX0 of multiplexers correspond to the first half of IIO channels280 * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or281 * 4-7). Example for AD7386/7/8 (2 channels parts):282 *283 * IIO | AD7386/7/8284 * | +----------------------------285 * | | _____ ______286 * | | | | | |287 * voltage0 | AinA0 --|--->| | | |288 * | | | mux |----->| ADCA |---289 * voltage2 | AinA1 --|--->| | | |290 * | | |_____| |_____ |291 * | | _____ ______292 * | | | | | |293 * voltage1 | AinB0 --|--->| | | |294 * | | | mux |----->| ADCB |---295 * voltage3 | AinB1 --|--->| | | |296 * | | |_____| |______|297 * | |298 * | +----------------------------299 *300 * Since this is simultaneous sampling for AinX0 OR AinX1 we have two separate301 * scan masks.302 * When sequencer mode is enabled, chip automatically cycles through303 * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all304 * channels, at the cost of an extra read, thus dividing the maximum rate by305 * two.306 */307enum {308 AD7380_SCAN_MASK_CH_0,309 AD7380_SCAN_MASK_CH_1,310 AD7380_SCAN_MASK_SEQ,311};312 313static const unsigned long ad7380_2x2_channel_scan_masks[] = {314 [AD7380_SCAN_MASK_CH_0] = GENMASK(1, 0),315 [AD7380_SCAN_MASK_CH_1] = GENMASK(3, 2),316 [AD7380_SCAN_MASK_SEQ] = GENMASK(3, 0),317 0318};319 320static const unsigned long ad7380_2x4_channel_scan_masks[] = {321 [AD7380_SCAN_MASK_CH_0] = GENMASK(3, 0),322 [AD7380_SCAN_MASK_CH_1] = GENMASK(7, 4),323 [AD7380_SCAN_MASK_SEQ] = GENMASK(7, 0),324 0325};326 327static const struct ad7380_timing_specs ad7380_timing = {328 .t_csh_ns = 10,329};330 331static const struct ad7380_timing_specs ad7380_4_timing = {332 .t_csh_ns = 20,333};334 335/*336 * Available oversampling ratios. The indices correspond with the bit value337 * expected by the chip. The available ratios depend on the averaging mode,338 * only normal averaging is supported for now.339 */340static const int ad7380_oversampling_ratios[] = {341 1, 2, 4, 8, 16, 32,342};343 344static const struct ad7380_chip_info ad7380_chip_info = {345 .name = "ad7380",346 .channels = ad7380_channels,347 .num_channels = ARRAY_SIZE(ad7380_channels),348 .num_simult_channels = 2,349 .supplies = ad7380_supplies,350 .num_supplies = ARRAY_SIZE(ad7380_supplies),351 .available_scan_masks = ad7380_2_channel_scan_masks,352 .timing_specs = &ad7380_timing,353};354 355static const struct ad7380_chip_info ad7381_chip_info = {356 .name = "ad7381",357 .channels = ad7381_channels,358 .num_channels = ARRAY_SIZE(ad7381_channels),359 .num_simult_channels = 2,360 .supplies = ad7380_supplies,361 .num_supplies = ARRAY_SIZE(ad7380_supplies),362 .available_scan_masks = ad7380_2_channel_scan_masks,363 .timing_specs = &ad7380_timing,364};365 366static const struct ad7380_chip_info ad7383_chip_info = {367 .name = "ad7383",368 .channels = ad7383_channels,369 .num_channels = ARRAY_SIZE(ad7383_channels),370 .num_simult_channels = 2,371 .supplies = ad7380_supplies,372 .num_supplies = ARRAY_SIZE(ad7380_supplies),373 .vcm_supplies = ad7380_2_channel_vcm_supplies,374 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies),375 .available_scan_masks = ad7380_2_channel_scan_masks,376 .timing_specs = &ad7380_timing,377};378 379static const struct ad7380_chip_info ad7384_chip_info = {380 .name = "ad7384",381 .channels = ad7384_channels,382 .num_channels = ARRAY_SIZE(ad7384_channels),383 .num_simult_channels = 2,384 .supplies = ad7380_supplies,385 .num_supplies = ARRAY_SIZE(ad7380_supplies),386 .vcm_supplies = ad7380_2_channel_vcm_supplies,387 .num_vcm_supplies = ARRAY_SIZE(ad7380_2_channel_vcm_supplies),388 .available_scan_masks = ad7380_2_channel_scan_masks,389 .timing_specs = &ad7380_timing,390};391 392static const struct ad7380_chip_info ad7386_chip_info = {393 .name = "ad7386",394 .channels = ad7386_channels,395 .num_channels = ARRAY_SIZE(ad7386_channels),396 .num_simult_channels = 2,397 .supplies = ad7380_supplies,398 .num_supplies = ARRAY_SIZE(ad7380_supplies),399 .has_mux = true,400 .available_scan_masks = ad7380_2x2_channel_scan_masks,401 .timing_specs = &ad7380_timing,402};403 404static const struct ad7380_chip_info ad7387_chip_info = {405 .name = "ad7387",406 .channels = ad7387_channels,407 .num_channels = ARRAY_SIZE(ad7387_channels),408 .num_simult_channels = 2,409 .supplies = ad7380_supplies,410 .num_supplies = ARRAY_SIZE(ad7380_supplies),411 .has_mux = true,412 .available_scan_masks = ad7380_2x2_channel_scan_masks,413 .timing_specs = &ad7380_timing,414};415 416static const struct ad7380_chip_info ad7388_chip_info = {417 .name = "ad7388",418 .channels = ad7388_channels,419 .num_channels = ARRAY_SIZE(ad7388_channels),420 .num_simult_channels = 2,421 .supplies = ad7380_supplies,422 .num_supplies = ARRAY_SIZE(ad7380_supplies),423 .has_mux = true,424 .available_scan_masks = ad7380_2x2_channel_scan_masks,425 .timing_specs = &ad7380_timing,426};427 428static const struct ad7380_chip_info ad7380_4_chip_info = {429 .name = "ad7380-4",430 .channels = ad7380_4_channels,431 .num_channels = ARRAY_SIZE(ad7380_4_channels),432 .num_simult_channels = 4,433 .supplies = ad7380_supplies,434 .num_supplies = ARRAY_SIZE(ad7380_supplies),435 .external_ref_only = true,436 .available_scan_masks = ad7380_4_channel_scan_masks,437 .timing_specs = &ad7380_4_timing,438};439 440static const struct ad7380_chip_info ad7381_4_chip_info = {441 .name = "ad7381-4",442 .channels = ad7381_4_channels,443 .num_channels = ARRAY_SIZE(ad7381_4_channels),444 .num_simult_channels = 4,445 .supplies = ad7380_supplies,446 .num_supplies = ARRAY_SIZE(ad7380_supplies),447 .available_scan_masks = ad7380_4_channel_scan_masks,448 .timing_specs = &ad7380_4_timing,449};450 451static const struct ad7380_chip_info ad7383_4_chip_info = {452 .name = "ad7383-4",453 .channels = ad7383_4_channels,454 .num_channels = ARRAY_SIZE(ad7383_4_channels),455 .num_simult_channels = 4,456 .supplies = ad7380_supplies,457 .num_supplies = ARRAY_SIZE(ad7380_supplies),458 .vcm_supplies = ad7380_4_channel_vcm_supplies,459 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies),460 .available_scan_masks = ad7380_4_channel_scan_masks,461 .timing_specs = &ad7380_4_timing,462};463 464static const struct ad7380_chip_info ad7384_4_chip_info = {465 .name = "ad7384-4",466 .channels = ad7384_4_channels,467 .num_channels = ARRAY_SIZE(ad7384_4_channels),468 .num_simult_channels = 4,469 .supplies = ad7380_supplies,470 .num_supplies = ARRAY_SIZE(ad7380_supplies),471 .vcm_supplies = ad7380_4_channel_vcm_supplies,472 .num_vcm_supplies = ARRAY_SIZE(ad7380_4_channel_vcm_supplies),473 .available_scan_masks = ad7380_4_channel_scan_masks,474 .timing_specs = &ad7380_4_timing,475};476 477static const struct ad7380_chip_info ad7386_4_chip_info = {478 .name = "ad7386-4",479 .channels = ad7386_4_channels,480 .num_channels = ARRAY_SIZE(ad7386_4_channels),481 .num_simult_channels = 4,482 .supplies = ad7380_supplies,483 .num_supplies = ARRAY_SIZE(ad7380_supplies),484 .has_mux = true,485 .available_scan_masks = ad7380_2x4_channel_scan_masks,486 .timing_specs = &ad7380_4_timing,487};488 489static const struct ad7380_chip_info ad7387_4_chip_info = {490 .name = "ad7387-4",491 .channels = ad7387_4_channels,492 .num_channels = ARRAY_SIZE(ad7387_4_channels),493 .num_simult_channels = 4,494 .supplies = ad7380_supplies,495 .num_supplies = ARRAY_SIZE(ad7380_supplies),496 .has_mux = true,497 .available_scan_masks = ad7380_2x4_channel_scan_masks,498 .timing_specs = &ad7380_4_timing,499};500 501static const struct ad7380_chip_info ad7388_4_chip_info = {502 .name = "ad7388-4",503 .channels = ad7388_4_channels,504 .num_channels = ARRAY_SIZE(ad7388_4_channels),505 .num_simult_channels = 4,506 .supplies = ad7380_supplies,507 .num_supplies = ARRAY_SIZE(ad7380_supplies),508 .has_mux = true,509 .available_scan_masks = ad7380_2x4_channel_scan_masks,510 .timing_specs = &ad7380_4_timing,511};512 513struct ad7380_state {514 const struct ad7380_chip_info *chip_info;515 struct spi_device *spi;516 struct regmap *regmap;517 unsigned int oversampling_ratio;518 bool resolution_boost_enabled;519 unsigned int ch;520 bool seq;521 unsigned int vref_mv;522 unsigned int vcm_mv[MAX_NUM_CHANNELS];523 /* xfers, message an buffer for reading sample data */524 struct spi_transfer normal_xfer[2];525 struct spi_message normal_msg;526 struct spi_transfer seq_xfer[4];527 struct spi_message seq_msg;528 /*529 * DMA (thus cache coherency maintenance) requires the transfer buffers530 * to live in their own cache lines.531 *532 * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and533 * one 64-bit aligned 64-bit timestamp.534 */535 u8 scan_data[ALIGN(MAX_NUM_CHANNELS * sizeof(u32), sizeof(s64))536 + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);537 /* buffers for reading/writing registers */538 u16 tx;539 u16 rx;540};541 542static int ad7380_regmap_reg_write(void *context, unsigned int reg,543 unsigned int val)544{545 struct ad7380_state *st = context;546 struct spi_transfer xfer = {547 .speed_hz = AD7380_REG_WR_SPEED_HZ,548 .bits_per_word = 16,549 .len = 2,550 .tx_buf = &st->tx,551 };552 553 st->tx = FIELD_PREP(AD7380_REG_WR, 1) |554 FIELD_PREP(AD7380_REG_REGADDR, reg) |555 FIELD_PREP(AD7380_REG_DATA, val);556 557 return spi_sync_transfer(st->spi, &xfer, 1);558}559 560static int ad7380_regmap_reg_read(void *context, unsigned int reg,561 unsigned int *val)562{563 struct ad7380_state *st = context;564 struct spi_transfer xfers[] = {565 {566 .speed_hz = AD7380_REG_WR_SPEED_HZ,567 .bits_per_word = 16,568 .len = 2,569 .tx_buf = &st->tx,570 .cs_change = 1,571 .cs_change_delay = {572 .value = st->chip_info->timing_specs->t_csh_ns,573 .unit = SPI_DELAY_UNIT_NSECS,574 },575 }, {576 .speed_hz = AD7380_REG_WR_SPEED_HZ,577 .bits_per_word = 16,578 .len = 2,579 .rx_buf = &st->rx,580 },581 };582 int ret;583 584 st->tx = FIELD_PREP(AD7380_REG_WR, 0) |585 FIELD_PREP(AD7380_REG_REGADDR, reg) |586 FIELD_PREP(AD7380_REG_DATA, 0);587 588 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));589 if (ret < 0)590 return ret;591 592 *val = FIELD_GET(AD7380_REG_DATA, st->rx);593 594 return 0;595}596 597static const struct regmap_config ad7380_regmap_config = {598 .reg_bits = 3,599 .val_bits = 12,600 .reg_read = ad7380_regmap_reg_read,601 .reg_write = ad7380_regmap_reg_write,602 .max_register = AD7380_REG_ADDR_ALERT_HIGH_TH,603 .can_sleep = true,604};605 606static int ad7380_debugfs_reg_access(struct iio_dev *indio_dev, u32 reg,607 u32 writeval, u32 *readval)608{609 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {610 struct ad7380_state *st = iio_priv(indio_dev);611 612 if (readval)613 return regmap_read(st->regmap, reg, readval);614 else615 return regmap_write(st->regmap, reg, writeval);616 }617 unreachable();618}619 620/*621 * When switching channel, the ADC require an additional settling time.622 * According to the datasheet, data is value on the third CS low. We already623 * have an extra toggle before each read (either direct reads or buffered reads)624 * to sample correct data, so we just add a single CS toggle at the end of the625 * register write.626 */627static int ad7380_set_ch(struct ad7380_state *st, unsigned int ch)628{629 struct spi_transfer xfer = {630 .delay = {631 .value = T_CONVERT_NS,632 .unit = SPI_DELAY_UNIT_NSECS,633 }634 };635 int ret;636 637 if (st->ch == ch)638 return 0;639 640 ret = regmap_update_bits(st->regmap,641 AD7380_REG_ADDR_CONFIG1,642 AD7380_CONFIG1_CH,643 FIELD_PREP(AD7380_CONFIG1_CH, ch));644 645 if (ret)646 return ret;647 648 st->ch = ch;649 650 if (st->oversampling_ratio > 1)651 xfer.delay.value = T_CONVERT_0_NS +652 T_CONVERT_X_NS * (st->oversampling_ratio - 1);653 654 return spi_sync_transfer(st->spi, &xfer, 1);655}656 657/**658 * ad7380_update_xfers - update the SPI transfers base on the current scan type659 * @st: device instance specific state660 * @scan_type: current scan type661 */662static void ad7380_update_xfers(struct ad7380_state *st,663 const struct iio_scan_type *scan_type)664{665 struct spi_transfer *xfer = st->seq ? st->seq_xfer : st->normal_xfer;666 unsigned int t_convert = T_CONVERT_NS;667 668 /*669 * In the case of oversampling, conversion time is higher than in normal670 * mode. Technically T_CONVERT_X_NS is lower for some chips, but we use671 * the maximum value for simplicity for now.672 */673 if (st->oversampling_ratio > 1)674 t_convert = T_CONVERT_0_NS + T_CONVERT_X_NS *675 (st->oversampling_ratio - 1);676 677 if (st->seq) {678 xfer[0].delay.value = xfer[1].delay.value = t_convert;679 xfer[0].delay.unit = xfer[1].delay.unit = SPI_DELAY_UNIT_NSECS;680 xfer[2].bits_per_word = xfer[3].bits_per_word =681 scan_type->realbits;682 xfer[2].len = xfer[3].len =683 BITS_TO_BYTES(scan_type->storagebits) *684 st->chip_info->num_simult_channels;685 xfer[3].rx_buf = xfer[2].rx_buf + xfer[2].len;686 /* Additional delay required here when oversampling is enabled */687 if (st->oversampling_ratio > 1)688 xfer[2].delay.value = t_convert;689 else690 xfer[2].delay.value = 0;691 xfer[2].delay.unit = SPI_DELAY_UNIT_NSECS;692 } else {693 xfer[0].delay.value = t_convert;694 xfer[0].delay.unit = SPI_DELAY_UNIT_NSECS;695 xfer[1].bits_per_word = scan_type->realbits;696 xfer[1].len = BITS_TO_BYTES(scan_type->storagebits) *697 st->chip_info->num_simult_channels;698 }699}700 701static int ad7380_triggered_buffer_preenable(struct iio_dev *indio_dev)702{703 struct ad7380_state *st = iio_priv(indio_dev);704 const struct iio_scan_type *scan_type;705 struct spi_message *msg = &st->normal_msg;706 707 /*708 * Currently, we always read all channels at the same time. The scan_type709 * is the same for all channels, so we just pass the first channel.710 */711 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]);712 if (IS_ERR(scan_type))713 return PTR_ERR(scan_type);714 715 if (st->chip_info->has_mux) {716 unsigned int index;717 int ret;718 719 /*720 * Depending on the requested scan_mask and current state,721 * we need to either change CH bit, or enable sequencer mode722 * to sample correct data.723 * Sequencer mode is enabled if active mask corresponds to all724 * IIO channels enabled. Otherwise, CH bit is set.725 */726 ret = iio_active_scan_mask_index(indio_dev);727 if (ret < 0)728 return ret;729 730 index = ret;731 if (index == AD7380_SCAN_MASK_SEQ) {732 ret = regmap_update_bits(st->regmap,733 AD7380_REG_ADDR_CONFIG1,734 AD7380_CONFIG1_SEQ,735 FIELD_PREP(AD7380_CONFIG1_SEQ, 1));736 if (ret)737 return ret;738 msg = &st->seq_msg;739 st->seq = true;740 } else {741 ret = ad7380_set_ch(st, index);742 if (ret)743 return ret;744 }745 746 }747 748 ad7380_update_xfers(st, scan_type);749 750 return spi_optimize_message(st->spi, msg);751}752 753static int ad7380_triggered_buffer_postdisable(struct iio_dev *indio_dev)754{755 struct ad7380_state *st = iio_priv(indio_dev);756 struct spi_message *msg = &st->normal_msg;757 int ret;758 759 if (st->seq) {760 ret = regmap_update_bits(st->regmap,761 AD7380_REG_ADDR_CONFIG1,762 AD7380_CONFIG1_SEQ,763 FIELD_PREP(AD7380_CONFIG1_SEQ, 0));764 if (ret)765 return ret;766 767 msg = &st->seq_msg;768 st->seq = false;769 }770 771 spi_unoptimize_message(msg);772 773 return 0;774}775 776static const struct iio_buffer_setup_ops ad7380_buffer_setup_ops = {777 .preenable = ad7380_triggered_buffer_preenable,778 .postdisable = ad7380_triggered_buffer_postdisable,779};780 781static irqreturn_t ad7380_trigger_handler(int irq, void *p)782{783 struct iio_poll_func *pf = p;784 struct iio_dev *indio_dev = pf->indio_dev;785 struct ad7380_state *st = iio_priv(indio_dev);786 struct spi_message *msg = st->seq ? &st->seq_msg : &st->normal_msg;787 int ret;788 789 ret = spi_sync(st->spi, msg);790 if (ret)791 goto out;792 793 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_data,794 pf->timestamp);795 796out:797 iio_trigger_notify_done(indio_dev->trig);798 799 return IRQ_HANDLED;800}801 802static int ad7380_read_direct(struct ad7380_state *st, unsigned int scan_index,803 const struct iio_scan_type *scan_type, int *val)804{805 unsigned int index = scan_index;806 int ret;807 808 if (st->chip_info->has_mux) {809 unsigned int ch = 0;810 811 if (index >= st->chip_info->num_simult_channels) {812 index -= st->chip_info->num_simult_channels;813 ch = 1;814 }815 816 ret = ad7380_set_ch(st, ch);817 if (ret)818 return ret;819 }820 821 ad7380_update_xfers(st, scan_type);822 823 ret = spi_sync(st->spi, &st->normal_msg);824 if (ret < 0)825 return ret;826 827 if (scan_type->storagebits > 16) {828 if (scan_type->sign == 's')829 *val = sign_extend32(*(u32 *)(st->scan_data + 4 * index),830 scan_type->realbits - 1);831 else832 *val = *(u32 *)(st->scan_data + 4 * index) &833 GENMASK(scan_type->realbits - 1, 0);834 } else {835 if (scan_type->sign == 's')836 *val = sign_extend32(*(u16 *)(st->scan_data + 2 * index),837 scan_type->realbits - 1);838 else839 *val = *(u16 *)(st->scan_data + 2 * index) &840 GENMASK(scan_type->realbits - 1, 0);841 }842 843 return IIO_VAL_INT;844}845 846static int ad7380_read_raw(struct iio_dev *indio_dev,847 struct iio_chan_spec const *chan,848 int *val, int *val2, long info)849{850 struct ad7380_state *st = iio_priv(indio_dev);851 const struct iio_scan_type *scan_type;852 853 scan_type = iio_get_current_scan_type(indio_dev, chan);854 855 if (IS_ERR(scan_type))856 return PTR_ERR(scan_type);857 858 switch (info) {859 case IIO_CHAN_INFO_RAW:860 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {861 return ad7380_read_direct(st, chan->scan_index,862 scan_type, val);863 }864 unreachable();865 case IIO_CHAN_INFO_SCALE:866 /*867 * According to the datasheet, the LSB size is:868 * * (2 × VREF) / 2^N, for differential chips869 * * VREF / 2^N, for pseudo-differential chips870 * where N is the ADC resolution (i.e realbits)871 */872 *val = st->vref_mv;873 *val2 = scan_type->realbits - chan->differential;874 875 return IIO_VAL_FRACTIONAL_LOG2;876 case IIO_CHAN_INFO_OFFSET:877 /*878 * According to IIO ABI, offset is applied before scale,879 * so offset is: vcm_mv / scale880 */881 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits)882 / st->vref_mv;883 884 return IIO_VAL_INT;885 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:886 *val = st->oversampling_ratio;887 888 return IIO_VAL_INT;889 default:890 return -EINVAL;891 }892}893 894static int ad7380_read_avail(struct iio_dev *indio_dev,895 struct iio_chan_spec const *chan,896 const int **vals, int *type, int *length,897 long mask)898{899 switch (mask) {900 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:901 *vals = ad7380_oversampling_ratios;902 *length = ARRAY_SIZE(ad7380_oversampling_ratios);903 *type = IIO_VAL_INT;904 905 return IIO_AVAIL_LIST;906 default:907 return -EINVAL;908 }909}910 911/**912 * ad7380_osr_to_regval - convert ratio to OSR register value913 * @ratio: ratio to check914 *915 * Check if ratio is present in the list of available ratios and return the916 * corresponding value that needs to be written to the register to select that917 * ratio.918 *919 * Returns: register value (0 to 7) or -EINVAL if there is not an exact match920 */921static int ad7380_osr_to_regval(int ratio)922{923 int i;924 925 for (i = 0; i < ARRAY_SIZE(ad7380_oversampling_ratios); i++) {926 if (ratio == ad7380_oversampling_ratios[i])927 return i;928 }929 930 return -EINVAL;931}932 933static int ad7380_write_raw(struct iio_dev *indio_dev,934 struct iio_chan_spec const *chan, int val,935 int val2, long mask)936{937 struct ad7380_state *st = iio_priv(indio_dev);938 int ret, osr, boost;939 940 switch (mask) {941 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:942 osr = ad7380_osr_to_regval(val);943 if (osr < 0)944 return osr;945 946 /* always enable resolution boost when oversampling is enabled */947 boost = osr > 0 ? 1 : 0;948 949 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {950 ret = regmap_update_bits(st->regmap,951 AD7380_REG_ADDR_CONFIG1,952 AD7380_CONFIG1_OSR | AD7380_CONFIG1_RES,953 FIELD_PREP(AD7380_CONFIG1_OSR, osr) |954 FIELD_PREP(AD7380_CONFIG1_RES, boost));955 956 if (ret)957 return ret;958 959 st->oversampling_ratio = val;960 st->resolution_boost_enabled = boost;961 962 /*963 * Perform a soft reset. This will flush the oversampling964 * block and FIFO but will maintain the content of the965 * configurable registers.966 */967 return regmap_update_bits(st->regmap,968 AD7380_REG_ADDR_CONFIG2,969 AD7380_CONFIG2_RESET,970 FIELD_PREP(AD7380_CONFIG2_RESET,971 AD7380_CONFIG2_RESET_SOFT));972 }973 unreachable();974 default:975 return -EINVAL;976 }977}978 979static int ad7380_get_current_scan_type(const struct iio_dev *indio_dev,980 const struct iio_chan_spec *chan)981{982 struct ad7380_state *st = iio_priv(indio_dev);983 984 return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST985 : AD7380_SCAN_TYPE_NORMAL;986}987 988static const struct iio_info ad7380_info = {989 .read_raw = &ad7380_read_raw,990 .read_avail = &ad7380_read_avail,991 .write_raw = &ad7380_write_raw,992 .get_current_scan_type = &ad7380_get_current_scan_type,993 .debugfs_reg_access = &ad7380_debugfs_reg_access,994};995 996static int ad7380_init(struct ad7380_state *st, bool external_ref_en)997{998 int ret;999 1000 /* perform hard reset */1001 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2,1002 AD7380_CONFIG2_RESET,1003 FIELD_PREP(AD7380_CONFIG2_RESET,1004 AD7380_CONFIG2_RESET_HARD));1005 if (ret < 0)1006 return ret;1007 1008 if (external_ref_en) {1009 /* select external reference voltage */1010 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1,1011 AD7380_CONFIG1_REFSEL);1012 if (ret < 0)1013 return ret;1014 }1015 1016 /* This is the default value after reset. */1017 st->oversampling_ratio = 1;1018 st->ch = 0;1019 st->seq = false;1020 1021 /* SPI 1-wire mode */1022 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2,1023 AD7380_CONFIG2_SDO,1024 FIELD_PREP(AD7380_CONFIG2_SDO, 1));1025}1026 1027static int ad7380_probe(struct spi_device *spi)1028{1029 struct iio_dev *indio_dev;1030 struct ad7380_state *st;1031 bool external_ref_en;1032 int ret, i;1033 1034 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));1035 if (!indio_dev)1036 return -ENOMEM;1037 1038 st = iio_priv(indio_dev);1039 st->spi = spi;1040 st->chip_info = spi_get_device_match_data(spi);1041 if (!st->chip_info)1042 return dev_err_probe(&spi->dev, -EINVAL, "missing match data\n");1043 1044 ret = devm_regulator_bulk_get_enable(&spi->dev, st->chip_info->num_supplies,1045 st->chip_info->supplies);1046 1047 if (ret)1048 return dev_err_probe(&spi->dev, ret,1049 "Failed to enable power supplies\n");1050 fsleep(T_POWERUP_US);1051 1052 if (st->chip_info->external_ref_only) {1053 ret = devm_regulator_get_enable_read_voltage(&spi->dev,1054 "refin");1055 if (ret < 0)1056 return dev_err_probe(&spi->dev, ret,1057 "Failed to get refin regulator\n");1058 1059 st->vref_mv = ret / 1000;1060 1061 /* these chips don't have a register bit for this */1062 external_ref_en = false;1063 } else {1064 /*1065 * If there is no REFIO supply, then it means that we are using1066 * the internal reference, otherwise REFIO is reference voltage.1067 */1068 ret = devm_regulator_get_enable_read_voltage(&spi->dev,1069 "refio");1070 if (ret < 0 && ret != -ENODEV)1071 return dev_err_probe(&spi->dev, ret,1072 "Failed to get refio regulator\n");1073 1074 external_ref_en = ret != -ENODEV;1075 st->vref_mv = external_ref_en ? ret / 1000 : AD7380_INTERNAL_REF_MV;1076 }1077 1078 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv))1079 return dev_err_probe(&spi->dev, -EINVAL,1080 "invalid number of VCM supplies\n");1081 1082 /*1083 * pseudo-differential chips have common mode supplies for the negative1084 * input pin.1085 */1086 for (i = 0; i < st->chip_info->num_vcm_supplies; i++) {1087 const char *vcm = st->chip_info->vcm_supplies[i];1088 1089 ret = devm_regulator_get_enable_read_voltage(&spi->dev, vcm);1090 if (ret < 0)1091 return dev_err_probe(&spi->dev, ret,1092 "Failed to get %s regulator\n",1093 vcm);1094 1095 st->vcm_mv[i] = ret / 1000;1096 }1097 1098 st->regmap = devm_regmap_init(&spi->dev, NULL, st, &ad7380_regmap_config);1099 if (IS_ERR(st->regmap))1100 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap),1101 "failed to allocate register map\n");1102 1103 /*1104 * Setting up xfer structures for both normal and sequence mode. These1105 * struct are used for both direct read and triggered buffer. Additional1106 * fields will be set up in ad7380_update_xfers() based on the current1107 * state of the driver at the time of the read.1108 */1109 1110 /*1111 * In normal mode a read is composed of two steps:1112 * - first, toggle CS (no data xfer) to trigger a conversion1113 * - then, read data1114 */1115 st->normal_xfer[0].cs_change = 1;1116 st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;1117 st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;1118 st->normal_xfer[1].rx_buf = st->scan_data;1119 1120 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer,1121 ARRAY_SIZE(st->normal_xfer));1122 /*1123 * In sequencer mode a read is composed of four steps:1124 * - CS toggle (no data xfer) to get the right point in the sequence1125 * - CS toggle (no data xfer) to trigger a conversion of AinX0 and1126 * acquisition of AinX11127 * - 2 data reads, to read AinX0 and AinX11128 */1129 st->seq_xfer[0].cs_change = 1;1130 st->seq_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;1131 st->seq_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;1132 st->seq_xfer[1].cs_change = 1;1133 st->seq_xfer[1].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;1134 st->seq_xfer[1].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;1135 1136 st->seq_xfer[2].rx_buf = st->scan_data;1137 st->seq_xfer[2].cs_change = 1;1138 st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns;1139 st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;1140 1141 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer,1142 ARRAY_SIZE(st->seq_xfer));1143 1144 indio_dev->channels = st->chip_info->channels;1145 indio_dev->num_channels = st->chip_info->num_channels;1146 indio_dev->name = st->chip_info->name;1147 indio_dev->info = &ad7380_info;1148 indio_dev->modes = INDIO_DIRECT_MODE;1149 indio_dev->available_scan_masks = st->chip_info->available_scan_masks;1150 1151 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,1152 iio_pollfunc_store_time,1153 ad7380_trigger_handler,1154 &ad7380_buffer_setup_ops);1155 if (ret)1156 return ret;1157 1158 ret = ad7380_init(st, external_ref_en);1159 if (ret)1160 return ret;1161 1162 return devm_iio_device_register(&spi->dev, indio_dev);1163}1164 1165static const struct of_device_id ad7380_of_match_table[] = {1166 { .compatible = "adi,ad7380", .data = &ad7380_chip_info },1167 { .compatible = "adi,ad7381", .data = &ad7381_chip_info },1168 { .compatible = "adi,ad7383", .data = &ad7383_chip_info },1169 { .compatible = "adi,ad7384", .data = &ad7384_chip_info },1170 { .compatible = "adi,ad7386", .data = &ad7386_chip_info },1171 { .compatible = "adi,ad7387", .data = &ad7387_chip_info },1172 { .compatible = "adi,ad7388", .data = &ad7388_chip_info },1173 { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info },1174 { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info },1175 { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info },1176 { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info },1177 { .compatible = "adi,ad7386-4", .data = &ad7386_4_chip_info },1178 { .compatible = "adi,ad7387-4", .data = &ad7387_4_chip_info },1179 { .compatible = "adi,ad7388-4", .data = &ad7388_4_chip_info },1180 { }1181};1182 1183static const struct spi_device_id ad7380_id_table[] = {1184 { "ad7380", (kernel_ulong_t)&ad7380_chip_info },1185 { "ad7381", (kernel_ulong_t)&ad7381_chip_info },1186 { "ad7383", (kernel_ulong_t)&ad7383_chip_info },1187 { "ad7384", (kernel_ulong_t)&ad7384_chip_info },1188 { "ad7386", (kernel_ulong_t)&ad7386_chip_info },1189 { "ad7387", (kernel_ulong_t)&ad7387_chip_info },1190 { "ad7388", (kernel_ulong_t)&ad7388_chip_info },1191 { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info },1192 { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info },1193 { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info },1194 { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info },1195 { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info },1196 { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info },1197 { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info },1198 { }1199};1200MODULE_DEVICE_TABLE(spi, ad7380_id_table);1201 1202static struct spi_driver ad7380_driver = {1203 .driver = {1204 .name = "ad7380",1205 .of_match_table = ad7380_of_match_table,1206 },1207 .probe = ad7380_probe,1208 .id_table = ad7380_id_table,1209};1210module_spi_driver(ad7380_driver);1211 1212MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");1213MODULE_DESCRIPTION("Analog Devices AD738x ADC driver");1214MODULE_LICENSE("GPL");1215