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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright 2016 Broadcom4 */5 6#include <linux/module.h>7#include <linux/mod_devicetable.h>8#include <linux/io.h>9#include <linux/clk.h>10#include <linux/mfd/syscon.h>11#include <linux/regmap.h>12#include <linux/delay.h>13#include <linux/interrupt.h>14#include <linux/platform_device.h>15 16#include <linux/iio/iio.h>17 18/* Below Register's are common to IPROC ADC and Touchscreen IP */19#define IPROC_REGCTL1 0x0020#define IPROC_REGCTL2 0x0421#define IPROC_INTERRUPT_THRES 0x0822#define IPROC_INTERRUPT_MASK 0x0c23#define IPROC_INTERRUPT_STATUS 0x1024#define IPROC_ANALOG_CONTROL 0x1c25#define IPROC_CONTROLLER_STATUS 0x1426#define IPROC_AUX_DATA 0x2027#define IPROC_SOFT_BYPASS_CONTROL 0x3828#define IPROC_SOFT_BYPASS_DATA 0x3C29 30/* IPROC ADC Channel register offsets */31#define IPROC_ADC_CHANNEL_REGCTL1 0x80032#define IPROC_ADC_CHANNEL_REGCTL2 0x80433#define IPROC_ADC_CHANNEL_STATUS 0x80834#define IPROC_ADC_CHANNEL_INTERRUPT_STATUS 0x80c35#define IPROC_ADC_CHANNEL_INTERRUPT_MASK 0x81036#define IPROC_ADC_CHANNEL_DATA 0x81437#define IPROC_ADC_CHANNEL_OFFSET 0x2038 39/* Bit definitions for IPROC_REGCTL2 */40#define IPROC_ADC_AUXIN_SCAN_ENA BIT(0)41#define IPROC_ADC_PWR_LDO BIT(5)42#define IPROC_ADC_PWR_ADC BIT(4)43#define IPROC_ADC_PWR_BG BIT(3)44#define IPROC_ADC_CONTROLLER_EN BIT(17)45 46/* Bit definitions for IPROC_INTERRUPT_MASK and IPROC_INTERRUPT_STATUS */47#define IPROC_ADC_AUXDATA_RDY_INTR BIT(3)48#define IPROC_ADC_INTR 949#define IPROC_ADC_INTR_MASK (0xFF << IPROC_ADC_INTR)50 51/* Bit definitions for IPROC_ANALOG_CONTROL */52#define IPROC_ADC_CHANNEL_SEL 1153#define IPROC_ADC_CHANNEL_SEL_MASK (0x7 << IPROC_ADC_CHANNEL_SEL)54 55/* Bit definitions for IPROC_ADC_CHANNEL_REGCTL1 */56#define IPROC_ADC_CHANNEL_ROUNDS 0x257#define IPROC_ADC_CHANNEL_ROUNDS_MASK (0x3F << IPROC_ADC_CHANNEL_ROUNDS)58#define IPROC_ADC_CHANNEL_MODE 0x159#define IPROC_ADC_CHANNEL_MODE_MASK (0x1 << IPROC_ADC_CHANNEL_MODE)60#define IPROC_ADC_CHANNEL_MODE_TDM 0x161#define IPROC_ADC_CHANNEL_MODE_SNAPSHOT 0x062#define IPROC_ADC_CHANNEL_ENABLE 0x063#define IPROC_ADC_CHANNEL_ENABLE_MASK 0x164 65/* Bit definitions for IPROC_ADC_CHANNEL_REGCTL2 */66#define IPROC_ADC_CHANNEL_WATERMARK 0x067#define IPROC_ADC_CHANNEL_WATERMARK_MASK \68 (0x3F << IPROC_ADC_CHANNEL_WATERMARK)69 70#define IPROC_ADC_WATER_MARK_LEVEL 0x171 72/* Bit definitions for IPROC_ADC_CHANNEL_STATUS */73#define IPROC_ADC_CHANNEL_DATA_LOST 0x074#define IPROC_ADC_CHANNEL_DATA_LOST_MASK \75 (0x0 << IPROC_ADC_CHANNEL_DATA_LOST)76#define IPROC_ADC_CHANNEL_VALID_ENTERIES 0x177#define IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK \78 (0xFF << IPROC_ADC_CHANNEL_VALID_ENTERIES)79#define IPROC_ADC_CHANNEL_TOTAL_ENTERIES 0x980#define IPROC_ADC_CHANNEL_TOTAL_ENTERIES_MASK \81 (0xFF << IPROC_ADC_CHANNEL_TOTAL_ENTERIES)82 83/* Bit definitions for IPROC_ADC_CHANNEL_INTERRUPT_MASK */84#define IPROC_ADC_CHANNEL_WTRMRK_INTR 0x085#define IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK \86 (0x1 << IPROC_ADC_CHANNEL_WTRMRK_INTR)87#define IPROC_ADC_CHANNEL_FULL_INTR 0x188#define IPROC_ADC_CHANNEL_FULL_INTR_MASK \89 (0x1 << IPROC_ADC_IPROC_ADC_CHANNEL_FULL_INTR)90#define IPROC_ADC_CHANNEL_EMPTY_INTR 0x291#define IPROC_ADC_CHANNEL_EMPTY_INTR_MASK \92 (0x1 << IPROC_ADC_CHANNEL_EMPTY_INTR)93 94#define IPROC_ADC_WATER_MARK_INTR_ENABLE 0x195 96/* Number of time to retry a set of the interrupt mask reg */97#define IPROC_ADC_INTMASK_RETRY_ATTEMPTS 1098 99#define IPROC_ADC_READ_TIMEOUT (HZ*2)100 101#define iproc_adc_dbg_reg(dev, priv, reg) \102do { \103 u32 val; \104 regmap_read(priv->regmap, reg, &val); \105 dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \106} while (0)107 108struct iproc_adc_priv {109 struct regmap *regmap;110 struct clk *adc_clk;111 struct mutex mutex;112 int irqno;113 int chan_val;114 int chan_id;115 struct completion completion;116};117 118static void iproc_adc_reg_dump(struct iio_dev *indio_dev)119{120 struct device *dev = &indio_dev->dev;121 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);122 123 iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL1);124 iproc_adc_dbg_reg(dev, adc_priv, IPROC_REGCTL2);125 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_THRES);126 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_MASK);127 iproc_adc_dbg_reg(dev, adc_priv, IPROC_INTERRUPT_STATUS);128 iproc_adc_dbg_reg(dev, adc_priv, IPROC_CONTROLLER_STATUS);129 iproc_adc_dbg_reg(dev, adc_priv, IPROC_ANALOG_CONTROL);130 iproc_adc_dbg_reg(dev, adc_priv, IPROC_AUX_DATA);131 iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_CONTROL);132 iproc_adc_dbg_reg(dev, adc_priv, IPROC_SOFT_BYPASS_DATA);133}134 135static irqreturn_t iproc_adc_interrupt_thread(int irq, void *data)136{137 u32 channel_intr_status;138 u32 intr_status;139 u32 intr_mask;140 struct iio_dev *indio_dev = data;141 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);142 143 /*144 * This interrupt is shared with the touchscreen driver.145 * Make sure this interrupt is intended for us.146 * Handle only ADC channel specific interrupts.147 */148 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status);149 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &intr_mask);150 intr_status = intr_status & intr_mask;151 channel_intr_status = (intr_status & IPROC_ADC_INTR_MASK) >>152 IPROC_ADC_INTR;153 if (channel_intr_status)154 return IRQ_WAKE_THREAD;155 156 return IRQ_NONE;157}158 159static irqreturn_t iproc_adc_interrupt_handler(int irq, void *data)160{161 irqreturn_t retval = IRQ_NONE;162 struct iproc_adc_priv *adc_priv;163 struct iio_dev *indio_dev = data;164 unsigned int valid_entries;165 u32 intr_status;166 u32 intr_channels;167 u32 channel_status;168 u32 ch_intr_status;169 170 adc_priv = iio_priv(indio_dev);171 172 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_STATUS, &intr_status);173 dev_dbg(&indio_dev->dev, "iproc_adc_interrupt_handler(),INTRPT_STS:%x\n",174 intr_status);175 176 intr_channels = (intr_status & IPROC_ADC_INTR_MASK) >> IPROC_ADC_INTR;177 if (intr_channels) {178 regmap_read(adc_priv->regmap,179 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +180 IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id,181 &ch_intr_status);182 183 if (ch_intr_status & IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK) {184 regmap_read(adc_priv->regmap,185 IPROC_ADC_CHANNEL_STATUS +186 IPROC_ADC_CHANNEL_OFFSET *187 adc_priv->chan_id,188 &channel_status);189 190 valid_entries = ((channel_status &191 IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK) >>192 IPROC_ADC_CHANNEL_VALID_ENTERIES);193 if (valid_entries >= 1) {194 regmap_read(adc_priv->regmap,195 IPROC_ADC_CHANNEL_DATA +196 IPROC_ADC_CHANNEL_OFFSET *197 adc_priv->chan_id,198 &adc_priv->chan_val);199 complete(&adc_priv->completion);200 } else {201 dev_err(&indio_dev->dev,202 "No data rcvd on channel %d\n",203 adc_priv->chan_id);204 }205 regmap_write(adc_priv->regmap,206 IPROC_ADC_CHANNEL_INTERRUPT_MASK +207 IPROC_ADC_CHANNEL_OFFSET *208 adc_priv->chan_id,209 (ch_intr_status &210 ~(IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK)));211 }212 regmap_write(adc_priv->regmap,213 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +214 IPROC_ADC_CHANNEL_OFFSET * adc_priv->chan_id,215 ch_intr_status);216 regmap_write(adc_priv->regmap, IPROC_INTERRUPT_STATUS,217 intr_channels);218 retval = IRQ_HANDLED;219 }220 221 return retval;222}223 224static int iproc_adc_do_read(struct iio_dev *indio_dev,225 int channel,226 u16 *p_adc_data)227{228 int read_len = 0;229 u32 val;230 u32 mask;231 u32 val_check;232 int failed_cnt = 0;233 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);234 235 mutex_lock(&adc_priv->mutex);236 237 /*238 * After a read is complete the ADC interrupts will be disabled so239 * we can assume this section of code is safe from interrupts.240 */241 adc_priv->chan_val = -1;242 adc_priv->chan_id = channel;243 244 reinit_completion(&adc_priv->completion);245 /* Clear any pending interrupt */246 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS,247 IPROC_ADC_INTR_MASK | IPROC_ADC_AUXDATA_RDY_INTR,248 ((0x0 << channel) << IPROC_ADC_INTR) |249 IPROC_ADC_AUXDATA_RDY_INTR);250 251 /* Configure channel for snapshot mode and enable */252 val = (BIT(IPROC_ADC_CHANNEL_ROUNDS) |253 (IPROC_ADC_CHANNEL_MODE_SNAPSHOT << IPROC_ADC_CHANNEL_MODE) |254 (0x1 << IPROC_ADC_CHANNEL_ENABLE));255 256 mask = IPROC_ADC_CHANNEL_ROUNDS_MASK | IPROC_ADC_CHANNEL_MODE_MASK |257 IPROC_ADC_CHANNEL_ENABLE_MASK;258 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL1 +259 IPROC_ADC_CHANNEL_OFFSET * channel),260 mask, val);261 262 /* Set the Watermark for a channel */263 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_REGCTL2 +264 IPROC_ADC_CHANNEL_OFFSET * channel),265 IPROC_ADC_CHANNEL_WATERMARK_MASK,266 0x1);267 268 /* Enable water mark interrupt */269 regmap_update_bits(adc_priv->regmap, (IPROC_ADC_CHANNEL_INTERRUPT_MASK +270 IPROC_ADC_CHANNEL_OFFSET *271 channel),272 IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK,273 IPROC_ADC_WATER_MARK_INTR_ENABLE);274 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val);275 276 /* Enable ADC interrupt for a channel */277 val |= (BIT(channel) << IPROC_ADC_INTR);278 regmap_write(adc_priv->regmap, IPROC_INTERRUPT_MASK, val);279 280 /*281 * There seems to be a very rare issue where writing to this register282 * does not take effect. To work around the issue we will try multiple283 * writes. In total we will spend about 10*10 = 100 us attempting this.284 * Testing has shown that this may loop a few time, but we have never285 * hit the full count.286 */287 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);288 while (val_check != val) {289 failed_cnt++;290 291 if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS)292 break;293 294 udelay(10);295 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK,296 IPROC_ADC_INTR_MASK,297 ((0x1 << channel) <<298 IPROC_ADC_INTR));299 300 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);301 }302 303 if (failed_cnt) {304 dev_dbg(&indio_dev->dev,305 "IntMask failed (%d times)", failed_cnt);306 if (failed_cnt > IPROC_ADC_INTMASK_RETRY_ATTEMPTS) {307 dev_err(&indio_dev->dev,308 "IntMask set failed. Read will likely fail.");309 read_len = -EIO;310 goto adc_err;311 }312 }313 regmap_read(adc_priv->regmap, IPROC_INTERRUPT_MASK, &val_check);314 315 if (wait_for_completion_timeout(&adc_priv->completion,316 IPROC_ADC_READ_TIMEOUT) > 0) {317 318 /* Only the lower 16 bits are relevant */319 *p_adc_data = adc_priv->chan_val & 0xFFFF;320 read_len = sizeof(*p_adc_data);321 322 } else {323 /*324 * We never got the interrupt, something went wrong.325 * Perhaps the interrupt may still be coming, we do not want326 * that now. Lets disable the ADC interrupt, and clear the327 * status to put it back in to normal state.328 */329 read_len = -ETIMEDOUT;330 goto adc_err;331 }332 mutex_unlock(&adc_priv->mutex);333 334 return read_len;335 336adc_err:337 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_MASK,338 IPROC_ADC_INTR_MASK,339 ((0x0 << channel) << IPROC_ADC_INTR));340 341 regmap_update_bits(adc_priv->regmap, IPROC_INTERRUPT_STATUS,342 IPROC_ADC_INTR_MASK,343 ((0x0 << channel) << IPROC_ADC_INTR));344 345 dev_err(&indio_dev->dev, "Timed out waiting for ADC data!\n");346 iproc_adc_reg_dump(indio_dev);347 mutex_unlock(&adc_priv->mutex);348 349 return read_len;350}351 352static int iproc_adc_enable(struct iio_dev *indio_dev)353{354 u32 val;355 u32 channel_id;356 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);357 int ret;358 359 /* Set i_amux = 3b'000, select channel 0 */360 ret = regmap_clear_bits(adc_priv->regmap, IPROC_ANALOG_CONTROL,361 IPROC_ADC_CHANNEL_SEL_MASK);362 if (ret) {363 dev_err(&indio_dev->dev,364 "failed to write IPROC_ANALOG_CONTROL %d\n", ret);365 return ret;366 }367 adc_priv->chan_val = -1;368 369 /*370 * PWR up LDO, ADC, and Band Gap (0 to enable)371 * Also enable ADC controller (set high)372 */373 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);374 if (ret) {375 dev_err(&indio_dev->dev,376 "failed to read IPROC_REGCTL2 %d\n", ret);377 return ret;378 }379 380 val &= ~(IPROC_ADC_PWR_LDO | IPROC_ADC_PWR_ADC | IPROC_ADC_PWR_BG);381 382 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);383 if (ret) {384 dev_err(&indio_dev->dev,385 "failed to write IPROC_REGCTL2 %d\n", ret);386 return ret;387 }388 389 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);390 if (ret) {391 dev_err(&indio_dev->dev,392 "failed to read IPROC_REGCTL2 %d\n", ret);393 return ret;394 }395 396 val |= IPROC_ADC_CONTROLLER_EN;397 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);398 if (ret) {399 dev_err(&indio_dev->dev,400 "failed to write IPROC_REGCTL2 %d\n", ret);401 return ret;402 }403 404 for (channel_id = 0; channel_id < indio_dev->num_channels;405 channel_id++) {406 ret = regmap_write(adc_priv->regmap,407 IPROC_ADC_CHANNEL_INTERRUPT_MASK +408 IPROC_ADC_CHANNEL_OFFSET * channel_id, 0);409 if (ret) {410 dev_err(&indio_dev->dev,411 "failed to write ADC_CHANNEL_INTERRUPT_MASK %d\n",412 ret);413 return ret;414 }415 416 ret = regmap_write(adc_priv->regmap,417 IPROC_ADC_CHANNEL_INTERRUPT_STATUS +418 IPROC_ADC_CHANNEL_OFFSET * channel_id, 0);419 if (ret) {420 dev_err(&indio_dev->dev,421 "failed to write ADC_CHANNEL_INTERRUPT_STATUS %d\n",422 ret);423 return ret;424 }425 }426 427 return 0;428}429 430static void iproc_adc_disable(struct iio_dev *indio_dev)431{432 u32 val;433 int ret;434 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);435 436 ret = regmap_read(adc_priv->regmap, IPROC_REGCTL2, &val);437 if (ret) {438 dev_err(&indio_dev->dev,439 "failed to read IPROC_REGCTL2 %d\n", ret);440 return;441 }442 443 val &= ~IPROC_ADC_CONTROLLER_EN;444 ret = regmap_write(adc_priv->regmap, IPROC_REGCTL2, val);445 if (ret) {446 dev_err(&indio_dev->dev,447 "failed to write IPROC_REGCTL2 %d\n", ret);448 return;449 }450}451 452static int iproc_adc_read_raw(struct iio_dev *indio_dev,453 struct iio_chan_spec const *chan,454 int *val,455 int *val2,456 long mask)457{458 u16 adc_data;459 int err;460 461 switch (mask) {462 case IIO_CHAN_INFO_RAW:463 err = iproc_adc_do_read(indio_dev, chan->channel, &adc_data);464 if (err < 0)465 return err;466 *val = adc_data;467 return IIO_VAL_INT;468 case IIO_CHAN_INFO_SCALE:469 switch (chan->type) {470 case IIO_VOLTAGE:471 *val = 1800;472 *val2 = 10;473 return IIO_VAL_FRACTIONAL_LOG2;474 default:475 return -EINVAL;476 }477 default:478 return -EINVAL;479 }480}481 482static const struct iio_info iproc_adc_iio_info = {483 .read_raw = &iproc_adc_read_raw,484};485 486#define IPROC_ADC_CHANNEL(_index, _id) { \487 .type = IIO_VOLTAGE, \488 .indexed = 1, \489 .channel = _index, \490 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \491 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \492 .datasheet_name = _id, \493}494 495static const struct iio_chan_spec iproc_adc_iio_channels[] = {496 IPROC_ADC_CHANNEL(0, "adc0"),497 IPROC_ADC_CHANNEL(1, "adc1"),498 IPROC_ADC_CHANNEL(2, "adc2"),499 IPROC_ADC_CHANNEL(3, "adc3"),500 IPROC_ADC_CHANNEL(4, "adc4"),501 IPROC_ADC_CHANNEL(5, "adc5"),502 IPROC_ADC_CHANNEL(6, "adc6"),503 IPROC_ADC_CHANNEL(7, "adc7"),504};505 506static int iproc_adc_probe(struct platform_device *pdev)507{508 struct iproc_adc_priv *adc_priv;509 struct iio_dev *indio_dev = NULL;510 int ret;511 512 indio_dev = devm_iio_device_alloc(&pdev->dev,513 sizeof(*adc_priv));514 if (!indio_dev) {515 dev_err(&pdev->dev, "failed to allocate iio device\n");516 return -ENOMEM;517 }518 519 adc_priv = iio_priv(indio_dev);520 platform_set_drvdata(pdev, indio_dev);521 522 mutex_init(&adc_priv->mutex);523 524 init_completion(&adc_priv->completion);525 526 adc_priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,527 "adc-syscon");528 if (IS_ERR(adc_priv->regmap)) {529 dev_err(&pdev->dev, "failed to get handle for tsc syscon\n");530 ret = PTR_ERR(adc_priv->regmap);531 return ret;532 }533 534 adc_priv->adc_clk = devm_clk_get(&pdev->dev, "tsc_clk");535 if (IS_ERR(adc_priv->adc_clk)) {536 dev_err(&pdev->dev,537 "failed getting clock tsc_clk\n");538 ret = PTR_ERR(adc_priv->adc_clk);539 return ret;540 }541 542 adc_priv->irqno = platform_get_irq(pdev, 0);543 if (adc_priv->irqno < 0)544 return adc_priv->irqno;545 546 ret = regmap_clear_bits(adc_priv->regmap, IPROC_REGCTL2,547 IPROC_ADC_AUXIN_SCAN_ENA);548 if (ret) {549 dev_err(&pdev->dev, "failed to write IPROC_REGCTL2 %d\n", ret);550 return ret;551 }552 553 ret = devm_request_threaded_irq(&pdev->dev, adc_priv->irqno,554 iproc_adc_interrupt_handler,555 iproc_adc_interrupt_thread,556 IRQF_SHARED, "iproc-adc", indio_dev);557 if (ret) {558 dev_err(&pdev->dev, "request_irq error %d\n", ret);559 return ret;560 }561 562 ret = clk_prepare_enable(adc_priv->adc_clk);563 if (ret) {564 dev_err(&pdev->dev,565 "clk_prepare_enable failed %d\n", ret);566 return ret;567 }568 569 ret = iproc_adc_enable(indio_dev);570 if (ret) {571 dev_err(&pdev->dev, "failed to enable adc %d\n", ret);572 goto err_adc_enable;573 }574 575 indio_dev->name = "iproc-static-adc";576 indio_dev->info = &iproc_adc_iio_info;577 indio_dev->modes = INDIO_DIRECT_MODE;578 indio_dev->channels = iproc_adc_iio_channels;579 indio_dev->num_channels = ARRAY_SIZE(iproc_adc_iio_channels);580 581 ret = iio_device_register(indio_dev);582 if (ret) {583 dev_err(&pdev->dev, "iio_device_register failed:err %d\n", ret);584 goto err_clk;585 }586 587 return 0;588 589err_clk:590 iproc_adc_disable(indio_dev);591err_adc_enable:592 clk_disable_unprepare(adc_priv->adc_clk);593 594 return ret;595}596 597static void iproc_adc_remove(struct platform_device *pdev)598{599 struct iio_dev *indio_dev = platform_get_drvdata(pdev);600 struct iproc_adc_priv *adc_priv = iio_priv(indio_dev);601 602 iio_device_unregister(indio_dev);603 iproc_adc_disable(indio_dev);604 clk_disable_unprepare(adc_priv->adc_clk);605}606 607static const struct of_device_id iproc_adc_of_match[] = {608 {.compatible = "brcm,iproc-static-adc", },609 { }610};611MODULE_DEVICE_TABLE(of, iproc_adc_of_match);612 613static struct platform_driver iproc_adc_driver = {614 .probe = iproc_adc_probe,615 .remove_new = iproc_adc_remove,616 .driver = {617 .name = "iproc-static-adc",618 .of_match_table = iproc_adc_of_match,619 },620};621module_platform_driver(iproc_adc_driver);622 623MODULE_DESCRIPTION("Broadcom iProc ADC controller driver");624MODULE_AUTHOR("Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>");625MODULE_LICENSE("GPL v2");626