1499 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter4 *5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>6 */7 8#include <linux/bitfield.h>9#include <linux/clk.h>10#include <linux/clk-provider.h>11#include <linux/delay.h>12#include <linux/io.h>13#include <linux/iio/iio.h>14#include <linux/module.h>15#include <linux/mutex.h>16#include <linux/nvmem-consumer.h>17#include <linux/interrupt.h>18#include <linux/of.h>19#include <linux/of_irq.h>20#include <linux/platform_device.h>21#include <linux/regmap.h>22#include <linux/regulator/consumer.h>23#include <linux/mfd/syscon.h>24 25#define MESON_SAR_ADC_REG0 0x0026 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)27 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)28 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)29 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)30 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)31 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)32 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)33 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)34 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)35 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)36 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)37 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)38 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)39 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)40 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)41 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)42 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)43 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)44 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)45 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)46 47#define MESON_SAR_ADC_CHAN_LIST 0x0448 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \50 (GENMASK(2, 0) << ((_chan) * 3))51 52#define MESON_SAR_ADC_AVG_CNTL 0x0853 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \54 (16 + ((_chan) * 2))55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \56 (GENMASK(17, 16) << ((_chan) * 2))57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \58 (0 + ((_chan) * 2))59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \60 (GENMASK(1, 0) << ((_chan) * 2))61 62#define MESON_SAR_ADC_REG3 0x0c63 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)64 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)65 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)66 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)67 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)68 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)69 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)70 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)71 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)72 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)73 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 1074 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 675 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)76 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)77 78#define MESON_SAR_ADC_DELAY 0x1079 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)80 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)81 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)82 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)83 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)84 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)85 86#define MESON_SAR_ADC_LAST_RD 0x1487 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)88 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)89 90#define MESON_SAR_ADC_FIFO_RD 0x1891 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)92 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)93 94#define MESON_SAR_ADC_AUX_SW 0x1c95 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \96 (8 + (((_chan) - 2) * 3))97 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)98 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)99 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)100 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)101 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)102 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)103 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)104 105#define MESON_SAR_ADC_CHAN_10_SW 0x20106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)122 123#define MESON_SAR_ADC_DETECT_IDLE_SW 0x24124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)141 142#define MESON_SAR_ADC_DELTA_10 0x28143 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)144 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)145 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)146 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)147 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)148 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)149 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)150 151/*152 * NOTE: registers from here are undocumented (the vendor Linux kernel driver153 * and u-boot source served as reference). These only seem to be relevant on154 * GXBB and newer.155 */156#define MESON_SAR_ADC_REG11 0x2c157 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)158 #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6)159 #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5)160 #define MESON_SAR_ADC_REG11_EOC BIT(1)161 #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0)162 163#define MESON_SAR_ADC_REG13 0x34164 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)165 166#define MESON_SAR_ADC_MAX_FIFO_SIZE 32167#define MESON_SAR_ADC_TIMEOUT 100 /* ms */168#define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6169#define MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL 7170#define MESON_SAR_ADC_TEMP_OFFSET 27171 172/* temperature sensor calibration information in eFuse */173#define MESON_SAR_ADC_EFUSE_BYTES 4174#define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)175#define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)176 177#define MESON_HHI_DPLL_TOP_0 0x318178#define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)179 180/* for use with IIO_VAL_INT_PLUS_MICRO */181#define MILLION 1000000182 183#define MESON_SAR_ADC_CHAN(_chan) { \184 .type = IIO_VOLTAGE, \185 .indexed = 1, \186 .channel = _chan, \187 .address = _chan, \188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \189 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \190 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \191 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \192 BIT(IIO_CHAN_INFO_CALIBSCALE), \193 .datasheet_name = "SAR_ADC_CH"#_chan, \194}195 196#define MESON_SAR_ADC_TEMP_CHAN(_chan) { \197 .type = IIO_TEMP, \198 .channel = _chan, \199 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \200 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \201 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \202 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \203 BIT(IIO_CHAN_INFO_SCALE), \204 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \205 BIT(IIO_CHAN_INFO_CALIBSCALE), \206 .datasheet_name = "TEMP_SENSOR", \207}208 209#define MESON_SAR_ADC_MUX(_chan, _sel) { \210 .type = IIO_VOLTAGE, \211 .channel = _chan, \212 .indexed = 1, \213 .address = MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL, \214 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \215 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \216 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \217 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \218 BIT(IIO_CHAN_INFO_CALIBSCALE), \219 .datasheet_name = "SAR_ADC_MUX_"#_sel, \220}221 222enum meson_sar_adc_vref_sel {223 VREF_CALIBATION_VOLTAGE = 0,224 VREF_VDDA = 1,225};226 227enum meson_sar_adc_avg_mode {228 NO_AVERAGING = 0x0,229 MEAN_AVERAGING = 0x1,230 MEDIAN_AVERAGING = 0x2,231};232 233enum meson_sar_adc_num_samples {234 ONE_SAMPLE = 0x0,235 TWO_SAMPLES = 0x1,236 FOUR_SAMPLES = 0x2,237 EIGHT_SAMPLES = 0x3,238};239 240enum meson_sar_adc_chan7_mux_sel {241 CHAN7_MUX_VSS = 0x0,242 CHAN7_MUX_VDD_DIV4 = 0x1,243 CHAN7_MUX_VDD_DIV2 = 0x2,244 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,245 CHAN7_MUX_VDD = 0x4,246 CHAN7_MUX_CH7_INPUT = 0x7,247};248 249enum meson_sar_adc_channel_index {250 NUM_CHAN_0,251 NUM_CHAN_1,252 NUM_CHAN_2,253 NUM_CHAN_3,254 NUM_CHAN_4,255 NUM_CHAN_5,256 NUM_CHAN_6,257 NUM_CHAN_7,258 NUM_CHAN_TEMP,259 NUM_MUX_0_VSS,260 NUM_MUX_1_VDD_DIV4,261 NUM_MUX_2_VDD_DIV2,262 NUM_MUX_3_VDD_MUL3_DIV4,263 NUM_MUX_4_VDD,264};265 266static enum meson_sar_adc_chan7_mux_sel chan7_mux_values[] = {267 CHAN7_MUX_VSS,268 CHAN7_MUX_VDD_DIV4,269 CHAN7_MUX_VDD_DIV2,270 CHAN7_MUX_VDD_MUL3_DIV4,271 CHAN7_MUX_VDD,272};273 274static const char * const chan7_mux_names[] = {275 [CHAN7_MUX_VSS] = "gnd",276 [CHAN7_MUX_VDD_DIV4] = "0.25vdd",277 [CHAN7_MUX_VDD_DIV2] = "0.5vdd",278 [CHAN7_MUX_VDD_MUL3_DIV4] = "0.75vdd",279 [CHAN7_MUX_VDD] = "vdd",280};281 282static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {283 MESON_SAR_ADC_CHAN(NUM_CHAN_0),284 MESON_SAR_ADC_CHAN(NUM_CHAN_1),285 MESON_SAR_ADC_CHAN(NUM_CHAN_2),286 MESON_SAR_ADC_CHAN(NUM_CHAN_3),287 MESON_SAR_ADC_CHAN(NUM_CHAN_4),288 MESON_SAR_ADC_CHAN(NUM_CHAN_5),289 MESON_SAR_ADC_CHAN(NUM_CHAN_6),290 MESON_SAR_ADC_CHAN(NUM_CHAN_7),291 MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0),292 MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1),293 MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2),294 MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3),295 MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4),296};297 298static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {299 MESON_SAR_ADC_CHAN(NUM_CHAN_0),300 MESON_SAR_ADC_CHAN(NUM_CHAN_1),301 MESON_SAR_ADC_CHAN(NUM_CHAN_2),302 MESON_SAR_ADC_CHAN(NUM_CHAN_3),303 MESON_SAR_ADC_CHAN(NUM_CHAN_4),304 MESON_SAR_ADC_CHAN(NUM_CHAN_5),305 MESON_SAR_ADC_CHAN(NUM_CHAN_6),306 MESON_SAR_ADC_CHAN(NUM_CHAN_7),307 MESON_SAR_ADC_TEMP_CHAN(NUM_CHAN_TEMP),308 MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0),309 MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1),310 MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2),311 MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3),312 MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4),313};314 315struct meson_sar_adc_param {316 bool has_bl30_integration;317 unsigned long clock_rate;318 u32 bandgap_reg;319 unsigned int resolution;320 const struct regmap_config *regmap_config;321 u8 temperature_trimming_bits;322 unsigned int temperature_multiplier;323 unsigned int temperature_divider;324 u8 disable_ring_counter;325 bool has_reg11;326 bool has_vref_select;327 u8 vref_select;328 u8 cmv_select;329 u8 adc_eoc;330 enum meson_sar_adc_vref_sel vref_volatge;331};332 333struct meson_sar_adc_data {334 const struct meson_sar_adc_param *param;335 const char *name;336};337 338struct meson_sar_adc_priv {339 struct regmap *regmap;340 struct regulator *vref;341 const struct meson_sar_adc_param *param;342 struct clk *clkin;343 struct clk *core_clk;344 struct clk *adc_sel_clk;345 struct clk *adc_clk;346 struct clk_gate clk_gate;347 struct clk *adc_div_clk;348 struct clk_divider clk_div;349 struct completion done;350 /* lock to protect against multiple access to the device */351 struct mutex lock;352 int calibbias;353 int calibscale;354 struct regmap *tsc_regmap;355 bool temperature_sensor_calibrated;356 u8 temperature_sensor_coefficient;357 u16 temperature_sensor_adc_val;358 enum meson_sar_adc_chan7_mux_sel chan7_mux_sel;359};360 361static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {362 .reg_bits = 8,363 .val_bits = 32,364 .reg_stride = 4,365 .max_register = MESON_SAR_ADC_REG13,366};367 368static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {369 .reg_bits = 8,370 .val_bits = 32,371 .reg_stride = 4,372 .max_register = MESON_SAR_ADC_DELTA_10,373};374 375static const struct iio_chan_spec *376find_channel_by_num(struct iio_dev *indio_dev, int num)377{378 int i;379 380 for (i = 0; i < indio_dev->num_channels; i++)381 if (indio_dev->channels[i].channel == num)382 return &indio_dev->channels[i];383 return NULL;384}385 386static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)387{388 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);389 u32 regval;390 391 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);392 393 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);394}395 396static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)397{398 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);399 int tmp;400 401 /* use val_calib = scale * val_raw + offset calibration function */402 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;403 404 return clamp(tmp, 0, (1 << priv->param->resolution) - 1);405}406 407static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)408{409 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);410 int val;411 412 /*413 * NOTE: we need a small delay before reading the status, otherwise414 * the sample engine may not have started internally (which would415 * seem to us that sampling is already finished).416 */417 udelay(1);418 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val,419 !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val),420 1, 10000);421}422 423static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,424 enum meson_sar_adc_chan7_mux_sel sel)425{426 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);427 u32 regval;428 429 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);430 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,431 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);432 433 usleep_range(10, 20);434 435 priv->chan7_mux_sel = sel;436}437 438static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,439 const struct iio_chan_spec *chan,440 int *val)441{442 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);443 struct device *dev = indio_dev->dev.parent;444 int regval, fifo_chan, fifo_val, count;445 446 if (!wait_for_completion_timeout(&priv->done,447 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))448 return -ETIMEDOUT;449 450 count = meson_sar_adc_get_fifo_count(indio_dev);451 if (count != 1) {452 dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count);453 return -EINVAL;454 }455 456 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);457 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);458 if (fifo_chan != chan->address) {459 dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n",460 fifo_chan, chan->address);461 return -EINVAL;462 }463 464 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);465 fifo_val &= GENMASK(priv->param->resolution - 1, 0);466 *val = meson_sar_adc_calib_val(indio_dev, fifo_val);467 468 return 0;469}470 471static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,472 const struct iio_chan_spec *chan,473 enum meson_sar_adc_avg_mode mode,474 enum meson_sar_adc_num_samples samples)475{476 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);477 int val, address = chan->address;478 479 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);480 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,481 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),482 val);483 484 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);485 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,486 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);487}488 489static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,490 const struct iio_chan_spec *chan)491{492 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);493 u32 regval;494 495 /*496 * the SAR ADC engine allows sampling multiple channels at the same497 * time. to keep it simple we're only working with one *internal*498 * channel, which starts counting at index 0 (which means: count = 1).499 */500 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);501 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,502 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);503 504 /* map channel index 0 to the channel which we want to read */505 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),506 chan->address);507 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,508 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);509 510 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,511 chan->address);512 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,513 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,514 regval);515 516 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,517 chan->address);518 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,519 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,520 regval);521 522 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {523 if (chan->type == IIO_TEMP)524 regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;525 else526 regval = 0;527 528 regmap_update_bits(priv->regmap,529 MESON_SAR_ADC_DELTA_10,530 MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);531 } else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) {532 enum meson_sar_adc_chan7_mux_sel sel;533 534 if (chan->channel == NUM_CHAN_7)535 sel = CHAN7_MUX_CH7_INPUT;536 else537 sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS];538 if (sel != priv->chan7_mux_sel)539 meson_sar_adc_set_chan7_mux(indio_dev, sel);540 }541}542 543static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)544{545 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);546 547 reinit_completion(&priv->done);548 549 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,550 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);551 552 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,553 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);554 555 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,556 MESON_SAR_ADC_REG0_SAMPLING_START);557}558 559static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)560{561 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);562 563 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,564 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);565 566 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG0,567 MESON_SAR_ADC_REG0_SAMPLING_STOP);568 569 /* wait until all modules are stopped */570 meson_sar_adc_wait_busy_clear(indio_dev);571 572 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,573 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);574}575 576static int meson_sar_adc_lock(struct iio_dev *indio_dev)577{578 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);579 int val, ret;580 581 mutex_lock(&priv->lock);582 583 if (priv->param->has_bl30_integration) {584 /* prevent BL30 from using the SAR ADC while we are using it */585 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELAY,586 MESON_SAR_ADC_DELAY_KERNEL_BUSY);587 588 udelay(1);589 590 /*591 * wait until BL30 releases it's lock (so we can use the SAR592 * ADC)593 */594 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val,595 !(val & MESON_SAR_ADC_DELAY_BL30_BUSY),596 1, 10000);597 if (ret) {598 mutex_unlock(&priv->lock);599 return ret;600 }601 }602 603 return 0;604}605 606static void meson_sar_adc_unlock(struct iio_dev *indio_dev)607{608 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);609 610 if (priv->param->has_bl30_integration)611 /* allow BL30 to use the SAR ADC again */612 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELAY,613 MESON_SAR_ADC_DELAY_KERNEL_BUSY);614 615 mutex_unlock(&priv->lock);616}617 618static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)619{620 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);621 unsigned int count, tmp;622 623 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {624 if (!meson_sar_adc_get_fifo_count(indio_dev))625 break;626 627 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);628 }629}630 631static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,632 const struct iio_chan_spec *chan,633 enum meson_sar_adc_avg_mode avg_mode,634 enum meson_sar_adc_num_samples avg_samples,635 int *val)636{637 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);638 struct device *dev = indio_dev->dev.parent;639 int ret;640 641 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)642 return -ENOTSUPP;643 644 ret = meson_sar_adc_lock(indio_dev);645 if (ret)646 return ret;647 648 /* clear the FIFO to make sure we're not reading old values */649 meson_sar_adc_clear_fifo(indio_dev);650 651 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);652 653 meson_sar_adc_enable_channel(indio_dev, chan);654 655 meson_sar_adc_start_sample_engine(indio_dev);656 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);657 meson_sar_adc_stop_sample_engine(indio_dev);658 659 meson_sar_adc_unlock(indio_dev);660 661 if (ret) {662 dev_warn(dev, "failed to read sample for channel %lu: %d\n",663 chan->address, ret);664 return ret;665 }666 667 return IIO_VAL_INT;668}669 670static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,671 const struct iio_chan_spec *chan,672 int *val, int *val2, long mask)673{674 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);675 struct device *dev = indio_dev->dev.parent;676 int ret;677 678 switch (mask) {679 case IIO_CHAN_INFO_RAW:680 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,681 ONE_SAMPLE, val);682 683 case IIO_CHAN_INFO_AVERAGE_RAW:684 return meson_sar_adc_get_sample(indio_dev, chan,685 MEAN_AVERAGING, EIGHT_SAMPLES,686 val);687 688 case IIO_CHAN_INFO_SCALE:689 if (chan->type == IIO_VOLTAGE) {690 ret = regulator_get_voltage(priv->vref);691 if (ret < 0) {692 dev_err(dev, "failed to get vref voltage: %d\n", ret);693 return ret;694 }695 696 *val = ret / 1000;697 *val2 = priv->param->resolution;698 return IIO_VAL_FRACTIONAL_LOG2;699 } else if (chan->type == IIO_TEMP) {700 /* SoC specific multiplier and divider */701 *val = priv->param->temperature_multiplier;702 *val2 = priv->param->temperature_divider;703 704 /* celsius to millicelsius */705 *val *= 1000;706 707 return IIO_VAL_FRACTIONAL;708 } else {709 return -EINVAL;710 }711 712 case IIO_CHAN_INFO_CALIBBIAS:713 *val = priv->calibbias;714 return IIO_VAL_INT;715 716 case IIO_CHAN_INFO_CALIBSCALE:717 *val = priv->calibscale / MILLION;718 *val2 = priv->calibscale % MILLION;719 return IIO_VAL_INT_PLUS_MICRO;720 721 case IIO_CHAN_INFO_OFFSET:722 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *723 priv->param->temperature_divider,724 priv->param->temperature_multiplier);725 *val -= priv->temperature_sensor_adc_val;726 return IIO_VAL_INT;727 728 default:729 return -EINVAL;730 }731}732 733static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,734 void __iomem *base)735{736 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);737 struct device *dev = indio_dev->dev.parent;738 struct clk_init_data init;739 const char *clk_parents[1];740 741 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev));742 if (!init.name)743 return -ENOMEM;744 745 init.flags = 0;746 init.ops = &clk_divider_ops;747 clk_parents[0] = __clk_get_name(priv->clkin);748 init.parent_names = clk_parents;749 init.num_parents = 1;750 751 priv->clk_div.reg = base + MESON_SAR_ADC_REG3;752 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;753 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;754 priv->clk_div.hw.init = &init;755 priv->clk_div.flags = 0;756 757 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw);758 if (WARN_ON(IS_ERR(priv->adc_div_clk)))759 return PTR_ERR(priv->adc_div_clk);760 761 init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev));762 if (!init.name)763 return -ENOMEM;764 765 init.flags = CLK_SET_RATE_PARENT;766 init.ops = &clk_gate_ops;767 clk_parents[0] = __clk_get_name(priv->adc_div_clk);768 init.parent_names = clk_parents;769 init.num_parents = 1;770 771 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;772 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);773 priv->clk_gate.hw.init = &init;774 775 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);776 if (WARN_ON(IS_ERR(priv->adc_clk)))777 return PTR_ERR(priv->adc_clk);778 779 return 0;780}781 782static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)783{784 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);785 u8 *buf, trimming_bits, trimming_mask, upper_adc_val;786 struct device *dev = indio_dev->dev.parent;787 struct nvmem_cell *temperature_calib;788 size_t read_len;789 int ret;790 791 temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib");792 if (IS_ERR(temperature_calib)) {793 ret = PTR_ERR(temperature_calib);794 795 /*796 * leave the temperature sensor disabled if no calibration data797 * was passed via nvmem-cells.798 */799 if (ret == -ENODEV)800 return 0;801 802 return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n");803 }804 805 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");806 if (IS_ERR(priv->tsc_regmap))807 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),808 "failed to get amlogic,hhi-sysctrl regmap\n");809 810 read_len = MESON_SAR_ADC_EFUSE_BYTES;811 buf = nvmem_cell_read(temperature_calib, &read_len);812 if (IS_ERR(buf))813 return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n");814 if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {815 kfree(buf);816 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n");817 }818 819 trimming_bits = priv->param->temperature_trimming_bits;820 trimming_mask = BIT(trimming_bits) - 1;821 822 priv->temperature_sensor_calibrated =823 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;824 priv->temperature_sensor_coefficient = buf[2] & trimming_mask;825 826 upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,827 buf[3]);828 829 priv->temperature_sensor_adc_val = buf[2];830 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;831 priv->temperature_sensor_adc_val >>= trimming_bits;832 833 kfree(buf);834 835 return 0;836}837 838static int meson_sar_adc_init(struct iio_dev *indio_dev)839{840 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);841 struct device *dev = indio_dev->dev.parent;842 int regval, i, ret;843 844 /*845 * make sure we start at CH7 input since the other muxes are only used846 * for internal calibration.847 */848 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);849 850 if (priv->param->has_bl30_integration) {851 /*852 * leave sampling delay and the input clocks as configured by853 * BL30 to make sure BL30 gets the values it expects when854 * reading the temperature sensor.855 */856 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);857 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)858 return 0;859 }860 861 meson_sar_adc_stop_sample_engine(indio_dev);862 863 /*864 * disable this bit as seems to be only relevant for Meson6 (based865 * on the vendor driver), which we don't support at the moment.866 */867 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG0,868 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);869 870 /* disable all channels by default */871 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);872 873 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,874 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE);875 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,876 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);877 878 /* delay between two samples = (10+1) * 1uS */879 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,880 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,881 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,882 10));883 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,884 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,885 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,886 0));887 888 /* delay between two samples = (10+1) * 1uS */889 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,890 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,891 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,892 10));893 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,894 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,895 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,896 1));897 898 /*899 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW900 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)901 */902 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);903 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,904 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,905 regval);906 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);907 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,908 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,909 regval);910 911 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,912 MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);913 914 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,915 MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);916 917 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,918 MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);919 920 regmap_set_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,921 MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);922 923 /*924 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW925 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable926 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and927 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.928 */929 regval = 0;930 for (i = 2; i <= 7; i++)931 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);932 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;933 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;934 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);935 936 if (priv->temperature_sensor_calibrated) {937 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,938 MESON_SAR_ADC_DELTA_10_TS_REVE1);939 regmap_set_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,940 MESON_SAR_ADC_DELTA_10_TS_REVE0);941 942 /*943 * set bits [3:0] of the TSC (temperature sensor coefficient)944 * to get the correct values when reading the temperature.945 */946 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,947 priv->temperature_sensor_coefficient);948 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,949 MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);950 951 if (priv->param->temperature_trimming_bits == 5) {952 if (priv->temperature_sensor_coefficient & BIT(4))953 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;954 else955 regval = 0;956 957 /*958 * bit [4] (the 5th bit when starting to count at 1)959 * of the TSC is located in the HHI register area.960 */961 regmap_update_bits(priv->tsc_regmap,962 MESON_HHI_DPLL_TOP_0,963 MESON_HHI_DPLL_TOP_0_TSC_BIT4,964 regval);965 }966 } else {967 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,968 MESON_SAR_ADC_DELTA_10_TS_REVE1);969 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,970 MESON_SAR_ADC_DELTA_10_TS_REVE0);971 }972 973 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,974 priv->param->disable_ring_counter);975 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,976 MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,977 regval);978 979 if (priv->param->has_reg11) {980 regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);981 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,982 MESON_SAR_ADC_REG11_EOC, regval);983 984 if (priv->param->has_vref_select) {985 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL,986 priv->param->vref_select);987 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,988 MESON_SAR_ADC_REG11_VREF_SEL, regval);989 }990 991 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,992 priv->param->vref_volatge);993 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,994 MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);995 996 regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,997 priv->param->cmv_select);998 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,999 MESON_SAR_ADC_REG11_CMV_SEL, regval);1000 }1001 1002 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);1003 if (ret)1004 return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");1005 1006 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);1007 if (ret)1008 return dev_err_probe(dev, ret, "failed to set adc clock rate\n");1009 1010 return 0;1011}1012 1013static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)1014{1015 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);1016 const struct meson_sar_adc_param *param = priv->param;1017 u32 enable_mask;1018 1019 if (param->bandgap_reg == MESON_SAR_ADC_REG11)1020 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;1021 else1022 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;1023 1024 regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,1025 on_off ? enable_mask : 0);1026}1027 1028static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)1029{1030 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);1031 struct device *dev = indio_dev->dev.parent;1032 int ret;1033 u32 regval;1034 1035 ret = meson_sar_adc_lock(indio_dev);1036 if (ret) {1037 dev_err(dev, "failed to lock adc\n");1038 goto err_lock;1039 }1040 1041 ret = regulator_enable(priv->vref);1042 if (ret < 0) {1043 dev_err(dev, "failed to enable vref regulator\n");1044 goto err_vref;1045 }1046 1047 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);1048 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,1049 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);1050 1051 meson_sar_adc_set_bandgap(indio_dev, true);1052 1053 regmap_set_bits(priv->regmap, MESON_SAR_ADC_REG3,1054 MESON_SAR_ADC_REG3_ADC_EN);1055 1056 udelay(5);1057 1058 ret = clk_prepare_enable(priv->adc_clk);1059 if (ret) {1060 dev_err(dev, "failed to enable adc clk\n");1061 goto err_adc_clk;1062 }1063 1064 meson_sar_adc_unlock(indio_dev);1065 1066 return 0;1067 1068err_adc_clk:1069 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,1070 MESON_SAR_ADC_REG3_ADC_EN);1071 meson_sar_adc_set_bandgap(indio_dev, false);1072 regulator_disable(priv->vref);1073err_vref:1074 meson_sar_adc_unlock(indio_dev);1075err_lock:1076 return ret;1077}1078 1079static void meson_sar_adc_hw_disable(struct iio_dev *indio_dev)1080{1081 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);1082 int ret;1083 1084 /*1085 * If taking the lock fails we have to assume that BL30 is broken. The1086 * best we can do then is to release the resources anyhow.1087 */1088 ret = meson_sar_adc_lock(indio_dev);1089 if (ret)1090 dev_err(indio_dev->dev.parent, "Failed to lock ADC (%pE)\n", ERR_PTR(ret));1091 1092 clk_disable_unprepare(priv->adc_clk);1093 1094 regmap_clear_bits(priv->regmap, MESON_SAR_ADC_REG3,1095 MESON_SAR_ADC_REG3_ADC_EN);1096 1097 meson_sar_adc_set_bandgap(indio_dev, false);1098 1099 regulator_disable(priv->vref);1100 1101 if (!ret)1102 meson_sar_adc_unlock(indio_dev);1103}1104 1105static irqreturn_t meson_sar_adc_irq(int irq, void *data)1106{1107 struct iio_dev *indio_dev = data;1108 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);1109 unsigned int cnt, threshold;1110 u32 regval;1111 1112 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);1113 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);1114 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);1115 1116 if (cnt < threshold)1117 return IRQ_NONE;1118 1119 complete(&priv->done);1120 1121 return IRQ_HANDLED;1122}1123 1124static int meson_sar_adc_calib(struct iio_dev *indio_dev)1125{1126 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);1127 int ret, nominal0, nominal1, value0, value1;1128 1129 /* use points 25% and 75% for calibration */1130 nominal0 = (1 << priv->param->resolution) / 4;1131 nominal1 = (1 << priv->param->resolution) * 3 / 4;1132 1133 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);1134 usleep_range(10, 20);1135 ret = meson_sar_adc_get_sample(indio_dev,1136 find_channel_by_num(indio_dev,1137 NUM_MUX_1_VDD_DIV4),1138 MEAN_AVERAGING, EIGHT_SAMPLES, &value0);1139 if (ret < 0)1140 goto out;1141 1142 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);1143 usleep_range(10, 20);1144 ret = meson_sar_adc_get_sample(indio_dev,1145 find_channel_by_num(indio_dev,1146 NUM_MUX_3_VDD_MUL3_DIV4),1147 MEAN_AVERAGING, EIGHT_SAMPLES, &value1);1148 if (ret < 0)1149 goto out;1150 1151 if (value1 <= value0) {1152 ret = -EINVAL;1153 goto out;1154 }1155 1156 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,1157 value1 - value0);1158 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,1159 MILLION);1160 ret = 0;1161out:1162 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);1163 1164 return ret;1165}1166 1167static int read_label(struct iio_dev *indio_dev,1168 struct iio_chan_spec const *chan,1169 char *label)1170{1171 if (chan->type == IIO_TEMP)1172 return sprintf(label, "temp-sensor\n");1173 if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS)1174 return sprintf(label, "%s\n",1175 chan7_mux_names[chan->channel - NUM_MUX_0_VSS]);1176 if (chan->type == IIO_VOLTAGE)1177 return sprintf(label, "channel-%d\n", chan->channel);1178 return 0;1179}1180 1181static const struct iio_info meson_sar_adc_iio_info = {1182 .read_raw = meson_sar_adc_iio_info_read_raw,1183 .read_label = read_label,1184};1185 1186static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {1187 .has_bl30_integration = false,1188 .clock_rate = 1150000,1189 .bandgap_reg = MESON_SAR_ADC_DELTA_10,1190 .regmap_config = &meson_sar_adc_regmap_config_meson8,1191 .resolution = 10,1192 .temperature_trimming_bits = 4,1193 .temperature_multiplier = 18 * 10000,1194 .temperature_divider = 1024 * 10 * 85,1195};1196 1197static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {1198 .has_bl30_integration = false,1199 .clock_rate = 1150000,1200 .bandgap_reg = MESON_SAR_ADC_DELTA_10,1201 .regmap_config = &meson_sar_adc_regmap_config_meson8,1202 .resolution = 10,1203 .temperature_trimming_bits = 5,1204 .temperature_multiplier = 10,1205 .temperature_divider = 32,1206};1207 1208static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {1209 .has_bl30_integration = true,1210 .clock_rate = 1200000,1211 .bandgap_reg = MESON_SAR_ADC_REG11,1212 .regmap_config = &meson_sar_adc_regmap_config_gxbb,1213 .resolution = 10,1214 .has_reg11 = true,1215 .vref_volatge = 1,1216 .cmv_select = 1,1217};1218 1219static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {1220 .has_bl30_integration = true,1221 .clock_rate = 1200000,1222 .bandgap_reg = MESON_SAR_ADC_REG11,1223 .regmap_config = &meson_sar_adc_regmap_config_gxbb,1224 .resolution = 12,1225 .disable_ring_counter = 1,1226 .has_reg11 = true,1227 .vref_volatge = 1,1228 .cmv_select = 1,1229};1230 1231static const struct meson_sar_adc_param meson_sar_adc_axg_param = {1232 .has_bl30_integration = true,1233 .clock_rate = 1200000,1234 .bandgap_reg = MESON_SAR_ADC_REG11,1235 .regmap_config = &meson_sar_adc_regmap_config_gxbb,1236 .resolution = 12,1237 .disable_ring_counter = 1,1238 .has_reg11 = true,1239 .vref_volatge = 1,1240 .has_vref_select = true,1241 .vref_select = VREF_VDDA,1242 .cmv_select = 1,1243};1244 1245static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {1246 .has_bl30_integration = false,1247 .clock_rate = 1200000,1248 .bandgap_reg = MESON_SAR_ADC_REG11,1249 .regmap_config = &meson_sar_adc_regmap_config_gxbb,1250 .resolution = 12,1251 .disable_ring_counter = 1,1252 .has_reg11 = true,1253 .adc_eoc = 1,1254 .has_vref_select = true,1255 .vref_select = VREF_VDDA,1256};1257 1258static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {1259 .param = &meson_sar_adc_meson8_param,1260 .name = "meson-meson8-saradc",1261};1262 1263static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {1264 .param = &meson_sar_adc_meson8b_param,1265 .name = "meson-meson8b-saradc",1266};1267 1268static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {1269 .param = &meson_sar_adc_meson8b_param,1270 .name = "meson-meson8m2-saradc",1271};1272 1273static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {1274 .param = &meson_sar_adc_gxbb_param,1275 .name = "meson-gxbb-saradc",1276};1277 1278static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {1279 .param = &meson_sar_adc_gxl_param,1280 .name = "meson-gxl-saradc",1281};1282 1283static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {1284 .param = &meson_sar_adc_gxl_param,1285 .name = "meson-gxm-saradc",1286};1287 1288static const struct meson_sar_adc_data meson_sar_adc_axg_data = {1289 .param = &meson_sar_adc_axg_param,1290 .name = "meson-axg-saradc",1291};1292 1293static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {1294 .param = &meson_sar_adc_g12a_param,1295 .name = "meson-g12a-saradc",1296};1297 1298static const struct of_device_id meson_sar_adc_of_match[] = {1299 {1300 .compatible = "amlogic,meson8-saradc",1301 .data = &meson_sar_adc_meson8_data,1302 }, {1303 .compatible = "amlogic,meson8b-saradc",1304 .data = &meson_sar_adc_meson8b_data,1305 }, {1306 .compatible = "amlogic,meson8m2-saradc",1307 .data = &meson_sar_adc_meson8m2_data,1308 }, {1309 .compatible = "amlogic,meson-gxbb-saradc",1310 .data = &meson_sar_adc_gxbb_data,1311 }, {1312 .compatible = "amlogic,meson-gxl-saradc",1313 .data = &meson_sar_adc_gxl_data,1314 }, {1315 .compatible = "amlogic,meson-gxm-saradc",1316 .data = &meson_sar_adc_gxm_data,1317 }, {1318 .compatible = "amlogic,meson-axg-saradc",1319 .data = &meson_sar_adc_axg_data,1320 }, {1321 .compatible = "amlogic,meson-g12a-saradc",1322 .data = &meson_sar_adc_g12a_data,1323 },1324 { /* sentinel */ }1325};1326MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);1327 1328static int meson_sar_adc_probe(struct platform_device *pdev)1329{1330 const struct meson_sar_adc_data *match_data;1331 struct meson_sar_adc_priv *priv;1332 struct device *dev = &pdev->dev;1333 struct iio_dev *indio_dev;1334 void __iomem *base;1335 int irq, ret;1336 1337 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));1338 if (!indio_dev)1339 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n");1340 1341 priv = iio_priv(indio_dev);1342 init_completion(&priv->done);1343 1344 match_data = of_device_get_match_data(dev);1345 if (!match_data)1346 return dev_err_probe(dev, -ENODEV, "failed to get match data\n");1347 1348 priv->param = match_data->param;1349 1350 indio_dev->name = match_data->name;1351 indio_dev->modes = INDIO_DIRECT_MODE;1352 indio_dev->info = &meson_sar_adc_iio_info;1353 1354 base = devm_platform_ioremap_resource(pdev, 0);1355 if (IS_ERR(base))1356 return PTR_ERR(base);1357 1358 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config);1359 if (IS_ERR(priv->regmap))1360 return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n");1361 1362 irq = irq_of_parse_and_map(dev->of_node, 0);1363 if (!irq)1364 return dev_err_probe(dev, -EINVAL, "failed to get irq\n");1365 1366 ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev);1367 if (ret)1368 return dev_err_probe(dev, ret, "failed to request irq\n");1369 1370 priv->clkin = devm_clk_get(dev, "clkin");1371 if (IS_ERR(priv->clkin))1372 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");1373 1374 priv->core_clk = devm_clk_get_enabled(dev, "core");1375 if (IS_ERR(priv->core_clk))1376 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");1377 1378 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk");1379 if (IS_ERR(priv->adc_clk))1380 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n");1381 1382 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel");1383 if (IS_ERR(priv->adc_sel_clk))1384 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n");1385 1386 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */1387 if (!priv->adc_clk) {1388 ret = meson_sar_adc_clk_init(indio_dev, base);1389 if (ret)1390 return dev_err_probe(dev, ret, "failed to init internal clk\n");1391 }1392 1393 priv->vref = devm_regulator_get(dev, "vref");1394 if (IS_ERR(priv->vref))1395 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n");1396 1397 priv->calibscale = MILLION;1398 1399 if (priv->param->temperature_trimming_bits) {1400 ret = meson_sar_adc_temp_sensor_init(indio_dev);1401 if (ret)1402 return ret;1403 }1404 1405 if (priv->temperature_sensor_calibrated) {1406 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;1407 indio_dev->num_channels =1408 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);1409 } else {1410 indio_dev->channels = meson_sar_adc_iio_channels;1411 indio_dev->num_channels =1412 ARRAY_SIZE(meson_sar_adc_iio_channels);1413 }1414 1415 ret = meson_sar_adc_init(indio_dev);1416 if (ret)1417 goto err;1418 1419 mutex_init(&priv->lock);1420 1421 ret = meson_sar_adc_hw_enable(indio_dev);1422 if (ret)1423 goto err;1424 1425 ret = meson_sar_adc_calib(indio_dev);1426 if (ret)1427 dev_warn(dev, "calibration failed\n");1428 1429 platform_set_drvdata(pdev, indio_dev);1430 1431 ret = iio_device_register(indio_dev);1432 if (ret) {1433 dev_err_probe(dev, ret, "failed to register iio device\n");1434 goto err_hw;1435 }1436 1437 return 0;1438 1439err_hw:1440 meson_sar_adc_hw_disable(indio_dev);1441err:1442 return ret;1443}1444 1445static void meson_sar_adc_remove(struct platform_device *pdev)1446{1447 struct iio_dev *indio_dev = platform_get_drvdata(pdev);1448 1449 iio_device_unregister(indio_dev);1450 1451 meson_sar_adc_hw_disable(indio_dev);1452}1453 1454static int meson_sar_adc_suspend(struct device *dev)1455{1456 struct iio_dev *indio_dev = dev_get_drvdata(dev);1457 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);1458 1459 meson_sar_adc_hw_disable(indio_dev);1460 1461 clk_disable_unprepare(priv->core_clk);1462 1463 return 0;1464}1465 1466static int meson_sar_adc_resume(struct device *dev)1467{1468 struct iio_dev *indio_dev = dev_get_drvdata(dev);1469 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);1470 int ret;1471 1472 ret = clk_prepare_enable(priv->core_clk);1473 if (ret) {1474 dev_err(dev, "failed to enable core clk\n");1475 return ret;1476 }1477 1478 return meson_sar_adc_hw_enable(indio_dev);1479}1480 1481static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,1482 meson_sar_adc_suspend, meson_sar_adc_resume);1483 1484static struct platform_driver meson_sar_adc_driver = {1485 .probe = meson_sar_adc_probe,1486 .remove_new = meson_sar_adc_remove,1487 .driver = {1488 .name = "meson-saradc",1489 .of_match_table = meson_sar_adc_of_match,1490 .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops),1491 },1492};1493 1494module_platform_driver(meson_sar_adc_driver);1495 1496MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");1497MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");1498MODULE_LICENSE("GPL v2");1499