598 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * RZ/G2L A/D Converter driver4 *5 * Copyright (c) 2021 Renesas Electronics Europe GmbH6 *7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>8 */9 10#include <linux/bitfield.h>11#include <linux/clk.h>12#include <linux/completion.h>13#include <linux/delay.h>14#include <linux/iio/iio.h>15#include <linux/interrupt.h>16#include <linux/io.h>17#include <linux/mod_devicetable.h>18#include <linux/module.h>19#include <linux/platform_device.h>20#include <linux/pm_runtime.h>21#include <linux/property.h>22#include <linux/reset.h>23 24#define DRIVER_NAME "rzg2l-adc"25 26#define RZG2L_ADM(n) ((n) * 0x4)27#define RZG2L_ADM0_ADCE BIT(0)28#define RZG2L_ADM0_ADBSY BIT(1)29#define RZG2L_ADM0_PWDWNB BIT(2)30#define RZG2L_ADM0_SRESB BIT(15)31#define RZG2L_ADM1_TRG BIT(0)32#define RZG2L_ADM1_MS BIT(2)33#define RZG2L_ADM1_BS BIT(4)34#define RZG2L_ADM1_EGA_MASK GENMASK(13, 12)35#define RZG2L_ADM2_CHSEL_MASK GENMASK(7, 0)36#define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24)37#define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16)38#define RZG2L_ADM3_ADCMP_E FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, 0xe)39#define RZG2L_ADM3_ADSMP_MASK GENMASK(15, 0)40 41#define RZG2L_ADINT 0x2042#define RZG2L_ADINT_INTEN_MASK GENMASK(7, 0)43#define RZG2L_ADINT_CSEEN BIT(16)44#define RZG2L_ADINT_INTS BIT(31)45 46#define RZG2L_ADSTS 0x2447#define RZG2L_ADSTS_CSEST BIT(16)48#define RZG2L_ADSTS_INTST_MASK GENMASK(7, 0)49 50#define RZG2L_ADIVC 0x2851#define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0)52#define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4)53 54#define RZG2L_ADFIL 0x2c55 56#define RZG2L_ADCR(n) (0x30 + ((n) * 0x4))57#define RZG2L_ADCR_AD_MASK GENMASK(11, 0)58 59#define RZG2L_ADSMP_DEFAULT_SAMPLING 0x57860 61#define RZG2L_ADC_MAX_CHANNELS 862#define RZG2L_ADC_CHN_MASK 0x763#define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4)64 65struct rzg2l_adc_data {66 const struct iio_chan_spec *channels;67 u8 num_channels;68};69 70struct rzg2l_adc {71 void __iomem *base;72 struct clk *pclk;73 struct clk *adclk;74 struct reset_control *presetn;75 struct reset_control *adrstn;76 struct completion completion;77 const struct rzg2l_adc_data *data;78 struct mutex lock;79 u16 last_val[RZG2L_ADC_MAX_CHANNELS];80};81 82static const char * const rzg2l_adc_channel_name[] = {83 "adc0",84 "adc1",85 "adc2",86 "adc3",87 "adc4",88 "adc5",89 "adc6",90 "adc7",91};92 93static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)94{95 return readl(adc->base + reg);96}97 98static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)99{100 writel(val, adc->base + reg);101}102 103static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)104{105 u32 reg;106 107 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));108 if (on)109 reg |= RZG2L_ADM0_PWDWNB;110 else111 reg &= ~RZG2L_ADM0_PWDWNB;112 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);113 udelay(2);114}115 116static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)117{118 int timeout = 5;119 u32 reg;120 121 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));122 if (start)123 reg |= RZG2L_ADM0_ADCE;124 else125 reg &= ~RZG2L_ADM0_ADCE;126 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);127 128 if (start)129 return;130 131 do {132 usleep_range(100, 200);133 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));134 timeout--;135 if (!timeout) {136 pr_err("%s stopping ADC timed out\n", __func__);137 break;138 }139 } while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE)));140}141 142static void rzg2l_set_trigger(struct rzg2l_adc *adc)143{144 u32 reg;145 146 /*147 * Setup ADM1 for SW trigger148 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid149 * BS[4] - Enable 1-buffer mode150 * MS[1] - Enable Select mode151 * TRG[0] - Enable software trigger mode152 */153 reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));154 reg &= ~RZG2L_ADM1_EGA_MASK;155 reg &= ~RZG2L_ADM1_BS;156 reg &= ~RZG2L_ADM1_TRG;157 reg |= RZG2L_ADM1_MS;158 rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);159}160 161static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)162{163 u32 reg;164 165 if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)166 return -EBUSY;167 168 rzg2l_set_trigger(adc);169 170 /* Select analog input channel subjected to conversion. */171 reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));172 reg &= ~RZG2L_ADM2_CHSEL_MASK;173 reg |= BIT(ch);174 rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);175 176 /*177 * Setup ADINT178 * INTS[31] - Select pulse signal179 * CSEEN[16] - Enable channel select error interrupt180 * INTEN[7:0] - Select channel interrupt181 */182 reg = rzg2l_adc_readl(adc, RZG2L_ADINT);183 reg &= ~RZG2L_ADINT_INTS;184 reg &= ~RZG2L_ADINT_INTEN_MASK;185 reg |= (RZG2L_ADINT_CSEEN | BIT(ch));186 rzg2l_adc_writel(adc, RZG2L_ADINT, reg);187 188 return 0;189}190 191static int rzg2l_adc_set_power(struct iio_dev *indio_dev, bool on)192{193 struct device *dev = indio_dev->dev.parent;194 195 if (on)196 return pm_runtime_resume_and_get(dev);197 198 return pm_runtime_put_sync(dev);199}200 201static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)202{203 int ret;204 205 ret = rzg2l_adc_set_power(indio_dev, true);206 if (ret)207 return ret;208 209 ret = rzg2l_adc_conversion_setup(adc, ch);210 if (ret) {211 rzg2l_adc_set_power(indio_dev, false);212 return ret;213 }214 215 reinit_completion(&adc->completion);216 217 rzg2l_adc_start_stop(adc, true);218 219 if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {220 rzg2l_adc_writel(adc, RZG2L_ADINT,221 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK);222 rzg2l_adc_start_stop(adc, false);223 rzg2l_adc_set_power(indio_dev, false);224 return -ETIMEDOUT;225 }226 227 return rzg2l_adc_set_power(indio_dev, false);228}229 230static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,231 struct iio_chan_spec const *chan,232 int *val, int *val2, long mask)233{234 struct rzg2l_adc *adc = iio_priv(indio_dev);235 int ret;236 u8 ch;237 238 switch (mask) {239 case IIO_CHAN_INFO_RAW:240 if (chan->type != IIO_VOLTAGE)241 return -EINVAL;242 243 mutex_lock(&adc->lock);244 ch = chan->channel & RZG2L_ADC_CHN_MASK;245 ret = rzg2l_adc_conversion(indio_dev, adc, ch);246 if (ret) {247 mutex_unlock(&adc->lock);248 return ret;249 }250 *val = adc->last_val[ch];251 mutex_unlock(&adc->lock);252 253 return IIO_VAL_INT;254 255 default:256 return -EINVAL;257 }258}259 260static int rzg2l_adc_read_label(struct iio_dev *iio_dev,261 const struct iio_chan_spec *chan,262 char *label)263{264 return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]);265}266 267static const struct iio_info rzg2l_adc_iio_info = {268 .read_raw = rzg2l_adc_read_raw,269 .read_label = rzg2l_adc_read_label,270};271 272static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)273{274 struct rzg2l_adc *adc = dev_id;275 unsigned long intst;276 u32 reg;277 int ch;278 279 reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);280 281 /* A/D conversion channel select error interrupt */282 if (reg & RZG2L_ADSTS_CSEST) {283 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);284 return IRQ_HANDLED;285 }286 287 intst = reg & RZG2L_ADSTS_INTST_MASK;288 if (!intst)289 return IRQ_NONE;290 291 for_each_set_bit(ch, &intst, RZG2L_ADC_MAX_CHANNELS)292 adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;293 294 /* clear the channel interrupt */295 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);296 297 complete(&adc->completion);298 299 return IRQ_HANDLED;300}301 302static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)303{304 struct iio_chan_spec *chan_array;305 struct rzg2l_adc_data *data;306 unsigned int channel;307 int num_channels;308 int ret;309 u8 i;310 311 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);312 if (!data)313 return -ENOMEM;314 315 num_channels = device_get_child_node_count(&pdev->dev);316 if (!num_channels) {317 dev_err(&pdev->dev, "no channel children\n");318 return -ENODEV;319 }320 321 if (num_channels > RZG2L_ADC_MAX_CHANNELS) {322 dev_err(&pdev->dev, "num of channel children out of range\n");323 return -EINVAL;324 }325 326 chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array),327 GFP_KERNEL);328 if (!chan_array)329 return -ENOMEM;330 331 i = 0;332 device_for_each_child_node_scoped(&pdev->dev, fwnode) {333 ret = fwnode_property_read_u32(fwnode, "reg", &channel);334 if (ret)335 return ret;336 337 if (channel >= RZG2L_ADC_MAX_CHANNELS)338 return -EINVAL;339 340 chan_array[i].type = IIO_VOLTAGE;341 chan_array[i].indexed = 1;342 chan_array[i].channel = channel;343 chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);344 chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel];345 i++;346 }347 348 data->num_channels = num_channels;349 data->channels = chan_array;350 adc->data = data;351 352 return 0;353}354 355static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)356{357 int timeout = 5;358 u32 reg;359 int ret;360 361 ret = clk_prepare_enable(adc->pclk);362 if (ret)363 return ret;364 365 /* SW reset */366 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));367 reg |= RZG2L_ADM0_SRESB;368 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);369 370 while (!(rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_SRESB)) {371 if (!timeout) {372 ret = -EBUSY;373 goto exit_hw_init;374 }375 timeout--;376 usleep_range(100, 200);377 }378 379 /* Only division by 4 can be set */380 reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);381 reg &= ~RZG2L_ADIVC_DIVADC_MASK;382 reg |= RZG2L_ADIVC_DIVADC_4;383 rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);384 385 /*386 * Setup AMD3387 * ADIL[31:24] - Should be always set to 0388 * ADCMP[23:16] - Should be always set to 0xe389 * ADSMP[15:0] - Set default (0x578) sampling period390 */391 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));392 reg &= ~RZG2L_ADM3_ADIL_MASK;393 reg &= ~RZG2L_ADM3_ADCMP_MASK;394 reg &= ~RZG2L_ADM3_ADSMP_MASK;395 reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFAULT_SAMPLING);396 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);397 398exit_hw_init:399 clk_disable_unprepare(adc->pclk);400 401 return ret;402}403 404static void rzg2l_adc_pm_runtime_disable(void *data)405{406 struct device *dev = data;407 408 pm_runtime_disable(dev->parent);409}410 411static void rzg2l_adc_pm_runtime_set_suspended(void *data)412{413 struct device *dev = data;414 415 pm_runtime_set_suspended(dev->parent);416}417 418static void rzg2l_adc_reset_assert(void *data)419{420 reset_control_assert(data);421}422 423static int rzg2l_adc_probe(struct platform_device *pdev)424{425 struct device *dev = &pdev->dev;426 struct iio_dev *indio_dev;427 struct rzg2l_adc *adc;428 int ret;429 int irq;430 431 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));432 if (!indio_dev)433 return -ENOMEM;434 435 adc = iio_priv(indio_dev);436 437 ret = rzg2l_adc_parse_properties(pdev, adc);438 if (ret)439 return ret;440 441 mutex_init(&adc->lock);442 443 adc->base = devm_platform_ioremap_resource(pdev, 0);444 if (IS_ERR(adc->base))445 return PTR_ERR(adc->base);446 447 adc->pclk = devm_clk_get(dev, "pclk");448 if (IS_ERR(adc->pclk)) {449 dev_err(dev, "Failed to get pclk");450 return PTR_ERR(adc->pclk);451 }452 453 adc->adclk = devm_clk_get(dev, "adclk");454 if (IS_ERR(adc->adclk)) {455 dev_err(dev, "Failed to get adclk");456 return PTR_ERR(adc->adclk);457 }458 459 adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n");460 if (IS_ERR(adc->adrstn)) {461 dev_err(dev, "failed to get adrstn\n");462 return PTR_ERR(adc->adrstn);463 }464 465 adc->presetn = devm_reset_control_get_exclusive(dev, "presetn");466 if (IS_ERR(adc->presetn)) {467 dev_err(dev, "failed to get presetn\n");468 return PTR_ERR(adc->presetn);469 }470 471 ret = reset_control_deassert(adc->adrstn);472 if (ret) {473 dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret);474 return ret;475 }476 477 ret = devm_add_action_or_reset(&pdev->dev,478 rzg2l_adc_reset_assert, adc->adrstn);479 if (ret) {480 dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n",481 ret);482 return ret;483 }484 485 ret = reset_control_deassert(adc->presetn);486 if (ret) {487 dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret);488 return ret;489 }490 491 ret = devm_add_action_or_reset(&pdev->dev,492 rzg2l_adc_reset_assert, adc->presetn);493 if (ret) {494 dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n",495 ret);496 return ret;497 }498 499 ret = rzg2l_adc_hw_init(adc);500 if (ret) {501 dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret);502 return ret;503 }504 505 irq = platform_get_irq(pdev, 0);506 if (irq < 0)507 return irq;508 509 ret = devm_request_irq(dev, irq, rzg2l_adc_isr,510 0, dev_name(dev), adc);511 if (ret < 0)512 return ret;513 514 init_completion(&adc->completion);515 516 platform_set_drvdata(pdev, indio_dev);517 518 indio_dev->name = DRIVER_NAME;519 indio_dev->info = &rzg2l_adc_iio_info;520 indio_dev->modes = INDIO_DIRECT_MODE;521 indio_dev->channels = adc->data->channels;522 indio_dev->num_channels = adc->data->num_channels;523 524 pm_runtime_set_suspended(dev);525 ret = devm_add_action_or_reset(&pdev->dev,526 rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev);527 if (ret)528 return ret;529 530 pm_runtime_enable(dev);531 ret = devm_add_action_or_reset(&pdev->dev,532 rzg2l_adc_pm_runtime_disable, &indio_dev->dev);533 if (ret)534 return ret;535 536 return devm_iio_device_register(dev, indio_dev);537}538 539static const struct of_device_id rzg2l_adc_match[] = {540 { .compatible = "renesas,rzg2l-adc",},541 { /* sentinel */ }542};543MODULE_DEVICE_TABLE(of, rzg2l_adc_match);544 545static int __maybe_unused rzg2l_adc_pm_runtime_suspend(struct device *dev)546{547 struct iio_dev *indio_dev = dev_get_drvdata(dev);548 struct rzg2l_adc *adc = iio_priv(indio_dev);549 550 rzg2l_adc_pwr(adc, false);551 clk_disable_unprepare(adc->adclk);552 clk_disable_unprepare(adc->pclk);553 554 return 0;555}556 557static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev)558{559 struct iio_dev *indio_dev = dev_get_drvdata(dev);560 struct rzg2l_adc *adc = iio_priv(indio_dev);561 int ret;562 563 ret = clk_prepare_enable(adc->pclk);564 if (ret)565 return ret;566 567 ret = clk_prepare_enable(adc->adclk);568 if (ret) {569 clk_disable_unprepare(adc->pclk);570 return ret;571 }572 573 rzg2l_adc_pwr(adc, true);574 575 return 0;576}577 578static const struct dev_pm_ops rzg2l_adc_pm_ops = {579 SET_RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend,580 rzg2l_adc_pm_runtime_resume,581 NULL)582};583 584static struct platform_driver rzg2l_adc_driver = {585 .probe = rzg2l_adc_probe,586 .driver = {587 .name = DRIVER_NAME,588 .of_match_table = rzg2l_adc_match,589 .pm = &rzg2l_adc_pm_ops,590 },591};592 593module_platform_driver(rzg2l_adc_driver);594 595MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");596MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");597MODULE_LICENSE("GPL v2");598