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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This file is part of STM32 DFSDM driver4 *5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved6 * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>.7 */8 9#ifndef MDF_STM32_DFSDM__H10#define MDF_STM32_DFSDM__H11 12#include <linux/bitfield.h>13 14/*15 * STM32 DFSDM - global register map16 * __________________________________________________________17 * | Offset | Registers block |18 * ----------------------------------------------------------19 * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |20 * ----------------------------------------------------------21 * | 0x020 | CHANNEL 1 |22 * ----------------------------------------------------------23 * | ... | ..... |24 * ----------------------------------------------------------25 * | 0x20 x n | CHANNEL n |26 * ----------------------------------------------------------27 * | 0x100 | FILTER 0 + COMMON FILTER FIELDs |28 * ----------------------------------------------------------29 * | 0x200 | FILTER 1 |30 * ----------------------------------------------------------31 * | | ..... |32 * ----------------------------------------------------------33 * | 0x100 x m | FILTER m |34 * ----------------------------------------------------------35 * | | ..... |36 * ----------------------------------------------------------37 * | 0x7F0-7FC | Identification registers |38 * ----------------------------------------------------------39 */40 41/*42 * Channels register definitions43 */44#define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)45#define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)46#define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)47#define DFSDM_CHWDATR(y) ((y) * 0x20 + 0x0C)48#define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10)49 50/* CHCFGR1: Channel configuration register 1 */51#define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0)52#define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)53#define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)54#define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)55#define DFSDM_CHCFGR1_SCDEN_MASK BIT(5)56#define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)57#define DFSDM_CHCFGR1_CKABEN_MASK BIT(6)58#define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)59#define DFSDM_CHCFGR1_CHEN_MASK BIT(7)60#define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)61#define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8)62#define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)63#define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12)64#define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)65#define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)66#define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)67#define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)68#define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)69#define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30)70#define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)71#define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31)72#define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)73 74/* CHCFGR2: Channel configuration register 2 */75#define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3)76#define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)77#define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8)78#define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)79 80/* AWSCDR: Channel analog watchdog and short circuit detector */81#define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0)82#define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)83#define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12)84#define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)85#define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16)86#define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)87#define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22)88#define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)89 90/*91 * Filters register definitions92 */93#define DFSDM_FILTER_BASE_ADR 0x10094#define DFSDM_FILTER_REG_MASK 0x7F95#define DFSDM_FILTER_X_BASE_ADR(x) ((x) * 0x80 + DFSDM_FILTER_BASE_ADR)96 97#define DFSDM_CR1(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x00)98#define DFSDM_CR2(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x04)99#define DFSDM_ISR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x08)100#define DFSDM_ICR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x0C)101#define DFSDM_JCHGR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x10)102#define DFSDM_FCR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x14)103#define DFSDM_JDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x18)104#define DFSDM_RDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x1C)105#define DFSDM_AWHTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x20)106#define DFSDM_AWLTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x24)107#define DFSDM_AWSR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x28)108#define DFSDM_AWCFR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x2C)109#define DFSDM_EXMAX(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x30)110#define DFSDM_EXMIN(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x34)111#define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x38)112 113/* CR1 Control register 1 */114#define DFSDM_CR1_DFEN_MASK BIT(0)115#define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)116#define DFSDM_CR1_JSWSTART_MASK BIT(1)117#define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)118#define DFSDM_CR1_JSYNC_MASK BIT(3)119#define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)120#define DFSDM_CR1_JSCAN_MASK BIT(4)121#define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)122#define DFSDM_CR1_JDMAEN_MASK BIT(5)123#define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)124#define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8)125#define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)126#define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13)127#define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)128#define DFSDM_CR1_RSWSTART_MASK BIT(17)129#define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)130#define DFSDM_CR1_RCONT_MASK BIT(18)131#define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)132#define DFSDM_CR1_RSYNC_MASK BIT(19)133#define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)134#define DFSDM_CR1_RDMAEN_MASK BIT(21)135#define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)136#define DFSDM_CR1_RCH_MASK GENMASK(26, 24)137#define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)138#define DFSDM_CR1_FAST_MASK BIT(29)139#define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)140#define DFSDM_CR1_AWFSEL_MASK BIT(30)141#define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)142 143/* CR2: Control register 2 */144#define DFSDM_CR2_IE_MASK GENMASK(6, 0)145#define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)146#define DFSDM_CR2_JEOCIE_MASK BIT(0)147#define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)148#define DFSDM_CR2_REOCIE_MASK BIT(1)149#define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)150#define DFSDM_CR2_JOVRIE_MASK BIT(2)151#define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)152#define DFSDM_CR2_ROVRIE_MASK BIT(3)153#define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)154#define DFSDM_CR2_AWDIE_MASK BIT(4)155#define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)156#define DFSDM_CR2_SCDIE_MASK BIT(5)157#define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)158#define DFSDM_CR2_CKABIE_MASK BIT(6)159#define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)160#define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)161#define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)162#define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16)163#define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)164 165/* ISR: Interrupt status register */166#define DFSDM_ISR_JEOCF_MASK BIT(0)167#define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)168#define DFSDM_ISR_REOCF_MASK BIT(1)169#define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)170#define DFSDM_ISR_JOVRF_MASK BIT(2)171#define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)172#define DFSDM_ISR_ROVRF_MASK BIT(3)173#define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)174#define DFSDM_ISR_AWDF_MASK BIT(4)175#define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)176#define DFSDM_ISR_JCIP_MASK BIT(13)177#define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)178#define DFSDM_ISR_RCIP_MASK BIT(14)179#define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)180#define DFSDM_ISR_CKABF_MASK GENMASK(23, 16)181#define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)182#define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)183#define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)184 185/* ICR: Interrupt flag clear register */186#define DFSDM_ICR_CLRJOVRF_MASK BIT(2)187#define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)188#define DFSDM_ICR_CLRROVRF_MASK BIT(3)189#define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)190#define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16)191#define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)192#define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y))193#define DFSDM_ICR_CLRCKABF_CH(v, y) \194 (((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))195#define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24)196#define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)197#define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y))198#define DFSDM_ICR_CLRSCDF_CH(v, y) \199 (((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))200 201/* FCR: Filter control register */202#define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)203#define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)204#define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)205#define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)206#define DFSDM_FCR_FORD_MASK GENMASK(31, 29)207#define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v)208 209/* RDATAR: Filter data register for regular channel */210#define DFSDM_DATAR_CH_MASK GENMASK(2, 0)211#define DFSDM_DATAR_DATA_OFFSET 8212#define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET)213 214/* AWLTR: Filter analog watchdog low threshold register */215#define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0)216#define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)217#define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8)218#define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)219 220/* AWHTR: Filter analog watchdog low threshold register */221#define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0)222#define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)223#define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8)224#define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)225 226/* AWSR: Filter watchdog status register */227#define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0)228#define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)229#define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8)230#define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)231 232/* AWCFR: Filter watchdog status register */233#define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0)234#define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)235#define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)236#define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)237 238/*239 * Identification register definitions240 */241#define DFSDM_HWCFGR 0x7F0242#define DFSDM_VERR 0x7F4243#define DFSDM_IPIDR 0x7F8244#define DFSDM_SIDR 0x7FC245 246/* HWCFGR: Hardware configuration register */247#define DFSDM_HWCFGR_NBT_MASK GENMASK(7, 0)248#define DFSDM_HWCFGR_NBF_MASK GENMASK(15, 8)249 250/* VERR: Version register */251#define DFSDM_VERR_MINREV_MASK GENMASK(3, 0)252#define DFSDM_VERR_MAJREV_MASK GENMASK(7, 4)253 254#define STM32MP15_IPIDR_NUMBER 0x00110031255 256/* DFSDM filter order */257enum stm32_dfsdm_sinc_order {258 DFSDM_FASTSINC_ORDER, /* FastSinc filter type */259 DFSDM_SINC1_ORDER, /* Sinc 1 filter type */260 DFSDM_SINC2_ORDER, /* Sinc 2 filter type */261 DFSDM_SINC3_ORDER, /* Sinc 3 filter type */262 DFSDM_SINC4_ORDER, /* Sinc 4 filter type (N.A. for watchdog) */263 DFSDM_SINC5_ORDER, /* Sinc 5 filter type (N.A. for watchdog) */264 DFSDM_NB_SINC_ORDER,265};266 267/**268 * struct stm32_dfsdm_filter_osr - DFSDM filter settings linked to oversampling269 * @iosr: integrator oversampling270 * @fosr: filter oversampling271 * @rshift: output sample right shift (hardware shift)272 * @lshift: output sample left shift (software shift)273 * @res: output sample resolution274 * @bits: output sample resolution in bits275 * @max: output sample maximum positive value276 */277struct stm32_dfsdm_filter_osr {278 unsigned int iosr;279 unsigned int fosr;280 unsigned int rshift;281 unsigned int lshift;282 u64 res;283 u32 bits;284 s32 max;285};286 287/**288 * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter289 * @ford: filter order290 * @flo: filter oversampling data table indexed by fast mode flag291 * @sync_mode: filter synchronized with filter 0292 * @fast: filter fast mode293 */294struct stm32_dfsdm_filter {295 enum stm32_dfsdm_sinc_order ford;296 struct stm32_dfsdm_filter_osr flo[2];297 unsigned int sync_mode;298 unsigned int fast;299};300 301/**302 * struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel303 * @id: id of the channel304 * @type: interface type linked to stm32_dfsdm_chan_type305 * @src: interface type linked to stm32_dfsdm_chan_src306 * @alt_si: alternative serial input interface307 */308struct stm32_dfsdm_channel {309 unsigned int id;310 unsigned int type;311 unsigned int src;312 unsigned int alt_si;313};314 315/**316 * struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances)317 * @base: control registers base cpu addr318 * @phys_base: DFSDM IP register physical address319 * @regmap: regmap for register read/write320 * @fl_list: filter resources list321 * @num_fls: number of filter resources available322 * @ch_list: channel resources list323 * @num_chs: number of channel resources available324 * @spi_master_freq: SPI clock out frequency325 */326struct stm32_dfsdm {327 void __iomem *base;328 phys_addr_t phys_base;329 struct regmap *regmap;330 struct stm32_dfsdm_filter *fl_list;331 unsigned int num_fls;332 struct stm32_dfsdm_channel *ch_list;333 unsigned int num_chs;334 unsigned int spi_master_freq;335};336 337/* DFSDM channel serial spi clock source */338enum stm32_dfsdm_spi_clk_src {339 DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL,340 DFSDM_CHANNEL_SPI_CLOCK_INTERNAL,341 DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING,342 DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING343};344 345int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm);346int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm);347 348#endif349