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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * ADC12130/ADC12132/ADC12138 12-bit plus sign ADC driver4 *5 * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>6 *7 * Datasheet: http://www.ti.com/lit/ds/symlink/adc12138.pdf8 */9 10#include <linux/module.h>11#include <linux/interrupt.h>12#include <linux/completion.h>13#include <linux/clk.h>14#include <linux/property.h>15#include <linux/spi/spi.h>16#include <linux/iio/iio.h>17#include <linux/iio/buffer.h>18#include <linux/iio/trigger.h>19#include <linux/iio/triggered_buffer.h>20#include <linux/iio/trigger_consumer.h>21#include <linux/regulator/consumer.h>22 23#define ADC12138_MODE_AUTO_CAL 0x0824#define ADC12138_MODE_READ_STATUS 0x0c25#define ADC12138_MODE_ACQUISITION_TIME_6 0x0e26#define ADC12138_MODE_ACQUISITION_TIME_10 0x4e27#define ADC12138_MODE_ACQUISITION_TIME_18 0x8e28#define ADC12138_MODE_ACQUISITION_TIME_34 0xce29 30#define ADC12138_STATUS_CAL BIT(6)31 32enum {33 adc12130,34 adc12132,35 adc12138,36};37 38struct adc12138 {39 struct spi_device *spi;40 unsigned int id;41 /* conversion clock */42 struct clk *cclk;43 /* positive analog voltage reference */44 struct regulator *vref_p;45 /* negative analog voltage reference */46 struct regulator *vref_n;47 struct mutex lock;48 struct completion complete;49 /* The number of cclk periods for the S/H's acquisition time */50 unsigned int acquisition_time;51 /*52 * Maximum size needed: 16x 2 bytes ADC data + 8 bytes timestamp.53 * Less may be need if not all channels are enabled, as long as54 * the 8 byte alignment of the timestamp is maintained.55 */56 __be16 data[20] __aligned(8);57 58 u8 tx_buf[2] __aligned(IIO_DMA_MINALIGN);59 u8 rx_buf[2];60};61 62#define ADC12138_VOLTAGE_CHANNEL(chan) \63 { \64 .type = IIO_VOLTAGE, \65 .indexed = 1, \66 .channel = chan, \67 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \68 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \69 | BIT(IIO_CHAN_INFO_OFFSET), \70 .scan_index = chan, \71 .scan_type = { \72 .sign = 's', \73 .realbits = 13, \74 .storagebits = 16, \75 .shift = 3, \76 .endianness = IIO_BE, \77 }, \78 }79 80#define ADC12138_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \81 { \82 .type = IIO_VOLTAGE, \83 .indexed = 1, \84 .channel = (chan1), \85 .channel2 = (chan2), \86 .differential = 1, \87 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \88 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \89 | BIT(IIO_CHAN_INFO_OFFSET), \90 .scan_index = si, \91 .scan_type = { \92 .sign = 's', \93 .realbits = 13, \94 .storagebits = 16, \95 .shift = 3, \96 .endianness = IIO_BE, \97 }, \98 }99 100static const struct iio_chan_spec adc12132_channels[] = {101 ADC12138_VOLTAGE_CHANNEL(0),102 ADC12138_VOLTAGE_CHANNEL(1),103 ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 2),104 ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 3),105 IIO_CHAN_SOFT_TIMESTAMP(4),106};107 108static const struct iio_chan_spec adc12138_channels[] = {109 ADC12138_VOLTAGE_CHANNEL(0),110 ADC12138_VOLTAGE_CHANNEL(1),111 ADC12138_VOLTAGE_CHANNEL(2),112 ADC12138_VOLTAGE_CHANNEL(3),113 ADC12138_VOLTAGE_CHANNEL(4),114 ADC12138_VOLTAGE_CHANNEL(5),115 ADC12138_VOLTAGE_CHANNEL(6),116 ADC12138_VOLTAGE_CHANNEL(7),117 ADC12138_VOLTAGE_CHANNEL_DIFF(0, 1, 8),118 ADC12138_VOLTAGE_CHANNEL_DIFF(1, 0, 9),119 ADC12138_VOLTAGE_CHANNEL_DIFF(2, 3, 10),120 ADC12138_VOLTAGE_CHANNEL_DIFF(3, 2, 11),121 ADC12138_VOLTAGE_CHANNEL_DIFF(4, 5, 12),122 ADC12138_VOLTAGE_CHANNEL_DIFF(5, 4, 13),123 ADC12138_VOLTAGE_CHANNEL_DIFF(6, 7, 14),124 ADC12138_VOLTAGE_CHANNEL_DIFF(7, 6, 15),125 IIO_CHAN_SOFT_TIMESTAMP(16),126};127 128static int adc12138_mode_programming(struct adc12138 *adc, u8 mode,129 void *rx_buf, int len)130{131 struct spi_transfer xfer = {132 .tx_buf = adc->tx_buf,133 .rx_buf = adc->rx_buf,134 .len = len,135 };136 int ret;137 138 /* Skip unused bits for ADC12130 and ADC12132 */139 if (adc->id != adc12138)140 mode = (mode & 0xc0) | ((mode & 0x0f) << 2);141 142 adc->tx_buf[0] = mode;143 144 ret = spi_sync_transfer(adc->spi, &xfer, 1);145 if (ret)146 return ret;147 148 memcpy(rx_buf, adc->rx_buf, len);149 150 return 0;151}152 153static int adc12138_read_status(struct adc12138 *adc)154{155 u8 rx_buf[2];156 int ret;157 158 ret = adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,159 rx_buf, 2);160 if (ret)161 return ret;162 163 return (rx_buf[0] << 1) | (rx_buf[1] >> 7);164}165 166static int __adc12138_start_conv(struct adc12138 *adc,167 struct iio_chan_spec const *channel,168 void *data, int len)169 170{171 static const u8 ch_to_mux[] = { 0, 4, 1, 5, 2, 6, 3, 7 };172 u8 mode = (ch_to_mux[channel->channel] << 4) |173 (channel->differential ? 0 : 0x80);174 175 return adc12138_mode_programming(adc, mode, data, len);176}177 178static int adc12138_start_conv(struct adc12138 *adc,179 struct iio_chan_spec const *channel)180{181 u8 trash;182 183 return __adc12138_start_conv(adc, channel, &trash, 1);184}185 186static int adc12138_start_and_read_conv(struct adc12138 *adc,187 struct iio_chan_spec const *channel,188 __be16 *data)189{190 return __adc12138_start_conv(adc, channel, data, 2);191}192 193static int adc12138_read_conv_data(struct adc12138 *adc, __be16 *value)194{195 /* Issue a read status instruction and read previous conversion data */196 return adc12138_mode_programming(adc, ADC12138_MODE_READ_STATUS,197 value, sizeof(*value));198}199 200static int adc12138_wait_eoc(struct adc12138 *adc, unsigned long timeout)201{202 if (!wait_for_completion_timeout(&adc->complete, timeout))203 return -ETIMEDOUT;204 205 return 0;206}207 208static int adc12138_adc_conversion(struct adc12138 *adc,209 struct iio_chan_spec const *channel,210 __be16 *value)211{212 int ret;213 214 reinit_completion(&adc->complete);215 216 ret = adc12138_start_conv(adc, channel);217 if (ret)218 return ret;219 220 ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));221 if (ret)222 return ret;223 224 return adc12138_read_conv_data(adc, value);225}226 227static int adc12138_read_raw(struct iio_dev *iio,228 struct iio_chan_spec const *channel, int *value,229 int *shift, long mask)230{231 struct adc12138 *adc = iio_priv(iio);232 int ret;233 __be16 data;234 235 switch (mask) {236 case IIO_CHAN_INFO_RAW:237 mutex_lock(&adc->lock);238 ret = adc12138_adc_conversion(adc, channel, &data);239 mutex_unlock(&adc->lock);240 if (ret)241 return ret;242 243 *value = sign_extend32(be16_to_cpu(data) >> channel->scan_type.shift,244 channel->scan_type.realbits - 1);245 246 return IIO_VAL_INT;247 case IIO_CHAN_INFO_SCALE:248 ret = regulator_get_voltage(adc->vref_p);249 if (ret < 0)250 return ret;251 *value = ret;252 253 if (!IS_ERR(adc->vref_n)) {254 ret = regulator_get_voltage(adc->vref_n);255 if (ret < 0)256 return ret;257 *value -= ret;258 }259 260 /* convert regulator output voltage to mV */261 *value /= 1000;262 *shift = channel->scan_type.realbits - 1;263 264 return IIO_VAL_FRACTIONAL_LOG2;265 case IIO_CHAN_INFO_OFFSET:266 if (!IS_ERR(adc->vref_n)) {267 *value = regulator_get_voltage(adc->vref_n);268 if (*value < 0)269 return *value;270 } else {271 *value = 0;272 }273 274 /* convert regulator output voltage to mV */275 *value /= 1000;276 277 return IIO_VAL_INT;278 }279 280 return -EINVAL;281}282 283static const struct iio_info adc12138_info = {284 .read_raw = adc12138_read_raw,285};286 287static int adc12138_init(struct adc12138 *adc)288{289 int ret;290 int status;291 u8 mode;292 u8 trash;293 294 reinit_completion(&adc->complete);295 296 ret = adc12138_mode_programming(adc, ADC12138_MODE_AUTO_CAL, &trash, 1);297 if (ret)298 return ret;299 300 /* data output at this time has no significance */301 status = adc12138_read_status(adc);302 if (status < 0)303 return status;304 305 adc12138_wait_eoc(adc, msecs_to_jiffies(100));306 307 status = adc12138_read_status(adc);308 if (status & ADC12138_STATUS_CAL) {309 dev_warn(&adc->spi->dev,310 "Auto Cal sequence is still in progress: %#x\n",311 status);312 return -EIO;313 }314 315 switch (adc->acquisition_time) {316 case 6:317 mode = ADC12138_MODE_ACQUISITION_TIME_6;318 break;319 case 10:320 mode = ADC12138_MODE_ACQUISITION_TIME_10;321 break;322 case 18:323 mode = ADC12138_MODE_ACQUISITION_TIME_18;324 break;325 case 34:326 mode = ADC12138_MODE_ACQUISITION_TIME_34;327 break;328 default:329 return -EINVAL;330 }331 332 return adc12138_mode_programming(adc, mode, &trash, 1);333}334 335static irqreturn_t adc12138_trigger_handler(int irq, void *p)336{337 struct iio_poll_func *pf = p;338 struct iio_dev *indio_dev = pf->indio_dev;339 struct adc12138 *adc = iio_priv(indio_dev);340 __be16 trash;341 int ret;342 int scan_index;343 int i = 0;344 345 mutex_lock(&adc->lock);346 347 iio_for_each_active_channel(indio_dev, scan_index) {348 const struct iio_chan_spec *scan_chan =349 &indio_dev->channels[scan_index];350 351 reinit_completion(&adc->complete);352 353 ret = adc12138_start_and_read_conv(adc, scan_chan,354 i ? &adc->data[i - 1] : &trash);355 if (ret) {356 dev_warn(&adc->spi->dev,357 "failed to start conversion\n");358 goto out;359 }360 361 ret = adc12138_wait_eoc(adc, msecs_to_jiffies(100));362 if (ret) {363 dev_warn(&adc->spi->dev, "wait eoc timeout\n");364 goto out;365 }366 367 i++;368 }369 370 if (i) {371 ret = adc12138_read_conv_data(adc, &adc->data[i - 1]);372 if (ret) {373 dev_warn(&adc->spi->dev,374 "failed to get conversion data\n");375 goto out;376 }377 }378 379 iio_push_to_buffers_with_timestamp(indio_dev, adc->data,380 iio_get_time_ns(indio_dev));381out:382 mutex_unlock(&adc->lock);383 384 iio_trigger_notify_done(indio_dev->trig);385 386 return IRQ_HANDLED;387}388 389static irqreturn_t adc12138_eoc_handler(int irq, void *p)390{391 struct iio_dev *indio_dev = p;392 struct adc12138 *adc = iio_priv(indio_dev);393 394 complete(&adc->complete);395 396 return IRQ_HANDLED;397}398 399static int adc12138_probe(struct spi_device *spi)400{401 struct iio_dev *indio_dev;402 struct adc12138 *adc;403 int ret;404 405 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));406 if (!indio_dev)407 return -ENOMEM;408 409 adc = iio_priv(indio_dev);410 adc->spi = spi;411 adc->id = spi_get_device_id(spi)->driver_data;412 mutex_init(&adc->lock);413 init_completion(&adc->complete);414 415 indio_dev->name = spi_get_device_id(spi)->name;416 indio_dev->info = &adc12138_info;417 indio_dev->modes = INDIO_DIRECT_MODE;418 419 switch (adc->id) {420 case adc12130:421 case adc12132:422 indio_dev->channels = adc12132_channels;423 indio_dev->num_channels = ARRAY_SIZE(adc12132_channels);424 break;425 case adc12138:426 indio_dev->channels = adc12138_channels;427 indio_dev->num_channels = ARRAY_SIZE(adc12138_channels);428 break;429 default:430 return -EINVAL;431 }432 433 ret = device_property_read_u32(&spi->dev, "ti,acquisition-time",434 &adc->acquisition_time);435 if (ret)436 adc->acquisition_time = 10;437 438 adc->cclk = devm_clk_get(&spi->dev, NULL);439 if (IS_ERR(adc->cclk))440 return PTR_ERR(adc->cclk);441 442 adc->vref_p = devm_regulator_get(&spi->dev, "vref-p");443 if (IS_ERR(adc->vref_p))444 return PTR_ERR(adc->vref_p);445 446 adc->vref_n = devm_regulator_get_optional(&spi->dev, "vref-n");447 if (IS_ERR(adc->vref_n)) {448 /*449 * Assume vref_n is 0V if an optional regulator is not450 * specified, otherwise return the error code.451 */452 ret = PTR_ERR(adc->vref_n);453 if (ret != -ENODEV)454 return ret;455 }456 457 ret = devm_request_irq(&spi->dev, spi->irq, adc12138_eoc_handler,458 IRQF_TRIGGER_RISING, indio_dev->name, indio_dev);459 if (ret)460 return ret;461 462 ret = clk_prepare_enable(adc->cclk);463 if (ret)464 return ret;465 466 ret = regulator_enable(adc->vref_p);467 if (ret)468 goto err_clk_disable;469 470 if (!IS_ERR(adc->vref_n)) {471 ret = regulator_enable(adc->vref_n);472 if (ret)473 goto err_vref_p_disable;474 }475 476 ret = adc12138_init(adc);477 if (ret)478 goto err_vref_n_disable;479 480 spi_set_drvdata(spi, indio_dev);481 482 ret = iio_triggered_buffer_setup(indio_dev, NULL,483 adc12138_trigger_handler, NULL);484 if (ret)485 goto err_vref_n_disable;486 487 ret = iio_device_register(indio_dev);488 if (ret)489 goto err_buffer_cleanup;490 491 return 0;492err_buffer_cleanup:493 iio_triggered_buffer_cleanup(indio_dev);494err_vref_n_disable:495 if (!IS_ERR(adc->vref_n))496 regulator_disable(adc->vref_n);497err_vref_p_disable:498 regulator_disable(adc->vref_p);499err_clk_disable:500 clk_disable_unprepare(adc->cclk);501 502 return ret;503}504 505static void adc12138_remove(struct spi_device *spi)506{507 struct iio_dev *indio_dev = spi_get_drvdata(spi);508 struct adc12138 *adc = iio_priv(indio_dev);509 510 iio_device_unregister(indio_dev);511 iio_triggered_buffer_cleanup(indio_dev);512 if (!IS_ERR(adc->vref_n))513 regulator_disable(adc->vref_n);514 regulator_disable(adc->vref_p);515 clk_disable_unprepare(adc->cclk);516}517 518static const struct of_device_id adc12138_dt_ids[] = {519 { .compatible = "ti,adc12130", },520 { .compatible = "ti,adc12132", },521 { .compatible = "ti,adc12138", },522 { }523};524MODULE_DEVICE_TABLE(of, adc12138_dt_ids);525 526static const struct spi_device_id adc12138_id[] = {527 { "adc12130", adc12130 },528 { "adc12132", adc12132 },529 { "adc12138", adc12138 },530 { }531};532MODULE_DEVICE_TABLE(spi, adc12138_id);533 534static struct spi_driver adc12138_driver = {535 .driver = {536 .name = "adc12138",537 .of_match_table = adc12138_dt_ids,538 },539 .probe = adc12138_probe,540 .remove = adc12138_remove,541 .id_table = adc12138_id,542};543module_spi_driver(adc12138_driver);544 545MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");546MODULE_DESCRIPTION("ADC12130/ADC12132/ADC12138 driver");547MODULE_LICENSE("GPL v2");548