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1// SPDX-License-Identifier: GPL-2.02/* TI ADS1298 chip family driver3 * Copyright (C) 2023 - 2024 Topic Embedded Products4 */5 6#include <linux/bitfield.h>7#include <linux/cleanup.h>8#include <linux/clk.h>9#include <linux/err.h>10#include <linux/delay.h>11#include <linux/device.h>12#include <linux/gpio/consumer.h>13#include <linux/log2.h>14#include <linux/math.h>15#include <linux/module.h>16#include <linux/regmap.h>17#include <linux/regulator/consumer.h>18#include <linux/slab.h>19#include <linux/spi/spi.h>20#include <linux/units.h>21 22#include <linux/iio/iio.h>23#include <linux/iio/buffer.h>24#include <linux/iio/kfifo_buf.h>25 26#include <linux/unaligned.h>27 28/* Commands */29#define ADS1298_CMD_WAKEUP 0x0230#define ADS1298_CMD_STANDBY 0x0431#define ADS1298_CMD_RESET 0x0632#define ADS1298_CMD_START 0x0833#define ADS1298_CMD_STOP 0x0a34#define ADS1298_CMD_RDATAC 0x1035#define ADS1298_CMD_SDATAC 0x1136#define ADS1298_CMD_RDATA 0x1237#define ADS1298_CMD_RREG 0x2038#define ADS1298_CMD_WREG 0x4039 40/* Registers */41#define ADS1298_REG_ID 0x0042#define ADS1298_MASK_ID_FAMILY GENMASK(7, 3)43#define ADS1298_MASK_ID_CHANNELS GENMASK(2, 0)44#define ADS1298_ID_FAMILY_ADS129X 0x9045#define ADS1298_ID_FAMILY_ADS129XR 0xd046 47#define ADS1298_REG_CONFIG1 0x0148#define ADS1298_MASK_CONFIG1_HR BIT(7)49#define ADS1298_MASK_CONFIG1_DR GENMASK(2, 0)50#define ADS1298_SHIFT_DR_HR 651#define ADS1298_SHIFT_DR_LP 752#define ADS1298_LOWEST_DR 0x0653 54#define ADS1298_REG_CONFIG2 0x0255#define ADS1298_MASK_CONFIG2_RESERVED BIT(6)56#define ADS1298_MASK_CONFIG2_WCT_CHOP BIT(5)57#define ADS1298_MASK_CONFIG2_INT_TEST BIT(4)58#define ADS1298_MASK_CONFIG2_TEST_AMP BIT(2)59#define ADS1298_MASK_CONFIG2_TEST_FREQ_DC GENMASK(1, 0)60#define ADS1298_MASK_CONFIG2_TEST_FREQ_SLOW 061#define ADS1298_MASK_CONFIG2_TEST_FREQ_FAST BIT(0)62 63#define ADS1298_REG_CONFIG3 0x0364#define ADS1298_MASK_CONFIG3_PWR_REFBUF BIT(7)65#define ADS1298_MASK_CONFIG3_RESERVED BIT(6)66#define ADS1298_MASK_CONFIG3_VREF_4V BIT(5)67 68#define ADS1298_REG_LOFF 0x0469#define ADS1298_REG_CHnSET(n) (0x05 + n)70#define ADS1298_MASK_CH_PD BIT(7)71#define ADS1298_MASK_CH_PGA GENMASK(6, 4)72#define ADS1298_MASK_CH_MUX GENMASK(2, 0)73 74#define ADS1298_REG_LOFF_STATP 0x1275#define ADS1298_REG_LOFF_STATN 0x1376#define ADS1298_REG_CONFIG4 0x1777#define ADS1298_MASK_CONFIG4_SINGLE_SHOT BIT(3)78 79#define ADS1298_REG_WCT1 0x1880#define ADS1298_REG_WCT2 0x1981 82#define ADS1298_MAX_CHANNELS 883#define ADS1298_BITS_PER_SAMPLE 2484#define ADS1298_CLK_RATE_HZ 204800085#define ADS1298_CLOCKS_TO_USECS(x) \86 (DIV_ROUND_UP((x) * MICROHZ_PER_HZ, ADS1298_CLK_RATE_HZ))87/*88 * Read/write register commands require 4 clocks to decode, for speeds above89 * 2x the clock rate, this would require extra time between the command byte and90 * the data. Much simpler is to just limit the SPI transfer speed while doing91 * register access.92 */93#define ADS1298_SPI_BUS_SPEED_SLOW ADS1298_CLK_RATE_HZ94/* For reading and writing registers, we need a 3-byte buffer */95#define ADS1298_SPI_CMD_BUFFER_SIZE 396/* Outputs status word and 'n' 24-bit samples, plus the command byte */97#define ADS1298_SPI_RDATA_BUFFER_SIZE(n) (((n) + 1) * 3 + 1)98#define ADS1298_SPI_RDATA_BUFFER_SIZE_MAX \99 ADS1298_SPI_RDATA_BUFFER_SIZE(ADS1298_MAX_CHANNELS)100 101struct ads1298_private {102 const struct ads1298_chip_info *chip_info;103 struct spi_device *spi;104 struct regulator *reg_avdd;105 struct regulator *reg_vref;106 struct clk *clk;107 struct regmap *regmap;108 struct completion completion;109 struct iio_trigger *trig;110 struct spi_transfer rdata_xfer;111 struct spi_message rdata_msg;112 spinlock_t irq_busy_lock; /* Handshake between SPI and DRDY irqs */113 /*114 * rdata_xfer_busy increments when a DRDY occurs and decrements when SPI115 * completion is reported. Hence its meaning is:116 * 0 = Waiting for DRDY interrupt117 * 1 = SPI transfer in progress118 * 2 = DRDY during SPI transfer, start another transfer on completion119 * >2 = Multiple DRDY during transfer, lost rdata_xfer_busy - 2 samples120 */121 unsigned int rdata_xfer_busy;122 123 /* Temporary storage for demuxing data after SPI transfer */124 u32 bounce_buffer[ADS1298_MAX_CHANNELS];125 126 /* For synchronous SPI exchanges (read/write registers) */127 u8 cmd_buffer[ADS1298_SPI_CMD_BUFFER_SIZE] __aligned(IIO_DMA_MINALIGN);128 129 /* Buffer used for incoming SPI data */130 u8 rx_buffer[ADS1298_SPI_RDATA_BUFFER_SIZE_MAX];131 /* Contains the RDATA command and zeroes to clock out */132 u8 tx_buffer[ADS1298_SPI_RDATA_BUFFER_SIZE_MAX];133};134 135/* Three bytes per sample in RX buffer, starting at offset 4 */136#define ADS1298_OFFSET_IN_RX_BUFFER(index) (3 * (index) + 4)137 138#define ADS1298_CHAN(index) \139{ \140 .type = IIO_VOLTAGE, \141 .indexed = 1, \142 .channel = index, \143 .address = ADS1298_OFFSET_IN_RX_BUFFER(index), \144 .info_mask_separate = \145 BIT(IIO_CHAN_INFO_RAW) | \146 BIT(IIO_CHAN_INFO_SCALE), \147 .info_mask_shared_by_all = \148 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \149 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \150 .scan_index = index, \151 .scan_type = { \152 .sign = 's', \153 .realbits = ADS1298_BITS_PER_SAMPLE, \154 .storagebits = 32, \155 .endianness = IIO_CPU, \156 }, \157}158 159static const struct iio_chan_spec ads1298_channels[] = {160 ADS1298_CHAN(0),161 ADS1298_CHAN(1),162 ADS1298_CHAN(2),163 ADS1298_CHAN(3),164 ADS1298_CHAN(4),165 ADS1298_CHAN(5),166 ADS1298_CHAN(6),167 ADS1298_CHAN(7),168};169 170static int ads1298_write_cmd(struct ads1298_private *priv, u8 command)171{172 struct spi_transfer xfer = {173 .tx_buf = priv->cmd_buffer,174 .rx_buf = priv->cmd_buffer,175 .len = 1,176 .speed_hz = ADS1298_SPI_BUS_SPEED_SLOW,177 .delay = {178 .value = 2,179 .unit = SPI_DELAY_UNIT_USECS,180 },181 };182 183 priv->cmd_buffer[0] = command;184 185 return spi_sync_transfer(priv->spi, &xfer, 1);186}187 188static int ads1298_read_one(struct ads1298_private *priv, int chan_index)189{190 int ret;191 192 /* Enable the channel */193 ret = regmap_update_bits(priv->regmap, ADS1298_REG_CHnSET(chan_index),194 ADS1298_MASK_CH_PD, 0);195 if (ret)196 return ret;197 198 /* Enable single-shot mode, so we don't need to send a STOP */199 ret = regmap_update_bits(priv->regmap, ADS1298_REG_CONFIG4,200 ADS1298_MASK_CONFIG4_SINGLE_SHOT,201 ADS1298_MASK_CONFIG4_SINGLE_SHOT);202 if (ret)203 return ret;204 205 reinit_completion(&priv->completion);206 207 ret = ads1298_write_cmd(priv, ADS1298_CMD_START);208 if (ret < 0) {209 dev_err(&priv->spi->dev, "CMD_START error: %d\n", ret);210 return ret;211 }212 213 /* Cannot take longer than 40ms (250Hz) */214 ret = wait_for_completion_timeout(&priv->completion, msecs_to_jiffies(50));215 if (!ret)216 return -ETIMEDOUT;217 218 return 0;219}220 221static int ads1298_get_samp_freq(struct ads1298_private *priv, int *val)222{223 unsigned long rate;224 unsigned int cfg;225 int ret;226 227 ret = regmap_read(priv->regmap, ADS1298_REG_CONFIG1, &cfg);228 if (ret)229 return ret;230 231 if (priv->clk)232 rate = clk_get_rate(priv->clk);233 else234 rate = ADS1298_CLK_RATE_HZ;235 if (!rate)236 return -EINVAL;237 238 /* Data rate shift depends on HR/LP mode */239 if (cfg & ADS1298_MASK_CONFIG1_HR)240 rate >>= ADS1298_SHIFT_DR_HR;241 else242 rate >>= ADS1298_SHIFT_DR_LP;243 244 *val = rate >> (cfg & ADS1298_MASK_CONFIG1_DR);245 246 return IIO_VAL_INT;247}248 249static int ads1298_set_samp_freq(struct ads1298_private *priv, int val)250{251 unsigned long rate;252 unsigned int factor;253 unsigned int cfg;254 255 if (priv->clk)256 rate = clk_get_rate(priv->clk);257 else258 rate = ADS1298_CLK_RATE_HZ;259 if (!rate)260 return -EINVAL;261 if (val <= 0)262 return -EINVAL;263 264 factor = (rate >> ADS1298_SHIFT_DR_HR) / val;265 if (factor >= BIT(ADS1298_SHIFT_DR_LP))266 cfg = ADS1298_LOWEST_DR;267 else if (factor)268 cfg = ADS1298_MASK_CONFIG1_HR | ilog2(factor); /* Use HR mode */269 else270 cfg = ADS1298_MASK_CONFIG1_HR; /* Fastest possible */271 272 return regmap_update_bits(priv->regmap, ADS1298_REG_CONFIG1,273 ADS1298_MASK_CONFIG1_HR | ADS1298_MASK_CONFIG1_DR,274 cfg);275}276 277static const u8 ads1298_pga_settings[] = { 6, 1, 2, 3, 4, 8, 12 };278 279static int ads1298_get_scale(struct ads1298_private *priv,280 int channel, int *val, int *val2)281{282 int ret;283 unsigned int regval;284 u8 gain;285 286 if (priv->reg_vref) {287 ret = regulator_get_voltage(priv->reg_vref);288 if (ret < 0)289 return ret;290 291 *val = ret / MILLI; /* Convert to millivolts */292 } else {293 ret = regmap_read(priv->regmap, ADS1298_REG_CONFIG3, ®val);294 if (ret)295 return ret;296 297 /* Refererence in millivolts */298 *val = regval & ADS1298_MASK_CONFIG3_VREF_4V ? 4000 : 2400;299 }300 301 ret = regmap_read(priv->regmap, ADS1298_REG_CHnSET(channel), ®val);302 if (ret)303 return ret;304 305 gain = ads1298_pga_settings[FIELD_GET(ADS1298_MASK_CH_PGA, regval)];306 *val /= gain; /* Full scale is VREF / gain */307 308 *val2 = ADS1298_BITS_PER_SAMPLE - 1; /* Signed, hence the -1 */309 310 return IIO_VAL_FRACTIONAL_LOG2;311}312 313static int ads1298_read_raw(struct iio_dev *indio_dev,314 struct iio_chan_spec const *chan,315 int *val, int *val2, long mask)316{317 struct ads1298_private *priv = iio_priv(indio_dev);318 int ret;319 320 switch (mask) {321 case IIO_CHAN_INFO_RAW:322 ret = iio_device_claim_direct_mode(indio_dev);323 if (ret)324 return ret;325 326 ret = ads1298_read_one(priv, chan->scan_index);327 328 iio_device_release_direct_mode(indio_dev);329 330 if (ret)331 return ret;332 333 *val = sign_extend32(get_unaligned_be24(priv->rx_buffer + chan->address),334 ADS1298_BITS_PER_SAMPLE - 1);335 return IIO_VAL_INT;336 case IIO_CHAN_INFO_SCALE:337 return ads1298_get_scale(priv, chan->channel, val, val2);338 case IIO_CHAN_INFO_SAMP_FREQ:339 return ads1298_get_samp_freq(priv, val);340 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:341 ret = regmap_read(priv->regmap, ADS1298_REG_CONFIG1, val);342 if (ret)343 return ret;344 345 *val = 16 << (*val & ADS1298_MASK_CONFIG1_DR);346 return IIO_VAL_INT;347 default:348 return -EINVAL;349 }350}351 352static int ads1298_write_raw(struct iio_dev *indio_dev,353 struct iio_chan_spec const *chan, int val,354 int val2, long mask)355{356 struct ads1298_private *priv = iio_priv(indio_dev);357 358 switch (mask) {359 case IIO_CHAN_INFO_SAMP_FREQ:360 return ads1298_set_samp_freq(priv, val);361 default:362 return -EINVAL;363 }364}365 366static int ads1298_reg_write(void *context, unsigned int reg, unsigned int val)367{368 struct ads1298_private *priv = context;369 struct spi_transfer reg_write_xfer = {370 .tx_buf = priv->cmd_buffer,371 .rx_buf = priv->cmd_buffer,372 .len = 3,373 .speed_hz = ADS1298_SPI_BUS_SPEED_SLOW,374 .delay = {375 .value = 2,376 .unit = SPI_DELAY_UNIT_USECS,377 },378 };379 380 priv->cmd_buffer[0] = ADS1298_CMD_WREG | reg;381 priv->cmd_buffer[1] = 0; /* Number of registers to be written - 1 */382 priv->cmd_buffer[2] = val;383 384 return spi_sync_transfer(priv->spi, ®_write_xfer, 1);385}386 387static int ads1298_reg_read(void *context, unsigned int reg, unsigned int *val)388{389 struct ads1298_private *priv = context;390 struct spi_transfer reg_read_xfer = {391 .tx_buf = priv->cmd_buffer,392 .rx_buf = priv->cmd_buffer,393 .len = 3,394 .speed_hz = ADS1298_SPI_BUS_SPEED_SLOW,395 .delay = {396 .value = 2,397 .unit = SPI_DELAY_UNIT_USECS,398 },399 };400 int ret;401 402 priv->cmd_buffer[0] = ADS1298_CMD_RREG | reg;403 priv->cmd_buffer[1] = 0; /* Number of registers to be read - 1 */404 priv->cmd_buffer[2] = 0;405 406 ret = spi_sync_transfer(priv->spi, ®_read_xfer, 1);407 if (ret)408 return ret;409 410 *val = priv->cmd_buffer[2];411 412 return 0;413}414 415static int ads1298_reg_access(struct iio_dev *indio_dev, unsigned int reg,416 unsigned int writeval, unsigned int *readval)417{418 struct ads1298_private *priv = iio_priv(indio_dev);419 420 if (readval)421 return regmap_read(priv->regmap, reg, readval);422 423 return regmap_write(priv->regmap, reg, writeval);424}425 426static void ads1298_rdata_unmark_busy(struct ads1298_private *priv)427{428 /* Notify we're no longer waiting for the SPI transfer to complete */429 guard(spinlock_irqsave)(&priv->irq_busy_lock);430 priv->rdata_xfer_busy = 0;431}432 433static int ads1298_update_scan_mode(struct iio_dev *indio_dev,434 const unsigned long *scan_mask)435{436 struct ads1298_private *priv = iio_priv(indio_dev);437 unsigned int val;438 int ret;439 int i;440 441 /* Make the interrupt routines start with a clean slate */442 ads1298_rdata_unmark_busy(priv);443 444 /* Configure power-down bits to match scan mask */445 for (i = 0; i < indio_dev->num_channels; i++) {446 val = test_bit(i, scan_mask) ? 0 : ADS1298_MASK_CH_PD;447 ret = regmap_update_bits(priv->regmap, ADS1298_REG_CHnSET(i),448 ADS1298_MASK_CH_PD, val);449 if (ret)450 return ret;451 }452 453 return 0;454}455 456static const struct iio_info ads1298_info = {457 .read_raw = &ads1298_read_raw,458 .write_raw = &ads1298_write_raw,459 .update_scan_mode = &ads1298_update_scan_mode,460 .debugfs_reg_access = &ads1298_reg_access,461};462 463static void ads1298_rdata_release_busy_or_restart(struct ads1298_private *priv)464{465 guard(spinlock_irqsave)(&priv->irq_busy_lock);466 467 if (priv->rdata_xfer_busy > 1) {468 /*469 * DRDY interrupt occurred before SPI completion. Start a new470 * SPI transaction now to retrieve the data that wasn't latched471 * into the ADS1298 chip's transfer buffer yet.472 */473 spi_async(priv->spi, &priv->rdata_msg);474 /*475 * If more than one DRDY took place, there was an overrun. Since476 * the sample is already lost, reset the counter to 1 so that477 * we will wait for a DRDY interrupt after this SPI transaction.478 */479 priv->rdata_xfer_busy = 1;480 } else {481 /* No pending data, wait for DRDY */482 priv->rdata_xfer_busy = 0;483 }484}485 486/* Called from SPI completion interrupt handler */487static void ads1298_rdata_complete(void *context)488{489 struct iio_dev *indio_dev = context;490 struct ads1298_private *priv = iio_priv(indio_dev);491 int scan_index;492 u32 *bounce = priv->bounce_buffer;493 494 if (!iio_buffer_enabled(indio_dev)) {495 /*496 * for a single transfer mode we're kept in direct_mode until497 * completion, avoiding a race with buffered IO.498 */499 ads1298_rdata_unmark_busy(priv);500 complete(&priv->completion);501 return;502 }503 504 /* Demux the channel data into our bounce buffer */505 iio_for_each_active_channel(indio_dev, scan_index) {506 const struct iio_chan_spec *scan_chan =507 &indio_dev->channels[scan_index];508 const u8 *data = priv->rx_buffer + scan_chan->address;509 510 *bounce++ = get_unaligned_be24(data);511 }512 513 /* rx_buffer can be overwritten from this point on */514 ads1298_rdata_release_busy_or_restart(priv);515 516 iio_push_to_buffers(indio_dev, priv->bounce_buffer);517}518 519static irqreturn_t ads1298_interrupt(int irq, void *dev_id)520{521 struct iio_dev *indio_dev = dev_id;522 struct ads1298_private *priv = iio_priv(indio_dev);523 unsigned int wasbusy;524 525 guard(spinlock_irqsave)(&priv->irq_busy_lock);526 527 wasbusy = priv->rdata_xfer_busy++;528 /* When no SPI transfer in transit, start one now */529 if (!wasbusy)530 spi_async(priv->spi, &priv->rdata_msg);531 532 return IRQ_HANDLED;533};534 535static int ads1298_buffer_postenable(struct iio_dev *indio_dev)536{537 struct ads1298_private *priv = iio_priv(indio_dev);538 int ret;539 540 /* Disable single-shot mode */541 ret = regmap_update_bits(priv->regmap, ADS1298_REG_CONFIG4,542 ADS1298_MASK_CONFIG4_SINGLE_SHOT, 0);543 if (ret)544 return ret;545 546 return ads1298_write_cmd(priv, ADS1298_CMD_START);547}548 549static int ads1298_buffer_predisable(struct iio_dev *indio_dev)550{551 struct ads1298_private *priv = iio_priv(indio_dev);552 553 return ads1298_write_cmd(priv, ADS1298_CMD_STOP);554}555 556static const struct iio_buffer_setup_ops ads1298_setup_ops = {557 .postenable = &ads1298_buffer_postenable,558 .predisable = &ads1298_buffer_predisable,559};560 561static void ads1298_reg_disable(void *reg)562{563 regulator_disable(reg);564}565 566static const struct regmap_range ads1298_regmap_volatile_range[] = {567 regmap_reg_range(ADS1298_REG_LOFF_STATP, ADS1298_REG_LOFF_STATN),568};569 570static const struct regmap_access_table ads1298_regmap_volatile = {571 .yes_ranges = ads1298_regmap_volatile_range,572 .n_yes_ranges = ARRAY_SIZE(ads1298_regmap_volatile_range),573};574 575static const struct regmap_config ads1298_regmap_config = {576 .reg_bits = 8,577 .val_bits = 8,578 .reg_read = ads1298_reg_read,579 .reg_write = ads1298_reg_write,580 .max_register = ADS1298_REG_WCT2,581 .volatile_table = &ads1298_regmap_volatile,582 .cache_type = REGCACHE_MAPLE,583};584 585static int ads1298_init(struct iio_dev *indio_dev)586{587 struct ads1298_private *priv = iio_priv(indio_dev);588 struct device *dev = &priv->spi->dev;589 const char *suffix;590 unsigned int val;591 int ret;592 593 /* Device initializes into RDATAC mode, which we don't want */594 ret = ads1298_write_cmd(priv, ADS1298_CMD_SDATAC);595 if (ret)596 return ret;597 598 ret = regmap_read(priv->regmap, ADS1298_REG_ID, &val);599 if (ret)600 return ret;601 602 /* Fill in name and channel count based on what the chip told us */603 indio_dev->num_channels = 4 + 2 * (val & ADS1298_MASK_ID_CHANNELS);604 switch (val & ADS1298_MASK_ID_FAMILY) {605 case ADS1298_ID_FAMILY_ADS129X:606 suffix = "";607 break;608 case ADS1298_ID_FAMILY_ADS129XR:609 suffix = "r";610 break;611 default:612 return dev_err_probe(dev, -ENODEV, "Unknown ID: 0x%x\n", val);613 }614 indio_dev->name = devm_kasprintf(dev, GFP_KERNEL, "ads129%u%s",615 indio_dev->num_channels, suffix);616 617 /* Enable internal test signal, double amplitude, double frequency */618 ret = regmap_write(priv->regmap, ADS1298_REG_CONFIG2,619 ADS1298_MASK_CONFIG2_RESERVED |620 ADS1298_MASK_CONFIG2_INT_TEST |621 ADS1298_MASK_CONFIG2_TEST_AMP |622 ADS1298_MASK_CONFIG2_TEST_FREQ_FAST);623 if (ret)624 return ret;625 626 val = ADS1298_MASK_CONFIG3_RESERVED; /* Must write 1 always */627 if (!priv->reg_vref) {628 /* Enable internal reference */629 val |= ADS1298_MASK_CONFIG3_PWR_REFBUF;630 /* Use 4V VREF when power supply is at least 4.4V */631 if (regulator_get_voltage(priv->reg_avdd) >= 4400000)632 val |= ADS1298_MASK_CONFIG3_VREF_4V;633 }634 return regmap_write(priv->regmap, ADS1298_REG_CONFIG3, val);635}636 637static int ads1298_probe(struct spi_device *spi)638{639 struct ads1298_private *priv;640 struct iio_dev *indio_dev;641 struct device *dev = &spi->dev;642 struct gpio_desc *reset_gpio;643 int ret;644 645 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));646 if (!indio_dev)647 return -ENOMEM;648 649 priv = iio_priv(indio_dev);650 651 /* Reset to be asserted before enabling clock and power */652 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);653 if (IS_ERR(reset_gpio))654 return dev_err_probe(dev, PTR_ERR(reset_gpio),655 "Cannot get reset GPIO\n");656 657 /* VREF can be supplied externally, otherwise use internal reference */658 priv->reg_vref = devm_regulator_get_optional(dev, "vref");659 if (IS_ERR(priv->reg_vref)) {660 if (PTR_ERR(priv->reg_vref) != -ENODEV)661 return dev_err_probe(dev, PTR_ERR(priv->reg_vref),662 "Failed to get vref regulator\n");663 664 priv->reg_vref = NULL;665 } else {666 ret = regulator_enable(priv->reg_vref);667 if (ret)668 return ret;669 670 ret = devm_add_action_or_reset(dev, ads1298_reg_disable, priv->reg_vref);671 if (ret)672 return ret;673 }674 675 priv->clk = devm_clk_get_optional_enabled(dev, "clk");676 if (IS_ERR(priv->clk))677 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clk\n");678 679 priv->reg_avdd = devm_regulator_get(dev, "avdd");680 if (IS_ERR(priv->reg_avdd))681 return dev_err_probe(dev, PTR_ERR(priv->reg_avdd),682 "Failed to get avdd regulator\n");683 684 ret = regulator_enable(priv->reg_avdd);685 if (ret)686 return dev_err_probe(dev, ret, "Failed to enable avdd regulator\n");687 688 ret = devm_add_action_or_reset(dev, ads1298_reg_disable, priv->reg_avdd);689 if (ret)690 return ret;691 692 priv->spi = spi;693 init_completion(&priv->completion);694 spin_lock_init(&priv->irq_busy_lock);695 priv->regmap = devm_regmap_init(dev, NULL, priv, &ads1298_regmap_config);696 if (IS_ERR(priv->regmap))697 return PTR_ERR(priv->regmap);698 699 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;700 indio_dev->channels = ads1298_channels;701 indio_dev->info = &ads1298_info;702 703 if (reset_gpio) {704 /*705 * Deassert reset now that clock and power are active.706 * Minimum reset pulsewidth is 2 clock cycles.707 */708 fsleep(ADS1298_CLOCKS_TO_USECS(2));709 gpiod_set_value_cansleep(reset_gpio, 0);710 } else {711 ret = ads1298_write_cmd(priv, ADS1298_CMD_RESET);712 if (ret)713 return dev_err_probe(dev, ret, "RESET failed\n");714 }715 /* Wait 18 clock cycles for reset command to complete */716 fsleep(ADS1298_CLOCKS_TO_USECS(18));717 718 ret = ads1298_init(indio_dev);719 if (ret)720 return dev_err_probe(dev, ret, "Init failed\n");721 722 priv->tx_buffer[0] = ADS1298_CMD_RDATA;723 priv->rdata_xfer.tx_buf = priv->tx_buffer;724 priv->rdata_xfer.rx_buf = priv->rx_buffer;725 priv->rdata_xfer.len = ADS1298_SPI_RDATA_BUFFER_SIZE(indio_dev->num_channels);726 /* Must keep CS low for 4 clocks */727 priv->rdata_xfer.delay.value = 2;728 priv->rdata_xfer.delay.unit = SPI_DELAY_UNIT_USECS;729 spi_message_init_with_transfers(&priv->rdata_msg, &priv->rdata_xfer, 1);730 priv->rdata_msg.complete = &ads1298_rdata_complete;731 priv->rdata_msg.context = indio_dev;732 733 ret = devm_request_irq(dev, spi->irq, &ads1298_interrupt,734 IRQF_TRIGGER_FALLING, indio_dev->name,735 indio_dev);736 if (ret)737 return ret;738 739 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &ads1298_setup_ops);740 if (ret)741 return ret;742 743 return devm_iio_device_register(dev, indio_dev);744}745 746static const struct spi_device_id ads1298_id[] = {747 { "ads1298" },748 { }749};750MODULE_DEVICE_TABLE(spi, ads1298_id);751 752static const struct of_device_id ads1298_of_table[] = {753 { .compatible = "ti,ads1298" },754 { }755};756MODULE_DEVICE_TABLE(of, ads1298_of_table);757 758static struct spi_driver ads1298_driver = {759 .driver = {760 .name = "ads1298",761 .of_match_table = ads1298_of_table,762 },763 .probe = ads1298_probe,764 .id_table = ads1298_id,765};766module_spi_driver(ads1298_driver);767 768MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");769MODULE_DESCRIPTION("TI ADS1298 ADC");770MODULE_LICENSE("GPL");771