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1// SPDX-License-Identifier: GPL-2.02/*3 * Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs4 *5 * Copyright (c) 2020 AVL DiTEST GmbH6 * Tomislav Denis <tomislav.denis@avl.com>7 *8 * Datasheet: https://www.ti.com/lit/ds/symlink/ads131e08.pdf9 */10 11#include <linux/bitfield.h>12#include <linux/clk.h>13#include <linux/delay.h>14#include <linux/module.h>15 16#include <linux/iio/buffer.h>17#include <linux/iio/iio.h>18#include <linux/iio/sysfs.h>19#include <linux/iio/trigger.h>20#include <linux/iio/trigger_consumer.h>21#include <linux/iio/triggered_buffer.h>22 23#include <linux/regulator/consumer.h>24#include <linux/spi/spi.h>25 26#include <linux/unaligned.h>27 28/* Commands */29#define ADS131E08_CMD_RESET 0x0630#define ADS131E08_CMD_START 0x0831#define ADS131E08_CMD_STOP 0x0A32#define ADS131E08_CMD_OFFSETCAL 0x1A33#define ADS131E08_CMD_SDATAC 0x1134#define ADS131E08_CMD_RDATA 0x1235#define ADS131E08_CMD_RREG(r) (BIT(5) | (r & GENMASK(4, 0)))36#define ADS131E08_CMD_WREG(r) (BIT(6) | (r & GENMASK(4, 0)))37 38/* Registers */39#define ADS131E08_ADR_CFG1R 0x0140#define ADS131E08_ADR_CFG3R 0x0341#define ADS131E08_ADR_CH0R 0x0542 43/* Configuration register 1 */44#define ADS131E08_CFG1R_DR_MASK GENMASK(2, 0)45 46/* Configuration register 3 */47#define ADS131E08_CFG3R_PDB_REFBUF_MASK BIT(7)48#define ADS131E08_CFG3R_VREF_4V_MASK BIT(5)49 50/* Channel settings register */51#define ADS131E08_CHR_GAIN_MASK GENMASK(6, 4)52#define ADS131E08_CHR_MUX_MASK GENMASK(2, 0)53#define ADS131E08_CHR_PWD_MASK BIT(7)54 55/* ADC misc */56#define ADS131E08_DEFAULT_DATA_RATE 157#define ADS131E08_DEFAULT_PGA_GAIN 158#define ADS131E08_DEFAULT_MUX 059 60#define ADS131E08_VREF_2V4_mV 240061#define ADS131E08_VREF_4V_mV 400062 63#define ADS131E08_WAIT_RESET_CYCLES 1864#define ADS131E08_WAIT_SDECODE_CYCLES 465#define ADS131E08_WAIT_OFFSETCAL_MS 15366#define ADS131E08_MAX_SETTLING_TIME_MS 667 68#define ADS131E08_NUM_STATUS_BYTES 369#define ADS131E08_NUM_DATA_BYTES_MAX 2470#define ADS131E08_NUM_DATA_BYTES(dr) (((dr) >= 32) ? 2 : 3)71#define ADS131E08_NUM_DATA_BITS(dr) (ADS131E08_NUM_DATA_BYTES(dr) * 8)72#define ADS131E08_NUM_STORAGE_BYTES 473 74enum ads131e08_ids {75 ads131e04,76 ads131e06,77 ads131e08,78};79 80struct ads131e08_info {81 unsigned int max_channels;82 const char *name;83};84 85struct ads131e08_channel_config {86 unsigned int pga_gain;87 unsigned int mux;88};89 90struct ads131e08_state {91 const struct ads131e08_info *info;92 struct spi_device *spi;93 struct iio_trigger *trig;94 struct clk *adc_clk;95 struct regulator *vref_reg;96 struct ads131e08_channel_config *channel_config;97 unsigned int data_rate;98 unsigned int vref_mv;99 unsigned int sdecode_delay_us;100 unsigned int reset_delay_us;101 unsigned int readback_len;102 struct completion completion;103 struct {104 u8 data[ADS131E08_NUM_DATA_BYTES_MAX];105 s64 ts __aligned(8);106 } tmp_buf;107 108 u8 tx_buf[3] __aligned(IIO_DMA_MINALIGN);109 /*110 * Add extra one padding byte to be able to access the last channel111 * value using u32 pointer112 */113 u8 rx_buf[ADS131E08_NUM_STATUS_BYTES +114 ADS131E08_NUM_DATA_BYTES_MAX + 1];115};116 117static const struct ads131e08_info ads131e08_info_tbl[] = {118 [ads131e04] = {119 .max_channels = 4,120 .name = "ads131e04",121 },122 [ads131e06] = {123 .max_channels = 6,124 .name = "ads131e06",125 },126 [ads131e08] = {127 .max_channels = 8,128 .name = "ads131e08",129 },130};131 132struct ads131e08_data_rate_desc {133 unsigned int rate; /* data rate in kSPS */134 u8 reg; /* reg value */135};136 137static const struct ads131e08_data_rate_desc ads131e08_data_rate_tbl[] = {138 { .rate = 64, .reg = 0x00 },139 { .rate = 32, .reg = 0x01 },140 { .rate = 16, .reg = 0x02 },141 { .rate = 8, .reg = 0x03 },142 { .rate = 4, .reg = 0x04 },143 { .rate = 2, .reg = 0x05 },144 { .rate = 1, .reg = 0x06 },145};146 147struct ads131e08_pga_gain_desc {148 unsigned int gain; /* PGA gain value */149 u8 reg; /* field value */150};151 152static const struct ads131e08_pga_gain_desc ads131e08_pga_gain_tbl[] = {153 { .gain = 1, .reg = 0x01 },154 { .gain = 2, .reg = 0x02 },155 { .gain = 4, .reg = 0x04 },156 { .gain = 8, .reg = 0x05 },157 { .gain = 12, .reg = 0x06 },158};159 160static const u8 ads131e08_valid_channel_mux_values[] = { 0, 1, 3, 4 };161 162static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd)163{164 int ret;165 166 ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0);167 if (ret)168 dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd);169 170 return ret;171}172 173static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg)174{175 int ret;176 struct spi_transfer transfer[] = {177 {178 .tx_buf = &st->tx_buf,179 .len = 2,180 .delay = {181 .value = st->sdecode_delay_us,182 .unit = SPI_DELAY_UNIT_USECS,183 },184 }, {185 .rx_buf = &st->rx_buf,186 .len = 1,187 },188 };189 190 st->tx_buf[0] = ADS131E08_CMD_RREG(reg);191 st->tx_buf[1] = 0;192 193 ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));194 if (ret) {195 dev_err(&st->spi->dev, "Read register failed\n");196 return ret;197 }198 199 return st->rx_buf[0];200}201 202static int ads131e08_write_reg(struct ads131e08_state *st, u8 reg, u8 value)203{204 int ret;205 struct spi_transfer transfer[] = {206 {207 .tx_buf = &st->tx_buf,208 .len = 3,209 .delay = {210 .value = st->sdecode_delay_us,211 .unit = SPI_DELAY_UNIT_USECS,212 },213 }214 };215 216 st->tx_buf[0] = ADS131E08_CMD_WREG(reg);217 st->tx_buf[1] = 0;218 st->tx_buf[2] = value;219 220 ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));221 if (ret)222 dev_err(&st->spi->dev, "Write register failed\n");223 224 return ret;225}226 227static int ads131e08_read_data(struct ads131e08_state *st, int rx_len)228{229 int ret;230 struct spi_transfer transfer[] = {231 {232 .tx_buf = &st->tx_buf,233 .len = 1,234 }, {235 .rx_buf = &st->rx_buf,236 .len = rx_len,237 },238 };239 240 st->tx_buf[0] = ADS131E08_CMD_RDATA;241 242 ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));243 if (ret)244 dev_err(&st->spi->dev, "Read data failed\n");245 246 return ret;247}248 249static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate)250{251 int i, reg, ret;252 253 for (i = 0; i < ARRAY_SIZE(ads131e08_data_rate_tbl); i++) {254 if (ads131e08_data_rate_tbl[i].rate == data_rate)255 break;256 }257 258 if (i == ARRAY_SIZE(ads131e08_data_rate_tbl)) {259 dev_err(&st->spi->dev, "invalid data rate value\n");260 return -EINVAL;261 }262 263 reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG1R);264 if (reg < 0)265 return reg;266 267 reg &= ~ADS131E08_CFG1R_DR_MASK;268 reg |= FIELD_PREP(ADS131E08_CFG1R_DR_MASK,269 ads131e08_data_rate_tbl[i].reg);270 271 ret = ads131e08_write_reg(st, ADS131E08_ADR_CFG1R, reg);272 if (ret)273 return ret;274 275 st->data_rate = data_rate;276 st->readback_len = ADS131E08_NUM_STATUS_BYTES +277 ADS131E08_NUM_DATA_BYTES(st->data_rate) *278 st->info->max_channels;279 280 return 0;281}282 283static int ads131e08_pga_gain_to_field_value(struct ads131e08_state *st,284 unsigned int pga_gain)285{286 int i;287 288 for (i = 0; i < ARRAY_SIZE(ads131e08_pga_gain_tbl); i++) {289 if (ads131e08_pga_gain_tbl[i].gain == pga_gain)290 break;291 }292 293 if (i == ARRAY_SIZE(ads131e08_pga_gain_tbl)) {294 dev_err(&st->spi->dev, "invalid PGA gain value\n");295 return -EINVAL;296 }297 298 return ads131e08_pga_gain_tbl[i].reg;299}300 301static int ads131e08_set_pga_gain(struct ads131e08_state *st,302 unsigned int channel, unsigned int pga_gain)303{304 int field_value, reg;305 306 field_value = ads131e08_pga_gain_to_field_value(st, pga_gain);307 if (field_value < 0)308 return field_value;309 310 reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);311 if (reg < 0)312 return reg;313 314 reg &= ~ADS131E08_CHR_GAIN_MASK;315 reg |= FIELD_PREP(ADS131E08_CHR_GAIN_MASK, field_value);316 317 return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);318}319 320static int ads131e08_validate_channel_mux(struct ads131e08_state *st,321 unsigned int mux)322{323 int i;324 325 for (i = 0; i < ARRAY_SIZE(ads131e08_valid_channel_mux_values); i++) {326 if (ads131e08_valid_channel_mux_values[i] == mux)327 break;328 }329 330 if (i == ARRAY_SIZE(ads131e08_valid_channel_mux_values)) {331 dev_err(&st->spi->dev, "invalid channel mux value\n");332 return -EINVAL;333 }334 335 return 0;336}337 338static int ads131e08_set_channel_mux(struct ads131e08_state *st,339 unsigned int channel, unsigned int mux)340{341 int reg;342 343 reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);344 if (reg < 0)345 return reg;346 347 reg &= ~ADS131E08_CHR_MUX_MASK;348 reg |= FIELD_PREP(ADS131E08_CHR_MUX_MASK, mux);349 350 return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);351}352 353static int ads131e08_power_down_channel(struct ads131e08_state *st,354 unsigned int channel, bool value)355{356 int reg;357 358 reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);359 if (reg < 0)360 return reg;361 362 reg &= ~ADS131E08_CHR_PWD_MASK;363 reg |= FIELD_PREP(ADS131E08_CHR_PWD_MASK, value);364 365 return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);366}367 368static int ads131e08_config_reference_voltage(struct ads131e08_state *st)369{370 int reg;371 372 reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG3R);373 if (reg < 0)374 return reg;375 376 reg &= ~ADS131E08_CFG3R_PDB_REFBUF_MASK;377 if (!st->vref_reg) {378 reg |= FIELD_PREP(ADS131E08_CFG3R_PDB_REFBUF_MASK, 1);379 reg &= ~ADS131E08_CFG3R_VREF_4V_MASK;380 reg |= FIELD_PREP(ADS131E08_CFG3R_VREF_4V_MASK,381 st->vref_mv == ADS131E08_VREF_4V_mV);382 }383 384 return ads131e08_write_reg(st, ADS131E08_ADR_CFG3R, reg);385}386 387static int ads131e08_initial_config(struct iio_dev *indio_dev)388{389 const struct iio_chan_spec *channel = indio_dev->channels;390 struct ads131e08_state *st = iio_priv(indio_dev);391 unsigned long active_channels = 0;392 int ret, i;393 394 ret = ads131e08_exec_cmd(st, ADS131E08_CMD_RESET);395 if (ret)396 return ret;397 398 udelay(st->reset_delay_us);399 400 /* Disable read data in continuous mode (enabled by default) */401 ret = ads131e08_exec_cmd(st, ADS131E08_CMD_SDATAC);402 if (ret)403 return ret;404 405 ret = ads131e08_set_data_rate(st, ADS131E08_DEFAULT_DATA_RATE);406 if (ret)407 return ret;408 409 ret = ads131e08_config_reference_voltage(st);410 if (ret)411 return ret;412 413 for (i = 0; i < indio_dev->num_channels; i++) {414 ret = ads131e08_set_pga_gain(st, channel->channel,415 st->channel_config[i].pga_gain);416 if (ret)417 return ret;418 419 ret = ads131e08_set_channel_mux(st, channel->channel,420 st->channel_config[i].mux);421 if (ret)422 return ret;423 424 active_channels |= BIT(channel->channel);425 channel++;426 }427 428 /* Power down unused channels */429 for_each_clear_bit(i, &active_channels, st->info->max_channels) {430 ret = ads131e08_power_down_channel(st, i, true);431 if (ret)432 return ret;433 }434 435 /* Request channel offset calibration */436 ret = ads131e08_exec_cmd(st, ADS131E08_CMD_OFFSETCAL);437 if (ret)438 return ret;439 440 /*441 * Channel offset calibration is triggered with the first START442 * command. Since calibration takes more time than settling operation,443 * this causes timeout error when command START is sent first444 * time (e.g. first call of the ads131e08_read_direct method).445 * To avoid this problem offset calibration is triggered here.446 */447 ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);448 if (ret)449 return ret;450 451 msleep(ADS131E08_WAIT_OFFSETCAL_MS);452 453 return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);454}455 456static int ads131e08_pool_data(struct ads131e08_state *st)457{458 unsigned long timeout;459 int ret;460 461 reinit_completion(&st->completion);462 463 ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);464 if (ret)465 return ret;466 467 timeout = msecs_to_jiffies(ADS131E08_MAX_SETTLING_TIME_MS);468 ret = wait_for_completion_timeout(&st->completion, timeout);469 if (!ret)470 return -ETIMEDOUT;471 472 ret = ads131e08_read_data(st, st->readback_len);473 if (ret)474 return ret;475 476 return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);477}478 479static int ads131e08_read_direct(struct iio_dev *indio_dev,480 struct iio_chan_spec const *channel, int *value)481{482 struct ads131e08_state *st = iio_priv(indio_dev);483 u8 num_bits, *src;484 int ret;485 486 ret = ads131e08_pool_data(st);487 if (ret)488 return ret;489 490 src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES +491 channel->channel * ADS131E08_NUM_DATA_BYTES(st->data_rate);492 493 num_bits = ADS131E08_NUM_DATA_BITS(st->data_rate);494 *value = sign_extend32(get_unaligned_be32(src) >> (32 - num_bits), num_bits - 1);495 496 return 0;497}498 499static int ads131e08_read_raw(struct iio_dev *indio_dev,500 struct iio_chan_spec const *channel, int *value,501 int *value2, long mask)502{503 struct ads131e08_state *st = iio_priv(indio_dev);504 int ret;505 506 switch (mask) {507 case IIO_CHAN_INFO_RAW:508 ret = iio_device_claim_direct_mode(indio_dev);509 if (ret)510 return ret;511 512 ret = ads131e08_read_direct(indio_dev, channel, value);513 iio_device_release_direct_mode(indio_dev);514 if (ret)515 return ret;516 517 return IIO_VAL_INT;518 519 case IIO_CHAN_INFO_SCALE:520 if (st->vref_reg) {521 ret = regulator_get_voltage(st->vref_reg);522 if (ret < 0)523 return ret;524 525 *value = ret / 1000;526 } else {527 *value = st->vref_mv;528 }529 530 *value /= st->channel_config[channel->address].pga_gain;531 *value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1;532 533 return IIO_VAL_FRACTIONAL_LOG2;534 535 case IIO_CHAN_INFO_SAMP_FREQ:536 *value = st->data_rate;537 538 return IIO_VAL_INT;539 540 default:541 return -EINVAL;542 }543}544 545static int ads131e08_write_raw(struct iio_dev *indio_dev,546 struct iio_chan_spec const *channel, int value,547 int value2, long mask)548{549 struct ads131e08_state *st = iio_priv(indio_dev);550 int ret;551 552 switch (mask) {553 case IIO_CHAN_INFO_SAMP_FREQ:554 ret = iio_device_claim_direct_mode(indio_dev);555 if (ret)556 return ret;557 558 ret = ads131e08_set_data_rate(st, value);559 iio_device_release_direct_mode(indio_dev);560 return ret;561 562 default:563 return -EINVAL;564 }565}566 567static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1 2 4 8 16 32 64");568 569static struct attribute *ads131e08_attributes[] = {570 &iio_const_attr_sampling_frequency_available.dev_attr.attr,571 NULL572};573 574static const struct attribute_group ads131e08_attribute_group = {575 .attrs = ads131e08_attributes,576};577 578static int ads131e08_debugfs_reg_access(struct iio_dev *indio_dev,579 unsigned int reg, unsigned int writeval, unsigned int *readval)580{581 struct ads131e08_state *st = iio_priv(indio_dev);582 583 if (readval) {584 int ret = ads131e08_read_reg(st, reg);585 *readval = ret;586 return ret;587 }588 589 return ads131e08_write_reg(st, reg, writeval);590}591 592static const struct iio_info ads131e08_iio_info = {593 .read_raw = ads131e08_read_raw,594 .write_raw = ads131e08_write_raw,595 .attrs = &ads131e08_attribute_group,596 .debugfs_reg_access = &ads131e08_debugfs_reg_access,597};598 599static int ads131e08_set_trigger_state(struct iio_trigger *trig, bool state)600{601 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);602 struct ads131e08_state *st = iio_priv(indio_dev);603 u8 cmd = state ? ADS131E08_CMD_START : ADS131E08_CMD_STOP;604 605 return ads131e08_exec_cmd(st, cmd);606}607 608static const struct iio_trigger_ops ads131e08_trigger_ops = {609 .set_trigger_state = &ads131e08_set_trigger_state,610 .validate_device = &iio_trigger_validate_own_device,611};612 613static irqreturn_t ads131e08_trigger_handler(int irq, void *private)614{615 struct iio_poll_func *pf = private;616 struct iio_dev *indio_dev = pf->indio_dev;617 struct ads131e08_state *st = iio_priv(indio_dev);618 unsigned int chn, i = 0;619 u8 *src, *dest;620 int ret;621 622 /*623 * The number of data bits per channel depends on the data rate.624 * For 32 and 64 ksps data rates, number of data bits per channel625 * is 16. This case is not compliant with used (fixed) scan element626 * type (be:s24/32>>8). So we use a little tweak to pack properly627 * 16 bits of data into the buffer.628 */629 unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate);630 u8 tweek_offset = num_bytes == 2 ? 1 : 0;631 632 if (iio_trigger_using_own(indio_dev))633 ret = ads131e08_read_data(st, st->readback_len);634 else635 ret = ads131e08_pool_data(st);636 637 if (ret)638 goto out;639 640 iio_for_each_active_channel(indio_dev, chn) {641 src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES + chn * num_bytes;642 dest = st->tmp_buf.data + i * ADS131E08_NUM_STORAGE_BYTES;643 644 /*645 * Tweek offset is 0:646 * +---+---+---+---+647 * |D0 |D1 |D2 | X | (3 data bytes)648 * +---+---+---+---+649 * a+0 a+1 a+2 a+3650 *651 * Tweek offset is 1:652 * +---+---+---+---+653 * |P0 |D0 |D1 | X | (one padding byte and 2 data bytes)654 * +---+---+---+---+655 * a+0 a+1 a+2 a+3656 */657 memcpy(dest + tweek_offset, src, num_bytes);658 659 /*660 * Data conversion from 16 bits of data to 24 bits of data661 * is done by sign extension (properly filling padding byte).662 */663 if (tweek_offset)664 *dest = *src & BIT(7) ? 0xff : 0x00;665 666 i++;667 }668 669 iio_push_to_buffers_with_timestamp(indio_dev, st->tmp_buf.data,670 iio_get_time_ns(indio_dev));671 672out:673 iio_trigger_notify_done(indio_dev->trig);674 675 return IRQ_HANDLED;676}677 678static irqreturn_t ads131e08_interrupt(int irq, void *private)679{680 struct iio_dev *indio_dev = private;681 struct ads131e08_state *st = iio_priv(indio_dev);682 683 if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev))684 iio_trigger_poll(st->trig);685 else686 complete(&st->completion);687 688 return IRQ_HANDLED;689}690 691static int ads131e08_alloc_channels(struct iio_dev *indio_dev)692{693 struct ads131e08_state *st = iio_priv(indio_dev);694 struct ads131e08_channel_config *channel_config;695 struct device *dev = &st->spi->dev;696 struct iio_chan_spec *channels;697 unsigned int channel, tmp;698 int num_channels, i, ret;699 700 ret = device_property_read_u32(dev, "ti,vref-internal", &tmp);701 if (ret)702 tmp = 0;703 704 switch (tmp) {705 case 0:706 st->vref_mv = ADS131E08_VREF_2V4_mV;707 break;708 case 1:709 st->vref_mv = ADS131E08_VREF_4V_mV;710 break;711 default:712 dev_err(&st->spi->dev, "invalid internal voltage reference\n");713 return -EINVAL;714 }715 716 num_channels = device_get_child_node_count(dev);717 if (num_channels == 0) {718 dev_err(&st->spi->dev, "no channel children\n");719 return -ENODEV;720 }721 722 if (num_channels > st->info->max_channels) {723 dev_err(&st->spi->dev, "num of channel children out of range\n");724 return -EINVAL;725 }726 727 channels = devm_kcalloc(&st->spi->dev, num_channels,728 sizeof(*channels), GFP_KERNEL);729 if (!channels)730 return -ENOMEM;731 732 channel_config = devm_kcalloc(&st->spi->dev, num_channels,733 sizeof(*channel_config), GFP_KERNEL);734 if (!channel_config)735 return -ENOMEM;736 737 i = 0;738 device_for_each_child_node_scoped(dev, node) {739 ret = fwnode_property_read_u32(node, "reg", &channel);740 if (ret)741 return ret;742 743 ret = fwnode_property_read_u32(node, "ti,gain", &tmp);744 if (ret) {745 channel_config[i].pga_gain = ADS131E08_DEFAULT_PGA_GAIN;746 } else {747 ret = ads131e08_pga_gain_to_field_value(st, tmp);748 if (ret < 0)749 return ret;750 751 channel_config[i].pga_gain = tmp;752 }753 754 ret = fwnode_property_read_u32(node, "ti,mux", &tmp);755 if (ret) {756 channel_config[i].mux = ADS131E08_DEFAULT_MUX;757 } else {758 ret = ads131e08_validate_channel_mux(st, tmp);759 if (ret)760 return ret;761 762 channel_config[i].mux = tmp;763 }764 765 channels[i].type = IIO_VOLTAGE;766 channels[i].indexed = 1;767 channels[i].channel = channel;768 channels[i].address = i;769 channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |770 BIT(IIO_CHAN_INFO_SCALE);771 channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ);772 channels[i].scan_index = channel;773 channels[i].scan_type.sign = 's';774 channels[i].scan_type.realbits = 24;775 channels[i].scan_type.storagebits = 32;776 channels[i].scan_type.shift = 8;777 channels[i].scan_type.endianness = IIO_BE;778 i++;779 }780 781 indio_dev->channels = channels;782 indio_dev->num_channels = num_channels;783 st->channel_config = channel_config;784 785 return 0;786 787}788 789static void ads131e08_regulator_disable(void *data)790{791 struct ads131e08_state *st = data;792 793 regulator_disable(st->vref_reg);794}795 796static int ads131e08_probe(struct spi_device *spi)797{798 const struct ads131e08_info *info;799 struct ads131e08_state *st;800 struct iio_dev *indio_dev;801 unsigned long adc_clk_hz;802 unsigned long adc_clk_ns;803 int ret;804 805 info = spi_get_device_match_data(spi);806 if (!info) {807 dev_err(&spi->dev, "failed to get match data\n");808 return -ENODEV;809 }810 811 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));812 if (!indio_dev) {813 dev_err(&spi->dev, "failed to allocate IIO device\n");814 return -ENOMEM;815 }816 817 st = iio_priv(indio_dev);818 st->info = info;819 st->spi = spi;820 821 ret = ads131e08_alloc_channels(indio_dev);822 if (ret)823 return ret;824 825 indio_dev->name = st->info->name;826 indio_dev->info = &ads131e08_iio_info;827 indio_dev->modes = INDIO_DIRECT_MODE;828 829 init_completion(&st->completion);830 831 if (spi->irq) {832 ret = devm_request_irq(&spi->dev, spi->irq,833 ads131e08_interrupt,834 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,835 spi->dev.driver->name, indio_dev);836 if (ret)837 return dev_err_probe(&spi->dev, ret,838 "request irq failed\n");839 } else {840 dev_err(&spi->dev, "data ready IRQ missing\n");841 return -ENODEV;842 }843 844 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",845 indio_dev->name, iio_device_id(indio_dev));846 if (!st->trig) {847 dev_err(&spi->dev, "failed to allocate IIO trigger\n");848 return -ENOMEM;849 }850 851 st->trig->ops = &ads131e08_trigger_ops;852 st->trig->dev.parent = &spi->dev;853 iio_trigger_set_drvdata(st->trig, indio_dev);854 ret = devm_iio_trigger_register(&spi->dev, st->trig);855 if (ret) {856 dev_err(&spi->dev, "failed to register IIO trigger\n");857 return -ENOMEM;858 }859 860 indio_dev->trig = iio_trigger_get(st->trig);861 862 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,863 NULL, &ads131e08_trigger_handler, NULL);864 if (ret) {865 dev_err(&spi->dev, "failed to setup IIO buffer\n");866 return ret;867 }868 869 st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");870 if (!IS_ERR(st->vref_reg)) {871 ret = regulator_enable(st->vref_reg);872 if (ret) {873 dev_err(&spi->dev,874 "failed to enable external vref supply\n");875 return ret;876 }877 878 ret = devm_add_action_or_reset(&spi->dev, ads131e08_regulator_disable, st);879 if (ret)880 return ret;881 } else {882 if (PTR_ERR(st->vref_reg) != -ENODEV)883 return PTR_ERR(st->vref_reg);884 885 st->vref_reg = NULL;886 }887 888 st->adc_clk = devm_clk_get_enabled(&spi->dev, "adc-clk");889 if (IS_ERR(st->adc_clk))890 return dev_err_probe(&spi->dev, PTR_ERR(st->adc_clk),891 "failed to get the ADC clock\n");892 893 adc_clk_hz = clk_get_rate(st->adc_clk);894 if (!adc_clk_hz) {895 dev_err(&spi->dev, "failed to get the ADC clock rate\n");896 return -EINVAL;897 }898 899 adc_clk_ns = NSEC_PER_SEC / adc_clk_hz;900 st->sdecode_delay_us = DIV_ROUND_UP(901 ADS131E08_WAIT_SDECODE_CYCLES * adc_clk_ns, NSEC_PER_USEC);902 st->reset_delay_us = DIV_ROUND_UP(903 ADS131E08_WAIT_RESET_CYCLES * adc_clk_ns, NSEC_PER_USEC);904 905 ret = ads131e08_initial_config(indio_dev);906 if (ret) {907 dev_err(&spi->dev, "initial configuration failed\n");908 return ret;909 }910 911 return devm_iio_device_register(&spi->dev, indio_dev);912}913 914static const struct of_device_id ads131e08_of_match[] = {915 { .compatible = "ti,ads131e04",916 .data = &ads131e08_info_tbl[ads131e04], },917 { .compatible = "ti,ads131e06",918 .data = &ads131e08_info_tbl[ads131e06], },919 { .compatible = "ti,ads131e08",920 .data = &ads131e08_info_tbl[ads131e08], },921 { }922};923MODULE_DEVICE_TABLE(of, ads131e08_of_match);924 925static const struct spi_device_id ads131e08_ids[] = {926 { "ads131e04", (kernel_ulong_t)&ads131e08_info_tbl[ads131e04] },927 { "ads131e06", (kernel_ulong_t)&ads131e08_info_tbl[ads131e06] },928 { "ads131e08", (kernel_ulong_t)&ads131e08_info_tbl[ads131e08] },929 { }930};931MODULE_DEVICE_TABLE(spi, ads131e08_ids);932 933static struct spi_driver ads131e08_driver = {934 .driver = {935 .name = "ads131e08",936 .of_match_table = ads131e08_of_match,937 },938 .probe = ads131e08_probe,939 .id_table = ads131e08_ids,940};941module_spi_driver(ads131e08_driver);942 943MODULE_AUTHOR("Tomislav Denis <tomislav.denis@avl.com>");944MODULE_DESCRIPTION("Driver for ADS131E0x ADC family");945MODULE_LICENSE("GPL v2");946