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1// SPDX-License-Identifier: GPL-2.02/*3 * Texas Instruments ADS7950 SPI ADC driver4 *5 * Copyright 2016 David Lechner <david@lechnology.com>6 *7 * Based on iio/ad7923.c:8 * Copyright 2011 Analog Devices Inc9 * Copyright 2012 CS Systemes d'Information10 *11 * And also on hwmon/ads79xx.c12 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/13 * Nishanth Menon14 */15 16#include <linux/acpi.h>17#include <linux/bitops.h>18#include <linux/device.h>19#include <linux/err.h>20#include <linux/gpio/driver.h>21#include <linux/interrupt.h>22#include <linux/kernel.h>23#include <linux/module.h>24#include <linux/regulator/consumer.h>25#include <linux/slab.h>26#include <linux/spi/spi.h>27 28#include <linux/iio/buffer.h>29#include <linux/iio/iio.h>30#include <linux/iio/sysfs.h>31#include <linux/iio/trigger_consumer.h>32#include <linux/iio/triggered_buffer.h>33 34/*35 * In case of ACPI, we use the 5000 mV as default for the reference pin.36 * Device tree users encode that via the vref-supply regulator.37 */38#define TI_ADS7950_VA_MV_ACPI_DEFAULT 500039 40#define TI_ADS7950_CR_GPIO BIT(14)41#define TI_ADS7950_CR_MANUAL BIT(12)42#define TI_ADS7950_CR_WRITE BIT(11)43#define TI_ADS7950_CR_CHAN(ch) ((ch) << 7)44#define TI_ADS7950_CR_RANGE_5V BIT(6)45#define TI_ADS7950_CR_GPIO_DATA BIT(4)46 47#define TI_ADS7950_MAX_CHAN 1648#define TI_ADS7950_NUM_GPIOS 449 50#define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))51 52/* val = value, dec = left shift, bits = number of bits of the mask */53#define TI_ADS7950_EXTRACT(val, dec, bits) \54 (((val) >> (dec)) & ((1 << (bits)) - 1))55 56#define TI_ADS7950_MAN_CMD(cmd) (TI_ADS7950_CR_MANUAL | (cmd))57#define TI_ADS7950_GPIO_CMD(cmd) (TI_ADS7950_CR_GPIO | (cmd))58 59/* Manual mode configuration */60#define TI_ADS7950_MAN_CMD_SETTINGS(st) \61 (TI_ADS7950_MAN_CMD(TI_ADS7950_CR_WRITE | st->cmd_settings_bitmask))62/* GPIO mode configuration */63#define TI_ADS7950_GPIO_CMD_SETTINGS(st) \64 (TI_ADS7950_GPIO_CMD(st->gpio_cmd_settings_bitmask))65 66struct ti_ads7950_state {67 struct spi_device *spi;68 struct spi_transfer ring_xfer;69 struct spi_transfer scan_single_xfer[3];70 struct spi_message ring_msg;71 struct spi_message scan_single_msg;72 73 /* Lock to protect the spi xfer buffers */74 struct mutex slock;75 struct gpio_chip chip;76 77 struct regulator *reg;78 unsigned int vref_mv;79 80 /*81 * Bitmask of lower 7 bits used for configuration82 * These bits only can be written when TI_ADS7950_CR_WRITE83 * is set, otherwise it retains its original state.84 * [0-3] GPIO signal85 * [4] Set following frame to return GPIO signal values86 * [5] Powers down device87 * [6] Sets Vref range1(2.5v) or range2(5v)88 *89 * Bits present on Manual/Auto1/Auto2 commands90 */91 unsigned int cmd_settings_bitmask;92 93 /*94 * Bitmask of GPIO command95 * [0-3] GPIO direction96 * [4-6] Different GPIO alarm mode configurations97 * [7] GPIO 2 as device range input98 * [8] GPIO 3 as device power down input99 * [9] Reset all registers100 * [10-11] N/A101 */102 unsigned int gpio_cmd_settings_bitmask;103 104 /*105 * DMA (thus cache coherency maintenance) may require the106 * transfer buffers to live in their own cache lines.107 */108 u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]109 __aligned(IIO_DMA_MINALIGN);110 u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];111 u16 single_tx;112 u16 single_rx;113 114};115 116struct ti_ads7950_chip_info {117 const struct iio_chan_spec *channels;118 unsigned int num_channels;119};120 121enum ti_ads7950_id {122 TI_ADS7950,123 TI_ADS7951,124 TI_ADS7952,125 TI_ADS7953,126 TI_ADS7954,127 TI_ADS7955,128 TI_ADS7956,129 TI_ADS7957,130 TI_ADS7958,131 TI_ADS7959,132 TI_ADS7960,133 TI_ADS7961,134};135 136#define TI_ADS7950_V_CHAN(index, bits) \137{ \138 .type = IIO_VOLTAGE, \139 .indexed = 1, \140 .channel = index, \141 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \142 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \143 .address = index, \144 .datasheet_name = "CH##index", \145 .scan_index = index, \146 .scan_type = { \147 .sign = 'u', \148 .realbits = bits, \149 .storagebits = 16, \150 .shift = 12 - (bits), \151 .endianness = IIO_CPU, \152 }, \153}154 155#define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \156const struct iio_chan_spec name ## _channels[] = { \157 TI_ADS7950_V_CHAN(0, bits), \158 TI_ADS7950_V_CHAN(1, bits), \159 TI_ADS7950_V_CHAN(2, bits), \160 TI_ADS7950_V_CHAN(3, bits), \161 IIO_CHAN_SOFT_TIMESTAMP(4), \162}163 164#define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \165const struct iio_chan_spec name ## _channels[] = { \166 TI_ADS7950_V_CHAN(0, bits), \167 TI_ADS7950_V_CHAN(1, bits), \168 TI_ADS7950_V_CHAN(2, bits), \169 TI_ADS7950_V_CHAN(3, bits), \170 TI_ADS7950_V_CHAN(4, bits), \171 TI_ADS7950_V_CHAN(5, bits), \172 TI_ADS7950_V_CHAN(6, bits), \173 TI_ADS7950_V_CHAN(7, bits), \174 IIO_CHAN_SOFT_TIMESTAMP(8), \175}176 177#define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \178const struct iio_chan_spec name ## _channels[] = { \179 TI_ADS7950_V_CHAN(0, bits), \180 TI_ADS7950_V_CHAN(1, bits), \181 TI_ADS7950_V_CHAN(2, bits), \182 TI_ADS7950_V_CHAN(3, bits), \183 TI_ADS7950_V_CHAN(4, bits), \184 TI_ADS7950_V_CHAN(5, bits), \185 TI_ADS7950_V_CHAN(6, bits), \186 TI_ADS7950_V_CHAN(7, bits), \187 TI_ADS7950_V_CHAN(8, bits), \188 TI_ADS7950_V_CHAN(9, bits), \189 TI_ADS7950_V_CHAN(10, bits), \190 TI_ADS7950_V_CHAN(11, bits), \191 IIO_CHAN_SOFT_TIMESTAMP(12), \192}193 194#define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \195const struct iio_chan_spec name ## _channels[] = { \196 TI_ADS7950_V_CHAN(0, bits), \197 TI_ADS7950_V_CHAN(1, bits), \198 TI_ADS7950_V_CHAN(2, bits), \199 TI_ADS7950_V_CHAN(3, bits), \200 TI_ADS7950_V_CHAN(4, bits), \201 TI_ADS7950_V_CHAN(5, bits), \202 TI_ADS7950_V_CHAN(6, bits), \203 TI_ADS7950_V_CHAN(7, bits), \204 TI_ADS7950_V_CHAN(8, bits), \205 TI_ADS7950_V_CHAN(9, bits), \206 TI_ADS7950_V_CHAN(10, bits), \207 TI_ADS7950_V_CHAN(11, bits), \208 TI_ADS7950_V_CHAN(12, bits), \209 TI_ADS7950_V_CHAN(13, bits), \210 TI_ADS7950_V_CHAN(14, bits), \211 TI_ADS7950_V_CHAN(15, bits), \212 IIO_CHAN_SOFT_TIMESTAMP(16), \213}214 215static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);216static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);217static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);218static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);219static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);220static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);221static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);222static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);223static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);224static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);225static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);226static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);227 228static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {229 [TI_ADS7950] = {230 .channels = ti_ads7950_channels,231 .num_channels = ARRAY_SIZE(ti_ads7950_channels),232 },233 [TI_ADS7951] = {234 .channels = ti_ads7951_channels,235 .num_channels = ARRAY_SIZE(ti_ads7951_channels),236 },237 [TI_ADS7952] = {238 .channels = ti_ads7952_channels,239 .num_channels = ARRAY_SIZE(ti_ads7952_channels),240 },241 [TI_ADS7953] = {242 .channels = ti_ads7953_channels,243 .num_channels = ARRAY_SIZE(ti_ads7953_channels),244 },245 [TI_ADS7954] = {246 .channels = ti_ads7954_channels,247 .num_channels = ARRAY_SIZE(ti_ads7954_channels),248 },249 [TI_ADS7955] = {250 .channels = ti_ads7955_channels,251 .num_channels = ARRAY_SIZE(ti_ads7955_channels),252 },253 [TI_ADS7956] = {254 .channels = ti_ads7956_channels,255 .num_channels = ARRAY_SIZE(ti_ads7956_channels),256 },257 [TI_ADS7957] = {258 .channels = ti_ads7957_channels,259 .num_channels = ARRAY_SIZE(ti_ads7957_channels),260 },261 [TI_ADS7958] = {262 .channels = ti_ads7958_channels,263 .num_channels = ARRAY_SIZE(ti_ads7958_channels),264 },265 [TI_ADS7959] = {266 .channels = ti_ads7959_channels,267 .num_channels = ARRAY_SIZE(ti_ads7959_channels),268 },269 [TI_ADS7960] = {270 .channels = ti_ads7960_channels,271 .num_channels = ARRAY_SIZE(ti_ads7960_channels),272 },273 [TI_ADS7961] = {274 .channels = ti_ads7961_channels,275 .num_channels = ARRAY_SIZE(ti_ads7961_channels),276 },277};278 279/*280 * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new281 * scan mask282 */283static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,284 const unsigned long *active_scan_mask)285{286 struct ti_ads7950_state *st = iio_priv(indio_dev);287 int i, cmd, len;288 289 len = 0;290 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {291 cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(i));292 st->tx_buf[len++] = cmd;293 }294 295 /* Data for the 1st channel is not returned until the 3rd transfer */296 st->tx_buf[len++] = 0;297 st->tx_buf[len++] = 0;298 299 st->ring_xfer.len = len * 2;300 301 return 0;302}303 304static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)305{306 struct iio_poll_func *pf = p;307 struct iio_dev *indio_dev = pf->indio_dev;308 struct ti_ads7950_state *st = iio_priv(indio_dev);309 int ret;310 311 mutex_lock(&st->slock);312 ret = spi_sync(st->spi, &st->ring_msg);313 if (ret < 0)314 goto out;315 316 iio_push_to_buffers_with_timestamp(indio_dev, &st->rx_buf[2],317 iio_get_time_ns(indio_dev));318 319out:320 mutex_unlock(&st->slock);321 iio_trigger_notify_done(indio_dev->trig);322 323 return IRQ_HANDLED;324}325 326static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)327{328 struct ti_ads7950_state *st = iio_priv(indio_dev);329 int ret, cmd;330 331 mutex_lock(&st->slock);332 cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(ch));333 st->single_tx = cmd;334 335 ret = spi_sync(st->spi, &st->scan_single_msg);336 if (ret)337 goto out;338 339 ret = st->single_rx;340 341out:342 mutex_unlock(&st->slock);343 344 return ret;345}346 347static int ti_ads7950_get_range(struct ti_ads7950_state *st)348{349 int vref;350 351 if (st->vref_mv) {352 vref = st->vref_mv;353 } else {354 vref = regulator_get_voltage(st->reg);355 if (vref < 0)356 return vref;357 358 vref /= 1000;359 }360 361 if (st->cmd_settings_bitmask & TI_ADS7950_CR_RANGE_5V)362 vref *= 2;363 364 return vref;365}366 367static int ti_ads7950_read_raw(struct iio_dev *indio_dev,368 struct iio_chan_spec const *chan,369 int *val, int *val2, long m)370{371 struct ti_ads7950_state *st = iio_priv(indio_dev);372 int ret;373 374 switch (m) {375 case IIO_CHAN_INFO_RAW:376 ret = ti_ads7950_scan_direct(indio_dev, chan->address);377 if (ret < 0)378 return ret;379 380 if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))381 return -EIO;382 383 *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,384 chan->scan_type.realbits);385 386 return IIO_VAL_INT;387 case IIO_CHAN_INFO_SCALE:388 ret = ti_ads7950_get_range(st);389 if (ret < 0)390 return ret;391 392 *val = ret;393 *val2 = (1 << chan->scan_type.realbits) - 1;394 395 return IIO_VAL_FRACTIONAL;396 }397 398 return -EINVAL;399}400 401static const struct iio_info ti_ads7950_info = {402 .read_raw = &ti_ads7950_read_raw,403 .update_scan_mode = ti_ads7950_update_scan_mode,404};405 406static void ti_ads7950_set(struct gpio_chip *chip, unsigned int offset,407 int value)408{409 struct ti_ads7950_state *st = gpiochip_get_data(chip);410 411 mutex_lock(&st->slock);412 413 if (value)414 st->cmd_settings_bitmask |= BIT(offset);415 else416 st->cmd_settings_bitmask &= ~BIT(offset);417 418 st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);419 spi_sync(st->spi, &st->scan_single_msg);420 421 mutex_unlock(&st->slock);422}423 424static int ti_ads7950_get(struct gpio_chip *chip, unsigned int offset)425{426 struct ti_ads7950_state *st = gpiochip_get_data(chip);427 int ret;428 429 mutex_lock(&st->slock);430 431 /* If set as output, return the output */432 if (st->gpio_cmd_settings_bitmask & BIT(offset)) {433 ret = st->cmd_settings_bitmask & BIT(offset);434 goto out;435 }436 437 /* GPIO data bit sets SDO bits 12-15 to GPIO input */438 st->cmd_settings_bitmask |= TI_ADS7950_CR_GPIO_DATA;439 st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);440 ret = spi_sync(st->spi, &st->scan_single_msg);441 if (ret)442 goto out;443 444 ret = ((st->single_rx >> 12) & BIT(offset)) ? 1 : 0;445 446 /* Revert back to original settings */447 st->cmd_settings_bitmask &= ~TI_ADS7950_CR_GPIO_DATA;448 st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);449 ret = spi_sync(st->spi, &st->scan_single_msg);450 if (ret)451 goto out;452 453out:454 mutex_unlock(&st->slock);455 456 return ret;457}458 459static int ti_ads7950_get_direction(struct gpio_chip *chip,460 unsigned int offset)461{462 struct ti_ads7950_state *st = gpiochip_get_data(chip);463 464 /* Bitmask is inverted from GPIO framework 0=input/1=output */465 return !(st->gpio_cmd_settings_bitmask & BIT(offset));466}467 468static int _ti_ads7950_set_direction(struct gpio_chip *chip, int offset,469 int input)470{471 struct ti_ads7950_state *st = gpiochip_get_data(chip);472 int ret = 0;473 474 mutex_lock(&st->slock);475 476 /* Only change direction if needed */477 if (input && (st->gpio_cmd_settings_bitmask & BIT(offset)))478 st->gpio_cmd_settings_bitmask &= ~BIT(offset);479 else if (!input && !(st->gpio_cmd_settings_bitmask & BIT(offset)))480 st->gpio_cmd_settings_bitmask |= BIT(offset);481 else482 goto out;483 484 st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);485 ret = spi_sync(st->spi, &st->scan_single_msg);486 487out:488 mutex_unlock(&st->slock);489 490 return ret;491}492 493static int ti_ads7950_direction_input(struct gpio_chip *chip,494 unsigned int offset)495{496 return _ti_ads7950_set_direction(chip, offset, 1);497}498 499static int ti_ads7950_direction_output(struct gpio_chip *chip,500 unsigned int offset, int value)501{502 ti_ads7950_set(chip, offset, value);503 504 return _ti_ads7950_set_direction(chip, offset, 0);505}506 507static int ti_ads7950_init_hw(struct ti_ads7950_state *st)508{509 int ret = 0;510 511 mutex_lock(&st->slock);512 513 /* Settings for Manual/Auto1/Auto2 commands */514 /* Default to 5v ref */515 st->cmd_settings_bitmask = TI_ADS7950_CR_RANGE_5V;516 st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);517 ret = spi_sync(st->spi, &st->scan_single_msg);518 if (ret)519 goto out;520 521 /* Settings for GPIO command */522 st->gpio_cmd_settings_bitmask = 0x0;523 st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);524 ret = spi_sync(st->spi, &st->scan_single_msg);525 526out:527 mutex_unlock(&st->slock);528 529 return ret;530}531 532static int ti_ads7950_probe(struct spi_device *spi)533{534 struct ti_ads7950_state *st;535 struct iio_dev *indio_dev;536 const struct ti_ads7950_chip_info *info;537 int ret;538 539 spi->bits_per_word = 16;540 spi->mode |= SPI_CS_WORD;541 ret = spi_setup(spi);542 if (ret < 0) {543 dev_err(&spi->dev, "Error in spi setup\n");544 return ret;545 }546 547 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));548 if (!indio_dev)549 return -ENOMEM;550 551 st = iio_priv(indio_dev);552 553 spi_set_drvdata(spi, indio_dev);554 555 st->spi = spi;556 557 info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];558 559 indio_dev->name = spi_get_device_id(spi)->name;560 indio_dev->modes = INDIO_DIRECT_MODE;561 indio_dev->channels = info->channels;562 indio_dev->num_channels = info->num_channels;563 indio_dev->info = &ti_ads7950_info;564 565 /* build spi ring message */566 spi_message_init(&st->ring_msg);567 568 st->ring_xfer.tx_buf = &st->tx_buf[0];569 st->ring_xfer.rx_buf = &st->rx_buf[0];570 /* len will be set later */571 572 spi_message_add_tail(&st->ring_xfer, &st->ring_msg);573 574 /*575 * Setup default message. The sample is read at the end of the first576 * transfer, then it takes one full cycle to convert the sample and one577 * more cycle to send the value. The conversion process is driven by578 * the SPI clock, which is why we have 3 transfers. The middle one is579 * just dummy data sent while the chip is converting the sample that580 * was read at the end of the first transfer.581 */582 583 st->scan_single_xfer[0].tx_buf = &st->single_tx;584 st->scan_single_xfer[0].len = 2;585 st->scan_single_xfer[0].cs_change = 1;586 st->scan_single_xfer[1].tx_buf = &st->single_tx;587 st->scan_single_xfer[1].len = 2;588 st->scan_single_xfer[1].cs_change = 1;589 st->scan_single_xfer[2].rx_buf = &st->single_rx;590 st->scan_single_xfer[2].len = 2;591 592 spi_message_init_with_transfers(&st->scan_single_msg,593 st->scan_single_xfer, 3);594 595 /* Use hard coded value for reference voltage in ACPI case */596 if (ACPI_COMPANION(&spi->dev))597 st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;598 599 mutex_init(&st->slock);600 601 st->reg = devm_regulator_get(&spi->dev, "vref");602 if (IS_ERR(st->reg)) {603 ret = dev_err_probe(&spi->dev, PTR_ERR(st->reg),604 "Failed to get regulator \"vref\"\n");605 goto error_destroy_mutex;606 }607 608 ret = regulator_enable(st->reg);609 if (ret) {610 dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");611 goto error_destroy_mutex;612 }613 614 ret = iio_triggered_buffer_setup(indio_dev, NULL,615 &ti_ads7950_trigger_handler, NULL);616 if (ret) {617 dev_err(&spi->dev, "Failed to setup triggered buffer\n");618 goto error_disable_reg;619 }620 621 ret = ti_ads7950_init_hw(st);622 if (ret) {623 dev_err(&spi->dev, "Failed to init adc chip\n");624 goto error_cleanup_ring;625 }626 627 ret = iio_device_register(indio_dev);628 if (ret) {629 dev_err(&spi->dev, "Failed to register iio device\n");630 goto error_cleanup_ring;631 }632 633 /* Add GPIO chip */634 st->chip.label = dev_name(&st->spi->dev);635 st->chip.parent = &st->spi->dev;636 st->chip.owner = THIS_MODULE;637 st->chip.can_sleep = true;638 st->chip.base = -1;639 st->chip.ngpio = TI_ADS7950_NUM_GPIOS;640 st->chip.get_direction = ti_ads7950_get_direction;641 st->chip.direction_input = ti_ads7950_direction_input;642 st->chip.direction_output = ti_ads7950_direction_output;643 st->chip.get = ti_ads7950_get;644 st->chip.set = ti_ads7950_set;645 646 ret = gpiochip_add_data(&st->chip, st);647 if (ret) {648 dev_err(&spi->dev, "Failed to init GPIOs\n");649 goto error_iio_device;650 }651 652 return 0;653 654error_iio_device:655 iio_device_unregister(indio_dev);656error_cleanup_ring:657 iio_triggered_buffer_cleanup(indio_dev);658error_disable_reg:659 regulator_disable(st->reg);660error_destroy_mutex:661 mutex_destroy(&st->slock);662 663 return ret;664}665 666static void ti_ads7950_remove(struct spi_device *spi)667{668 struct iio_dev *indio_dev = spi_get_drvdata(spi);669 struct ti_ads7950_state *st = iio_priv(indio_dev);670 671 gpiochip_remove(&st->chip);672 iio_device_unregister(indio_dev);673 iio_triggered_buffer_cleanup(indio_dev);674 regulator_disable(st->reg);675 mutex_destroy(&st->slock);676}677 678static const struct spi_device_id ti_ads7950_id[] = {679 { "ads7950", TI_ADS7950 },680 { "ads7951", TI_ADS7951 },681 { "ads7952", TI_ADS7952 },682 { "ads7953", TI_ADS7953 },683 { "ads7954", TI_ADS7954 },684 { "ads7955", TI_ADS7955 },685 { "ads7956", TI_ADS7956 },686 { "ads7957", TI_ADS7957 },687 { "ads7958", TI_ADS7958 },688 { "ads7959", TI_ADS7959 },689 { "ads7960", TI_ADS7960 },690 { "ads7961", TI_ADS7961 },691 { }692};693MODULE_DEVICE_TABLE(spi, ti_ads7950_id);694 695static const struct of_device_id ads7950_of_table[] = {696 { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },697 { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },698 { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },699 { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },700 { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },701 { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },702 { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },703 { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },704 { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },705 { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },706 { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },707 { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },708 { }709};710MODULE_DEVICE_TABLE(of, ads7950_of_table);711 712static struct spi_driver ti_ads7950_driver = {713 .driver = {714 .name = "ads7950",715 .of_match_table = ads7950_of_table,716 },717 .probe = ti_ads7950_probe,718 .remove = ti_ads7950_remove,719 .id_table = ti_ads7950_id,720};721module_spi_driver(ti_ads7950_driver);722 723MODULE_AUTHOR("David Lechner <david@lechnology.com>");724MODULE_DESCRIPTION("TI TI_ADS7950 ADC");725MODULE_LICENSE("GPL v2");726