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1// SPDX-License-Identifier: GPL-2.0+2/*3 * AD7150 capacitive sensor driver supporting AD7150/1/64 *5 * Copyright 2010-2011 Analog Devices Inc.6 * Copyright 2021 Jonathan Cameron <Jonathan.Cameron@huawei.com>7 */8 9#include <linux/bitfield.h>10#include <linux/device.h>11#include <linux/interrupt.h>12#include <linux/irq.h>13#include <linux/i2c.h>14#include <linux/kernel.h>15#include <linux/module.h>16#include <linux/mod_devicetable.h>17#include <linux/regulator/consumer.h>18#include <linux/slab.h>19 20#include <linux/iio/iio.h>21#include <linux/iio/sysfs.h>22#include <linux/iio/events.h>23 24#define AD7150_STATUS_REG 025#define AD7150_STATUS_OUT1 BIT(3)26#define AD7150_STATUS_OUT2 BIT(5)27#define AD7150_CH1_DATA_HIGH_REG 128#define AD7150_CH2_DATA_HIGH_REG 329#define AD7150_CH1_AVG_HIGH_REG 530#define AD7150_CH2_AVG_HIGH_REG 731#define AD7150_CH1_SENSITIVITY_REG 932#define AD7150_CH1_THR_HOLD_H_REG 933#define AD7150_CH1_TIMEOUT_REG 1034#define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0)35#define AD7150_CH_TIMEOUT_APPROACHING GENMASK(7, 4)36#define AD7150_CH1_SETUP_REG 1137#define AD7150_CH2_SENSITIVITY_REG 1238#define AD7150_CH2_THR_HOLD_H_REG 1239#define AD7150_CH2_TIMEOUT_REG 1340#define AD7150_CH2_SETUP_REG 1441#define AD7150_CFG_REG 1542#define AD7150_CFG_FIX BIT(7)43#define AD7150_CFG_THRESHTYPE_MSK GENMASK(6, 5)44#define AD7150_CFG_TT_NEG 0x045#define AD7150_CFG_TT_POS 0x146#define AD7150_CFG_TT_IN_WINDOW 0x247#define AD7150_CFG_TT_OUT_WINDOW 0x348#define AD7150_PD_TIMER_REG 1649#define AD7150_CH1_CAPDAC_REG 1750#define AD7150_CH2_CAPDAC_REG 1851#define AD7150_SN3_REG 1952#define AD7150_SN2_REG 2053#define AD7150_SN1_REG 2154#define AD7150_SN0_REG 2255#define AD7150_ID_REG 2356 57enum {58 AD7150,59 AD7151,60};61 62/**63 * struct ad7150_chip_info - instance specific chip data64 * @client: i2c client for this device65 * @threshold: thresholds for simple capacitance value events66 * @thresh_sensitivity: threshold for simple capacitance offset67 * from 'average' value.68 * @thresh_timeout: a timeout, in samples from the moment an69 * adaptive threshold event occurs to when the average70 * value jumps to current value. Note made up of two fields,71 * 3:0 are for timeout receding - applies if below lower threshold72 * 7:4 are for timeout approaching - applies if above upper threshold73 * @state_lock: ensure consistent state of this structure wrt the74 * hardware.75 * @interrupts: one or two interrupt numbers depending on device type.76 * @int_enabled: is a given interrupt currently enabled.77 * @type: threshold type78 * @dir: threshold direction79 */80struct ad7150_chip_info {81 struct i2c_client *client;82 u16 threshold[2][2];83 u8 thresh_sensitivity[2][2];84 u8 thresh_timeout[2][2];85 struct mutex state_lock;86 int interrupts[2];87 bool int_enabled[2];88 enum iio_event_type type;89 enum iio_event_direction dir;90};91 92static const u8 ad7150_addresses[][6] = {93 { AD7150_CH1_DATA_HIGH_REG, AD7150_CH1_AVG_HIGH_REG,94 AD7150_CH1_SETUP_REG, AD7150_CH1_THR_HOLD_H_REG,95 AD7150_CH1_SENSITIVITY_REG, AD7150_CH1_TIMEOUT_REG },96 { AD7150_CH2_DATA_HIGH_REG, AD7150_CH2_AVG_HIGH_REG,97 AD7150_CH2_SETUP_REG, AD7150_CH2_THR_HOLD_H_REG,98 AD7150_CH2_SENSITIVITY_REG, AD7150_CH2_TIMEOUT_REG },99};100 101static int ad7150_read_raw(struct iio_dev *indio_dev,102 struct iio_chan_spec const *chan,103 int *val,104 int *val2,105 long mask)106{107 struct ad7150_chip_info *chip = iio_priv(indio_dev);108 int channel = chan->channel;109 int ret;110 111 switch (mask) {112 case IIO_CHAN_INFO_RAW:113 ret = i2c_smbus_read_word_swapped(chip->client,114 ad7150_addresses[channel][0]);115 if (ret < 0)116 return ret;117 *val = ret >> 4;118 119 return IIO_VAL_INT;120 case IIO_CHAN_INFO_AVERAGE_RAW:121 ret = i2c_smbus_read_word_swapped(chip->client,122 ad7150_addresses[channel][1]);123 if (ret < 0)124 return ret;125 *val = ret;126 127 return IIO_VAL_INT;128 case IIO_CHAN_INFO_SCALE:129 /*130 * Base units for capacitance are nano farads and the value131 * calculated from the datasheet formula is in picofarad132 * so multiply by 1000133 */134 *val = 1000;135 *val2 = 40944 >> 4; /* To match shift in _RAW */136 return IIO_VAL_FRACTIONAL;137 case IIO_CHAN_INFO_OFFSET:138 *val = -(12288 >> 4); /* To match shift in _RAW */139 return IIO_VAL_INT;140 case IIO_CHAN_INFO_SAMP_FREQ:141 /* Strangely same for both 1 and 2 chan parts */142 *val = 100;143 return IIO_VAL_INT;144 default:145 return -EINVAL;146 }147}148 149static int ad7150_read_event_config(struct iio_dev *indio_dev,150 const struct iio_chan_spec *chan,151 enum iio_event_type type,152 enum iio_event_direction dir)153{154 struct ad7150_chip_info *chip = iio_priv(indio_dev);155 u8 threshtype;156 bool thrfixed;157 int ret;158 159 ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);160 if (ret < 0)161 return ret;162 163 threshtype = FIELD_GET(AD7150_CFG_THRESHTYPE_MSK, ret);164 165 /*check if threshold mode is fixed or adaptive*/166 thrfixed = FIELD_GET(AD7150_CFG_FIX, ret);167 168 switch (type) {169 case IIO_EV_TYPE_THRESH_ADAPTIVE:170 if (dir == IIO_EV_DIR_RISING)171 return !thrfixed && (threshtype == AD7150_CFG_TT_POS);172 return !thrfixed && (threshtype == AD7150_CFG_TT_NEG);173 case IIO_EV_TYPE_THRESH:174 if (dir == IIO_EV_DIR_RISING)175 return thrfixed && (threshtype == AD7150_CFG_TT_POS);176 return thrfixed && (threshtype == AD7150_CFG_TT_NEG);177 default:178 break;179 }180 return -EINVAL;181}182 183/* state_lock should be held to ensure consistent state */184static int ad7150_write_event_params(struct iio_dev *indio_dev,185 unsigned int chan,186 enum iio_event_type type,187 enum iio_event_direction dir)188{189 struct ad7150_chip_info *chip = iio_priv(indio_dev);190 int rising = (dir == IIO_EV_DIR_RISING);191 192 /* Only update value live, if parameter is in use */193 if ((type != chip->type) || (dir != chip->dir))194 return 0;195 196 switch (type) {197 /* Note completely different from the adaptive versions */198 case IIO_EV_TYPE_THRESH: {199 u16 value = chip->threshold[rising][chan];200 return i2c_smbus_write_word_swapped(chip->client,201 ad7150_addresses[chan][3],202 value);203 }204 case IIO_EV_TYPE_THRESH_ADAPTIVE: {205 int ret;206 u8 sens, timeout;207 208 sens = chip->thresh_sensitivity[rising][chan];209 ret = i2c_smbus_write_byte_data(chip->client,210 ad7150_addresses[chan][4],211 sens);212 if (ret)213 return ret;214 215 /*216 * Single timeout register contains timeouts for both217 * directions.218 */219 timeout = FIELD_PREP(AD7150_CH_TIMEOUT_APPROACHING,220 chip->thresh_timeout[1][chan]);221 timeout |= FIELD_PREP(AD7150_CH_TIMEOUT_RECEDING,222 chip->thresh_timeout[0][chan]);223 return i2c_smbus_write_byte_data(chip->client,224 ad7150_addresses[chan][5],225 timeout);226 }227 default:228 return -EINVAL;229 }230}231 232static int ad7150_write_event_config(struct iio_dev *indio_dev,233 const struct iio_chan_spec *chan,234 enum iio_event_type type,235 enum iio_event_direction dir, int state)236{237 struct ad7150_chip_info *chip = iio_priv(indio_dev);238 int ret = 0;239 240 /*241 * There is only a single shared control and no on chip242 * interrupt disables for the two interrupt lines.243 * So, enabling will switch the events configured to enable244 * whatever was most recently requested and if necessary enable_irq()245 * the interrupt and any disable will disable_irq() for that246 * channels interrupt.247 */248 if (!state) {249 if ((chip->int_enabled[chan->channel]) &&250 (type == chip->type) && (dir == chip->dir)) {251 disable_irq(chip->interrupts[chan->channel]);252 chip->int_enabled[chan->channel] = false;253 }254 return 0;255 }256 257 mutex_lock(&chip->state_lock);258 if ((type != chip->type) || (dir != chip->dir)) {259 int rising = (dir == IIO_EV_DIR_RISING);260 u8 thresh_type, cfg, fixed;261 262 /*263 * Need to temporarily disable both interrupts if264 * enabled - this is to avoid races around changing265 * config and thresholds.266 * Note enable/disable_irq() are reference counted so267 * no need to check if already enabled.268 */269 disable_irq(chip->interrupts[0]);270 disable_irq(chip->interrupts[1]);271 272 ret = i2c_smbus_read_byte_data(chip->client, AD7150_CFG_REG);273 if (ret < 0)274 goto error_ret;275 276 cfg = ret & ~(AD7150_CFG_THRESHTYPE_MSK | AD7150_CFG_FIX);277 278 if (type == IIO_EV_TYPE_THRESH_ADAPTIVE)279 fixed = 0;280 else281 fixed = 1;282 283 if (rising)284 thresh_type = AD7150_CFG_TT_POS;285 else286 thresh_type = AD7150_CFG_TT_NEG;287 288 cfg |= FIELD_PREP(AD7150_CFG_FIX, fixed) |289 FIELD_PREP(AD7150_CFG_THRESHTYPE_MSK, thresh_type);290 291 ret = i2c_smbus_write_byte_data(chip->client, AD7150_CFG_REG,292 cfg);293 if (ret < 0)294 goto error_ret;295 296 /*297 * There is a potential race condition here, but not easy298 * to close given we can't disable the interrupt at the299 * chip side of things. Rely on the status bit.300 */301 chip->type = type;302 chip->dir = dir;303 304 /* update control attributes */305 ret = ad7150_write_event_params(indio_dev, chan->channel, type,306 dir);307 if (ret)308 goto error_ret;309 /* reenable any irq's we disabled whilst changing mode */310 enable_irq(chip->interrupts[0]);311 enable_irq(chip->interrupts[1]);312 }313 if (!chip->int_enabled[chan->channel]) {314 enable_irq(chip->interrupts[chan->channel]);315 chip->int_enabled[chan->channel] = true;316 }317 318error_ret:319 mutex_unlock(&chip->state_lock);320 321 return ret;322}323 324static int ad7150_read_event_value(struct iio_dev *indio_dev,325 const struct iio_chan_spec *chan,326 enum iio_event_type type,327 enum iio_event_direction dir,328 enum iio_event_info info,329 int *val, int *val2)330{331 struct ad7150_chip_info *chip = iio_priv(indio_dev);332 int rising = (dir == IIO_EV_DIR_RISING);333 334 /* Complex register sharing going on here */335 switch (info) {336 case IIO_EV_INFO_VALUE:337 switch (type) {338 case IIO_EV_TYPE_THRESH_ADAPTIVE:339 *val = chip->thresh_sensitivity[rising][chan->channel];340 return IIO_VAL_INT;341 case IIO_EV_TYPE_THRESH:342 *val = chip->threshold[rising][chan->channel];343 return IIO_VAL_INT;344 default:345 return -EINVAL;346 }347 case IIO_EV_INFO_TIMEOUT:348 *val = 0;349 *val2 = chip->thresh_timeout[rising][chan->channel] * 10000;350 return IIO_VAL_INT_PLUS_MICRO;351 default:352 return -EINVAL;353 }354}355 356static int ad7150_write_event_value(struct iio_dev *indio_dev,357 const struct iio_chan_spec *chan,358 enum iio_event_type type,359 enum iio_event_direction dir,360 enum iio_event_info info,361 int val, int val2)362{363 int ret;364 struct ad7150_chip_info *chip = iio_priv(indio_dev);365 int rising = (dir == IIO_EV_DIR_RISING);366 367 mutex_lock(&chip->state_lock);368 switch (info) {369 case IIO_EV_INFO_VALUE:370 switch (type) {371 case IIO_EV_TYPE_THRESH_ADAPTIVE:372 chip->thresh_sensitivity[rising][chan->channel] = val;373 break;374 case IIO_EV_TYPE_THRESH:375 chip->threshold[rising][chan->channel] = val;376 break;377 default:378 ret = -EINVAL;379 goto error_ret;380 }381 break;382 case IIO_EV_INFO_TIMEOUT: {383 /*384 * Raw timeout is in cycles of 10 msecs as long as both385 * channels are enabled.386 * In terms of INT_PLUS_MICRO, that is in units of 10,000387 */388 int timeout = val2 / 10000;389 390 if (val != 0 || timeout < 0 || timeout > 15 || val2 % 10000) {391 ret = -EINVAL;392 goto error_ret;393 }394 395 chip->thresh_timeout[rising][chan->channel] = timeout;396 break;397 }398 default:399 ret = -EINVAL;400 goto error_ret;401 }402 403 /* write back if active */404 ret = ad7150_write_event_params(indio_dev, chan->channel, type, dir);405 406error_ret:407 mutex_unlock(&chip->state_lock);408 return ret;409}410 411static const struct iio_event_spec ad7150_events[] = {412 {413 .type = IIO_EV_TYPE_THRESH,414 .dir = IIO_EV_DIR_RISING,415 .mask_separate = BIT(IIO_EV_INFO_VALUE) |416 BIT(IIO_EV_INFO_ENABLE),417 }, {418 .type = IIO_EV_TYPE_THRESH,419 .dir = IIO_EV_DIR_FALLING,420 .mask_separate = BIT(IIO_EV_INFO_VALUE) |421 BIT(IIO_EV_INFO_ENABLE),422 }, {423 .type = IIO_EV_TYPE_THRESH_ADAPTIVE,424 .dir = IIO_EV_DIR_RISING,425 .mask_separate = BIT(IIO_EV_INFO_VALUE) |426 BIT(IIO_EV_INFO_ENABLE) |427 BIT(IIO_EV_INFO_TIMEOUT),428 }, {429 .type = IIO_EV_TYPE_THRESH_ADAPTIVE,430 .dir = IIO_EV_DIR_FALLING,431 .mask_separate = BIT(IIO_EV_INFO_VALUE) |432 BIT(IIO_EV_INFO_ENABLE) |433 BIT(IIO_EV_INFO_TIMEOUT),434 },435};436 437#define AD7150_CAPACITANCE_CHAN(_chan) { \438 .type = IIO_CAPACITANCE, \439 .indexed = 1, \440 .channel = _chan, \441 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \442 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \443 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \444 BIT(IIO_CHAN_INFO_OFFSET), \445 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\446 .event_spec = ad7150_events, \447 .num_event_specs = ARRAY_SIZE(ad7150_events), \448 }449 450#define AD7150_CAPACITANCE_CHAN_NO_IRQ(_chan) { \451 .type = IIO_CAPACITANCE, \452 .indexed = 1, \453 .channel = _chan, \454 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \455 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \456 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \457 BIT(IIO_CHAN_INFO_OFFSET), \458 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\459 }460 461static const struct iio_chan_spec ad7150_channels[] = {462 AD7150_CAPACITANCE_CHAN(0),463 AD7150_CAPACITANCE_CHAN(1),464};465 466static const struct iio_chan_spec ad7150_channels_no_irq[] = {467 AD7150_CAPACITANCE_CHAN_NO_IRQ(0),468 AD7150_CAPACITANCE_CHAN_NO_IRQ(1),469};470 471static const struct iio_chan_spec ad7151_channels[] = {472 AD7150_CAPACITANCE_CHAN(0),473};474 475static const struct iio_chan_spec ad7151_channels_no_irq[] = {476 AD7150_CAPACITANCE_CHAN_NO_IRQ(0),477};478 479static irqreturn_t __ad7150_event_handler(void *private, u8 status_mask,480 int channel)481{482 struct iio_dev *indio_dev = private;483 struct ad7150_chip_info *chip = iio_priv(indio_dev);484 s64 timestamp = iio_get_time_ns(indio_dev);485 int int_status;486 487 int_status = i2c_smbus_read_byte_data(chip->client, AD7150_STATUS_REG);488 if (int_status < 0)489 return IRQ_HANDLED;490 491 if (!(int_status & status_mask))492 return IRQ_HANDLED;493 494 iio_push_event(indio_dev,495 IIO_UNMOD_EVENT_CODE(IIO_CAPACITANCE, channel,496 chip->type, chip->dir),497 timestamp);498 499 return IRQ_HANDLED;500}501 502static irqreturn_t ad7150_event_handler_ch1(int irq, void *private)503{504 return __ad7150_event_handler(private, AD7150_STATUS_OUT1, 0);505}506 507static irqreturn_t ad7150_event_handler_ch2(int irq, void *private)508{509 return __ad7150_event_handler(private, AD7150_STATUS_OUT2, 1);510}511 512static IIO_CONST_ATTR(in_capacitance_thresh_adaptive_timeout_available,513 "[0 0.01 0.15]");514 515static struct attribute *ad7150_event_attributes[] = {516 &iio_const_attr_in_capacitance_thresh_adaptive_timeout_available517 .dev_attr.attr,518 NULL,519};520 521static const struct attribute_group ad7150_event_attribute_group = {522 .attrs = ad7150_event_attributes,523 .name = "events",524};525 526static const struct iio_info ad7150_info = {527 .event_attrs = &ad7150_event_attribute_group,528 .read_raw = &ad7150_read_raw,529 .read_event_config = &ad7150_read_event_config,530 .write_event_config = &ad7150_write_event_config,531 .read_event_value = &ad7150_read_event_value,532 .write_event_value = &ad7150_write_event_value,533};534 535static const struct iio_info ad7150_info_no_irq = {536 .read_raw = &ad7150_read_raw,537};538 539static int ad7150_probe(struct i2c_client *client)540{541 const struct i2c_device_id *id = i2c_client_get_device_id(client);542 struct ad7150_chip_info *chip;543 struct iio_dev *indio_dev;544 bool use_irq = true;545 int ret;546 547 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));548 if (!indio_dev)549 return -ENOMEM;550 551 chip = iio_priv(indio_dev);552 mutex_init(&chip->state_lock);553 chip->client = client;554 555 indio_dev->name = id->name;556 557 indio_dev->modes = INDIO_DIRECT_MODE;558 559 ret = devm_regulator_get_enable(&client->dev, "vdd");560 if (ret)561 return ret;562 563 chip->interrupts[0] = fwnode_irq_get(dev_fwnode(&client->dev), 0);564 if (chip->interrupts[0] < 0)565 use_irq = false;566 else if (id->driver_data == AD7150) {567 chip->interrupts[1] = fwnode_irq_get(dev_fwnode(&client->dev), 1);568 if (chip->interrupts[1] < 0)569 use_irq = false;570 }571 if (use_irq) {572 irq_set_status_flags(chip->interrupts[0], IRQ_NOAUTOEN);573 ret = devm_request_threaded_irq(&client->dev,574 chip->interrupts[0],575 NULL,576 &ad7150_event_handler_ch1,577 IRQF_TRIGGER_RISING |578 IRQF_ONESHOT,579 "ad7150_irq1",580 indio_dev);581 if (ret)582 return ret;583 584 indio_dev->info = &ad7150_info;585 switch (id->driver_data) {586 case AD7150:587 indio_dev->channels = ad7150_channels;588 indio_dev->num_channels = ARRAY_SIZE(ad7150_channels);589 irq_set_status_flags(chip->interrupts[1], IRQ_NOAUTOEN);590 ret = devm_request_threaded_irq(&client->dev,591 chip->interrupts[1],592 NULL,593 &ad7150_event_handler_ch2,594 IRQF_TRIGGER_RISING |595 IRQF_ONESHOT,596 "ad7150_irq2",597 indio_dev);598 if (ret)599 return ret;600 break;601 case AD7151:602 indio_dev->channels = ad7151_channels;603 indio_dev->num_channels = ARRAY_SIZE(ad7151_channels);604 break;605 default:606 return -EINVAL;607 }608 609 } else {610 indio_dev->info = &ad7150_info_no_irq;611 switch (id->driver_data) {612 case AD7150:613 indio_dev->channels = ad7150_channels_no_irq;614 indio_dev->num_channels =615 ARRAY_SIZE(ad7150_channels_no_irq);616 break;617 case AD7151:618 indio_dev->channels = ad7151_channels_no_irq;619 indio_dev->num_channels =620 ARRAY_SIZE(ad7151_channels_no_irq);621 break;622 default:623 return -EINVAL;624 }625 }626 627 return devm_iio_device_register(indio_dev->dev.parent, indio_dev);628}629 630static const struct i2c_device_id ad7150_id[] = {631 { "ad7150", AD7150 },632 { "ad7151", AD7151 },633 { "ad7156", AD7150 },634 {}635};636 637MODULE_DEVICE_TABLE(i2c, ad7150_id);638 639static const struct of_device_id ad7150_of_match[] = {640 { "adi,ad7150" },641 { "adi,ad7151" },642 { "adi,ad7156" },643 {}644};645static struct i2c_driver ad7150_driver = {646 .driver = {647 .name = "ad7150",648 .of_match_table = ad7150_of_match,649 },650 .probe = ad7150_probe,651 .id_table = ad7150_id,652};653module_i2c_driver(ad7150_driver);654 655MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");656MODULE_DESCRIPTION("Analog Devices AD7150/1/6 capacitive sensor driver");657MODULE_LICENSE("GPL v2");658