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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Analog Devices AD3552R4 * Digital to Analog converter driver5 *6 * Copyright 2021 Analog Devices Inc.7 */8#include <linux/unaligned.h>9#include <linux/device.h>10#include <linux/iio/triggered_buffer.h>11#include <linux/iio/trigger_consumer.h>12#include <linux/iopoll.h>13#include <linux/kernel.h>14#include <linux/regulator/consumer.h>15#include <linux/spi/spi.h>16 17/* Register addresses */18/* Primary address space */19#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A 0x0020#define AD3552R_MASK_SOFTWARE_RESET (BIT(7) | BIT(0))21#define AD3552R_MASK_ADDR_ASCENSION BIT(5)22#define AD3552R_MASK_SDO_ACTIVE BIT(4)23#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B 0x0124#define AD3552R_MASK_SINGLE_INST BIT(7)25#define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)26#define AD3552R_REG_ADDR_DEVICE_CONFIG 0x0227#define AD3552R_MASK_DEVICE_STATUS(n) BIT(4 + (n))28#define AD3552R_MASK_CUSTOM_MODES GENMASK(3, 2)29#define AD3552R_MASK_OPERATING_MODES GENMASK(1, 0)30#define AD3552R_REG_ADDR_CHIP_TYPE 0x0331#define AD3552R_MASK_CLASS GENMASK(7, 0)32#define AD3552R_REG_ADDR_PRODUCT_ID_L 0x0433#define AD3552R_REG_ADDR_PRODUCT_ID_H 0x0534#define AD3552R_REG_ADDR_CHIP_GRADE 0x0635#define AD3552R_MASK_GRADE GENMASK(7, 4)36#define AD3552R_MASK_DEVICE_REVISION GENMASK(3, 0)37#define AD3552R_REG_ADDR_SCRATCH_PAD 0x0A38#define AD3552R_REG_ADDR_SPI_REVISION 0x0B39#define AD3552R_REG_ADDR_VENDOR_L 0x0C40#define AD3552R_REG_ADDR_VENDOR_H 0x0D41#define AD3552R_REG_ADDR_STREAM_MODE 0x0E42#define AD3552R_MASK_LENGTH GENMASK(7, 0)43#define AD3552R_REG_ADDR_TRANSFER_REGISTER 0x0F44#define AD3552R_MASK_MULTI_IO_MODE GENMASK(7, 6)45#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE BIT(2)46#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C 0x1047#define AD3552R_MASK_CRC_ENABLE (GENMASK(7, 6) |\48 GENMASK(1, 0))49#define AD3552R_MASK_STRICT_REGISTER_ACCESS BIT(5)50#define AD3552R_REG_ADDR_INTERFACE_STATUS_A 0x1151#define AD3552R_MASK_INTERFACE_NOT_READY BIT(7)52#define AD3552R_MASK_CLOCK_COUNTING_ERROR BIT(5)53#define AD3552R_MASK_INVALID_OR_NO_CRC BIT(3)54#define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER BIT(2)55#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS BIT(1)56#define AD3552R_MASK_REGISTER_ADDRESS_INVALID BIT(0)57#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D 0x1458#define AD3552R_MASK_ALERT_ENABLE_PULLUP BIT(6)59#define AD3552R_MASK_MEM_CRC_EN BIT(4)60#define AD3552R_MASK_SDO_DRIVE_STRENGTH GENMASK(3, 2)61#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN BIT(1)62#define AD3552R_MASK_SPI_CONFIG_DDR BIT(0)63#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG 0x1564#define AD3552R_MASK_IDUMP_FAST_MODE BIT(6)65#define AD3552R_MASK_SAMPLE_HOLD_DIFFERENTIAL_USER_EN BIT(5)66#define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM GENMASK(4, 3)67#define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE BIT(2)68#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL GENMASK(1, 0)69#define AD3552R_REG_ADDR_ERR_ALARM_MASK 0x1670#define AD3552R_MASK_REF_RANGE_ALARM BIT(6)71#define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM BIT(5)72#define AD3552R_MASK_MEM_CRC_ERR_ALARM BIT(4)73#define AD3552R_MASK_SPI_CRC_ERR_ALARM BIT(3)74#define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM BIT(2)75#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM BIT(1)76#define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM BIT(0)77#define AD3552R_REG_ADDR_ERR_STATUS 0x1778#define AD3552R_MASK_REF_RANGE_ERR_STATUS BIT(6)79#define AD3552R_MASK_DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS BIT(5)80#define AD3552R_MASK_MEM_CRC_ERR_STATUS BIT(4)81#define AD3552R_MASK_RESET_STATUS BIT(0)82#define AD3552R_REG_ADDR_POWERDOWN_CONFIG 0x1883#define AD3552R_MASK_CH_DAC_POWERDOWN(ch) BIT(4 + (ch))84#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch) BIT(ch)85#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE 0x1986#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch) ((ch) ? GENMASK(7, 4) :\87 GENMASK(3, 0))88#define AD3552R_REG_ADDR_CH_OFFSET(ch) (0x1B + (ch) * 2)89#define AD3552R_MASK_CH_OFFSET_BITS_0_7 GENMASK(7, 0)90#define AD3552R_REG_ADDR_CH_GAIN(ch) (0x1C + (ch) * 2)91#define AD3552R_MASK_CH_RANGE_OVERRIDE BIT(7)92#define AD3552R_MASK_CH_GAIN_SCALING_N GENMASK(6, 5)93#define AD3552R_MASK_CH_GAIN_SCALING_P GENMASK(4, 3)94#define AD3552R_MASK_CH_OFFSET_POLARITY BIT(2)95#define AD3552R_MASK_CH_OFFSET_BIT_8 BIT(0)96/*97 * Secondary region98 * For multibyte registers specify the highest address because the access is99 * done in descending order100 */101#define AD3552R_SECONDARY_REGION_START 0x28102#define AD3552R_REG_ADDR_HW_LDAC_16B 0x28103#define AD3552R_REG_ADDR_CH_DAC_16B(ch) (0x2C - (1 - ch) * 2)104#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B 0x2E105#define AD3552R_REG_ADDR_CH_SELECT_16B 0x2F106#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B 0x31107#define AD3552R_REG_ADDR_SW_LDAC_16B 0x32108#define AD3552R_REG_ADDR_CH_INPUT_16B(ch) (0x36 - (1 - ch) * 2)109/* 3 bytes registers */110#define AD3552R_REG_START_24B 0x37111#define AD3552R_REG_ADDR_HW_LDAC_24B 0x37112#define AD3552R_REG_ADDR_CH_DAC_24B(ch) (0x3D - (1 - ch) * 3)113#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B 0x40114#define AD3552R_REG_ADDR_CH_SELECT_24B 0x41115#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B 0x44116#define AD3552R_REG_ADDR_SW_LDAC_24B 0x45117#define AD3552R_REG_ADDR_CH_INPUT_24B(ch) (0x4B - (1 - ch) * 3)118 119/* Useful defines */120#define AD3552R_MAX_CH 2121#define AD3552R_MASK_CH(ch) BIT(ch)122#define AD3552R_MASK_ALL_CH GENMASK(1, 0)123#define AD3552R_MAX_REG_SIZE 3124#define AD3552R_READ_BIT BIT(7)125#define AD3552R_ADDR_MASK GENMASK(6, 0)126#define AD3552R_MASK_DAC_12B 0xFFF0127#define AD3552R_DEFAULT_CONFIG_B_VALUE 0x8128#define AD3552R_SCRATCH_PAD_TEST_VAL1 0x34129#define AD3552R_SCRATCH_PAD_TEST_VAL2 0xB2130#define AD3552R_GAIN_SCALE 1000131#define AD3552R_LDAC_PULSE_US 100132 133enum ad3552r_ch_vref_select {134 /* Internal source with Vref I/O floating */135 AD3552R_INTERNAL_VREF_PIN_FLOATING,136 /* Internal source with Vref I/O at 2.5V */137 AD3552R_INTERNAL_VREF_PIN_2P5V,138 /* External source with Vref I/O as input */139 AD3552R_EXTERNAL_VREF_PIN_INPUT140};141 142enum ad3552r_id {143 AD3541R_ID = 0x400b,144 AD3542R_ID = 0x4009,145 AD3551R_ID = 0x400a,146 AD3552R_ID = 0x4008,147};148 149enum ad3552r_ch_output_range {150 /* Range from 0 V to 2.5 V. Requires Rfb1x connection */151 AD3552R_CH_OUTPUT_RANGE_0__2P5V,152 /* Range from 0 V to 5 V. Requires Rfb1x connection */153 AD3552R_CH_OUTPUT_RANGE_0__5V,154 /* Range from 0 V to 10 V. Requires Rfb2x connection */155 AD3552R_CH_OUTPUT_RANGE_0__10V,156 /* Range from -5 V to 5 V. Requires Rfb2x connection */157 AD3552R_CH_OUTPUT_RANGE_NEG_5__5V,158 /* Range from -10 V to 10 V. Requires Rfb4x connection */159 AD3552R_CH_OUTPUT_RANGE_NEG_10__10V,160};161 162static const s32 ad3552r_ch_ranges[][2] = {163 [AD3552R_CH_OUTPUT_RANGE_0__2P5V] = {0, 2500},164 [AD3552R_CH_OUTPUT_RANGE_0__5V] = {0, 5000},165 [AD3552R_CH_OUTPUT_RANGE_0__10V] = {0, 10000},166 [AD3552R_CH_OUTPUT_RANGE_NEG_5__5V] = {-5000, 5000},167 [AD3552R_CH_OUTPUT_RANGE_NEG_10__10V] = {-10000, 10000}168};169 170enum ad3542r_ch_output_range {171 /* Range from 0 V to 2.5 V. Requires Rfb1x connection */172 AD3542R_CH_OUTPUT_RANGE_0__2P5V,173 /* Range from 0 V to 3 V. Requires Rfb1x connection */174 AD3542R_CH_OUTPUT_RANGE_0__3V,175 /* Range from 0 V to 5 V. Requires Rfb1x connection */176 AD3542R_CH_OUTPUT_RANGE_0__5V,177 /* Range from 0 V to 10 V. Requires Rfb2x connection */178 AD3542R_CH_OUTPUT_RANGE_0__10V,179 /* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */180 AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V,181 /* Range from -5 V to 5 V. Requires Rfb2x connection */182 AD3542R_CH_OUTPUT_RANGE_NEG_5__5V,183};184 185static const s32 ad3542r_ch_ranges[][2] = {186 [AD3542R_CH_OUTPUT_RANGE_0__2P5V] = {0, 2500},187 [AD3542R_CH_OUTPUT_RANGE_0__3V] = {0, 3000},188 [AD3542R_CH_OUTPUT_RANGE_0__5V] = {0, 5000},189 [AD3542R_CH_OUTPUT_RANGE_0__10V] = {0, 10000},190 [AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V] = {-2500, 7500},191 [AD3542R_CH_OUTPUT_RANGE_NEG_5__5V] = {-5000, 5000}192};193 194enum ad3552r_ch_gain_scaling {195 /* Gain scaling of 1 */196 AD3552R_CH_GAIN_SCALING_1,197 /* Gain scaling of 0.5 */198 AD3552R_CH_GAIN_SCALING_0_5,199 /* Gain scaling of 0.25 */200 AD3552R_CH_GAIN_SCALING_0_25,201 /* Gain scaling of 0.125 */202 AD3552R_CH_GAIN_SCALING_0_125,203};204 205/* Gain * AD3552R_GAIN_SCALE */206static const s32 gains_scaling_table[] = {207 [AD3552R_CH_GAIN_SCALING_1] = 1000,208 [AD3552R_CH_GAIN_SCALING_0_5] = 500,209 [AD3552R_CH_GAIN_SCALING_0_25] = 250,210 [AD3552R_CH_GAIN_SCALING_0_125] = 125211};212 213enum ad3552r_dev_attributes {214 /* - Direct register values */215 /* From 0-3 */216 AD3552R_SDO_DRIVE_STRENGTH,217 /*218 * 0 -> Internal Vref, vref_io pin floating (default)219 * 1 -> Internal Vref, vref_io driven by internal vref220 * 2 or 3 -> External Vref221 */222 AD3552R_VREF_SELECT,223 /* Read registers in ascending order if set. Else descending */224 AD3552R_ADDR_ASCENSION,225};226 227enum ad3552r_ch_attributes {228 /* DAC powerdown */229 AD3552R_CH_DAC_POWERDOWN,230 /* DAC amplifier powerdown */231 AD3552R_CH_AMPLIFIER_POWERDOWN,232 /* Select the output range. Select from enum ad3552r_ch_output_range */233 AD3552R_CH_OUTPUT_RANGE_SEL,234 /*235 * Over-rider the range selector in order to manually set the output236 * voltage range237 */238 AD3552R_CH_RANGE_OVERRIDE,239 /* Manually set the offset voltage */240 AD3552R_CH_GAIN_OFFSET,241 /* Sets the polarity of the offset. */242 AD3552R_CH_GAIN_OFFSET_POLARITY,243 /* PDAC gain scaling */244 AD3552R_CH_GAIN_SCALING_P,245 /* NDAC gain scaling */246 AD3552R_CH_GAIN_SCALING_N,247 /* Rfb value */248 AD3552R_CH_RFB,249 /* Channel select. When set allow Input -> DAC and Mask -> DAC */250 AD3552R_CH_SELECT,251};252 253struct ad3552r_ch_data {254 s32 scale_int;255 s32 scale_dec;256 s32 offset_int;257 s32 offset_dec;258 s16 gain_offset;259 u16 rfb;260 u8 n;261 u8 p;262 u8 range;263 bool range_override;264};265 266struct ad3552r_model_data {267 const char *model_name;268 enum ad3552r_id chip_id;269 unsigned int num_hw_channels;270 const s32 (*ranges_table)[2];271 int num_ranges;272 bool requires_output_range;273};274 275struct ad3552r_desc {276 const struct ad3552r_model_data *model_data;277 /* Used to look the spi bus for atomic operations where needed */278 struct mutex lock;279 struct gpio_desc *gpio_reset;280 struct gpio_desc *gpio_ldac;281 struct spi_device *spi;282 struct ad3552r_ch_data ch_data[AD3552R_MAX_CH];283 struct iio_chan_spec channels[AD3552R_MAX_CH + 1];284 unsigned long enabled_ch;285 unsigned int num_ch;286};287 288static const u16 addr_mask_map[][2] = {289 [AD3552R_ADDR_ASCENSION] = {290 AD3552R_REG_ADDR_INTERFACE_CONFIG_A,291 AD3552R_MASK_ADDR_ASCENSION292 },293 [AD3552R_SDO_DRIVE_STRENGTH] = {294 AD3552R_REG_ADDR_INTERFACE_CONFIG_D,295 AD3552R_MASK_SDO_DRIVE_STRENGTH296 },297 [AD3552R_VREF_SELECT] = {298 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,299 AD3552R_MASK_REFERENCE_VOLTAGE_SEL300 },301};302 303/* 0 -> reg addr, 1->ch0 mask, 2->ch1 mask */304static const u16 addr_mask_map_ch[][3] = {305 [AD3552R_CH_DAC_POWERDOWN] = {306 AD3552R_REG_ADDR_POWERDOWN_CONFIG,307 AD3552R_MASK_CH_DAC_POWERDOWN(0),308 AD3552R_MASK_CH_DAC_POWERDOWN(1)309 },310 [AD3552R_CH_AMPLIFIER_POWERDOWN] = {311 AD3552R_REG_ADDR_POWERDOWN_CONFIG,312 AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0),313 AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1)314 },315 [AD3552R_CH_OUTPUT_RANGE_SEL] = {316 AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,317 AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0),318 AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1)319 },320 [AD3552R_CH_SELECT] = {321 AD3552R_REG_ADDR_CH_SELECT_16B,322 AD3552R_MASK_CH(0),323 AD3552R_MASK_CH(1)324 }325};326 327static u8 _ad3552r_reg_len(u8 addr)328{329 switch (addr) {330 case AD3552R_REG_ADDR_HW_LDAC_16B:331 case AD3552R_REG_ADDR_CH_SELECT_16B:332 case AD3552R_REG_ADDR_SW_LDAC_16B:333 case AD3552R_REG_ADDR_HW_LDAC_24B:334 case AD3552R_REG_ADDR_CH_SELECT_24B:335 case AD3552R_REG_ADDR_SW_LDAC_24B:336 return 1;337 default:338 break;339 }340 341 if (addr > AD3552R_REG_ADDR_HW_LDAC_24B)342 return 3;343 if (addr > AD3552R_REG_ADDR_HW_LDAC_16B)344 return 2;345 346 return 1;347}348 349/* SPI transfer to device */350static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len,351 u8 *data, bool is_read)352{353 /* Maximum transfer: Addr (1B) + 2 * (Data Reg (3B)) + SW LDAC(1B) */354 u8 buf[8];355 356 buf[0] = addr & AD3552R_ADDR_MASK;357 buf[0] |= is_read ? AD3552R_READ_BIT : 0;358 if (is_read)359 return spi_write_then_read(dac->spi, buf, 1, data, len);360 361 memcpy(buf + 1, data, len);362 return spi_write_then_read(dac->spi, buf, len + 1, NULL, 0);363}364 365static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)366{367 u8 reg_len;368 u8 buf[AD3552R_MAX_REG_SIZE] = { 0 };369 370 reg_len = _ad3552r_reg_len(addr);371 if (reg_len == 2)372 /* Only DAC register are 2 bytes wide */373 val &= AD3552R_MASK_DAC_12B;374 if (reg_len == 1)375 buf[0] = val & 0xFF;376 else377 /* reg_len can be 2 or 3, but 3rd bytes needs to be set to 0 */378 put_unaligned_be16(val, buf);379 380 return ad3552r_transfer(dac, addr, reg_len, buf, false);381}382 383static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)384{385 int err;386 u8 reg_len, buf[AD3552R_MAX_REG_SIZE] = { 0 };387 388 reg_len = _ad3552r_reg_len(addr);389 err = ad3552r_transfer(dac, addr, reg_len, buf, true);390 if (err)391 return err;392 393 if (reg_len == 1)394 *val = buf[0];395 else396 /* reg_len can be 2 or 3, but only first 2 bytes are relevant */397 *val = get_unaligned_be16(buf);398 399 return 0;400}401 402static u16 ad3552r_field_prep(u16 val, u16 mask)403{404 return (val << __ffs(mask)) & mask;405}406 407/* Update field of a register, shift val if needed */408static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask,409 u16 val)410{411 int ret;412 u16 reg;413 414 ret = ad3552r_read_reg(dac, addr, ®);415 if (ret < 0)416 return ret;417 418 reg &= ~mask;419 reg |= ad3552r_field_prep(val, mask);420 421 return ad3552r_write_reg(dac, addr, reg);422}423 424static int ad3552r_set_ch_value(struct ad3552r_desc *dac,425 enum ad3552r_ch_attributes attr,426 u8 ch,427 u16 val)428{429 /* Update register related to attributes in chip */430 return ad3552r_update_reg_field(dac, addr_mask_map_ch[attr][0],431 addr_mask_map_ch[attr][ch + 1], val);432}433 434#define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) { \435 .type = IIO_VOLTAGE, \436 .output = true, \437 .indexed = true, \438 .channel = _idx, \439 .scan_index = _idx, \440 .scan_type = { \441 .sign = 'u', \442 .realbits = 16, \443 .storagebits = 16, \444 .endianness = IIO_BE, \445 }, \446 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \447 BIT(IIO_CHAN_INFO_SCALE) | \448 BIT(IIO_CHAN_INFO_ENABLE) | \449 BIT(IIO_CHAN_INFO_OFFSET), \450})451 452static int ad3552r_read_raw(struct iio_dev *indio_dev,453 struct iio_chan_spec const *chan,454 int *val,455 int *val2,456 long mask)457{458 struct ad3552r_desc *dac = iio_priv(indio_dev);459 u16 tmp_val;460 int err;461 u8 ch = chan->channel;462 463 switch (mask) {464 case IIO_CHAN_INFO_RAW:465 mutex_lock(&dac->lock);466 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch),467 &tmp_val);468 mutex_unlock(&dac->lock);469 if (err < 0)470 return err;471 *val = tmp_val;472 return IIO_VAL_INT;473 case IIO_CHAN_INFO_ENABLE:474 mutex_lock(&dac->lock);475 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,476 &tmp_val);477 mutex_unlock(&dac->lock);478 if (err < 0)479 return err;480 *val = !((tmp_val & AD3552R_MASK_CH_DAC_POWERDOWN(ch)) >>481 __ffs(AD3552R_MASK_CH_DAC_POWERDOWN(ch)));482 return IIO_VAL_INT;483 case IIO_CHAN_INFO_SCALE:484 *val = dac->ch_data[ch].scale_int;485 *val2 = dac->ch_data[ch].scale_dec;486 return IIO_VAL_INT_PLUS_MICRO;487 case IIO_CHAN_INFO_OFFSET:488 *val = dac->ch_data[ch].offset_int;489 *val2 = dac->ch_data[ch].offset_dec;490 return IIO_VAL_INT_PLUS_MICRO;491 default:492 return -EINVAL;493 }494}495 496static int ad3552r_write_raw(struct iio_dev *indio_dev,497 struct iio_chan_spec const *chan,498 int val,499 int val2,500 long mask)501{502 struct ad3552r_desc *dac = iio_priv(indio_dev);503 int err;504 505 mutex_lock(&dac->lock);506 switch (mask) {507 case IIO_CHAN_INFO_RAW:508 err = ad3552r_write_reg(dac,509 AD3552R_REG_ADDR_CH_DAC_24B(chan->channel),510 val);511 break;512 case IIO_CHAN_INFO_ENABLE:513 err = ad3552r_set_ch_value(dac, AD3552R_CH_DAC_POWERDOWN,514 chan->channel, !val);515 break;516 default:517 err = -EINVAL;518 break;519 }520 mutex_unlock(&dac->lock);521 522 return err;523}524 525static const struct iio_info ad3552r_iio_info = {526 .read_raw = ad3552r_read_raw,527 .write_raw = ad3552r_write_raw528};529 530static int32_t ad3552r_trigger_hw_ldac(struct gpio_desc *ldac)531{532 gpiod_set_value_cansleep(ldac, 0);533 usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10);534 gpiod_set_value_cansleep(ldac, 1);535 536 return 0;537}538 539static int ad3552r_write_all_channels(struct ad3552r_desc *dac, u8 *data)540{541 int err, len;542 u8 addr, buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE + 1];543 544 addr = AD3552R_REG_ADDR_CH_INPUT_24B(1);545 /* CH1 */546 memcpy(buff, data + 2, 2);547 buff[2] = 0;548 /* CH0 */549 memcpy(buff + 3, data, 2);550 buff[5] = 0;551 len = 6;552 if (!dac->gpio_ldac) {553 /* Software LDAC */554 buff[6] = AD3552R_MASK_ALL_CH;555 ++len;556 }557 err = ad3552r_transfer(dac, addr, len, buff, false);558 if (err)559 return err;560 561 if (dac->gpio_ldac)562 return ad3552r_trigger_hw_ldac(dac->gpio_ldac);563 564 return 0;565}566 567static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data)568{569 int err;570 u8 addr, buff[AD3552R_MAX_REG_SIZE];571 572 if (mask == AD3552R_MASK_ALL_CH) {573 if (memcmp(data, data + 2, 2) != 0)574 return ad3552r_write_all_channels(dac, data);575 576 addr = AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B;577 } else {578 addr = AD3552R_REG_ADDR_CH_INPUT_24B(__ffs(mask));579 }580 581 memcpy(buff, data, 2);582 buff[2] = 0;583 err = ad3552r_transfer(dac, addr, 3, data, false);584 if (err)585 return err;586 587 if (dac->gpio_ldac)588 return ad3552r_trigger_hw_ldac(dac->gpio_ldac);589 590 return ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B, mask);591}592 593static irqreturn_t ad3552r_trigger_handler(int irq, void *p)594{595 struct iio_poll_func *pf = p;596 struct iio_dev *indio_dev = pf->indio_dev;597 struct iio_buffer *buf = indio_dev->buffer;598 struct ad3552r_desc *dac = iio_priv(indio_dev);599 /* Maximum size of a scan */600 u8 buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE];601 int err;602 603 memset(buff, 0, sizeof(buff));604 err = iio_pop_from_buffer(buf, buff);605 if (err)606 goto end;607 608 mutex_lock(&dac->lock);609 ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff);610 mutex_unlock(&dac->lock);611end:612 iio_trigger_notify_done(indio_dev->trig);613 614 return IRQ_HANDLED;615}616 617static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac)618{619 const u16 val1 = AD3552R_SCRATCH_PAD_TEST_VAL1;620 const u16 val2 = AD3552R_SCRATCH_PAD_TEST_VAL2;621 u16 val;622 int err;623 624 err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val1);625 if (err < 0)626 return err;627 628 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);629 if (err < 0)630 return err;631 632 if (val1 != val)633 return -ENODEV;634 635 err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val2);636 if (err < 0)637 return err;638 639 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);640 if (err < 0)641 return err;642 643 if (val2 != val)644 return -ENODEV;645 646 return 0;647}648 649struct reg_addr_pool {650 struct ad3552r_desc *dac;651 u8 addr;652};653 654static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)655{656 int err;657 u16 val;658 659 err = ad3552r_read_reg(addr->dac, addr->addr, &val);660 if (err)661 return err;662 663 return val;664}665 666static int ad3552r_reset(struct ad3552r_desc *dac)667{668 struct reg_addr_pool addr;669 int ret;670 int val;671 672 dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",673 GPIOD_OUT_LOW);674 if (IS_ERR(dac->gpio_reset))675 return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset),676 "Error while getting gpio reset");677 678 if (dac->gpio_reset) {679 /* Perform hardware reset */680 usleep_range(10, 20);681 gpiod_set_value_cansleep(dac->gpio_reset, 1);682 } else {683 /* Perform software reset if no GPIO provided */684 ret = ad3552r_update_reg_field(dac,685 AD3552R_REG_ADDR_INTERFACE_CONFIG_A,686 AD3552R_MASK_SOFTWARE_RESET,687 AD3552R_MASK_SOFTWARE_RESET);688 if (ret < 0)689 return ret;690 691 }692 693 addr.dac = dac;694 addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B;695 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,696 val == AD3552R_DEFAULT_CONFIG_B_VALUE ||697 val < 0,698 5000, 50000);699 if (val < 0)700 ret = val;701 if (ret) {702 dev_err(&dac->spi->dev, "Error while resetting");703 return ret;704 }705 706 ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,707 !(val & AD3552R_MASK_INTERFACE_NOT_READY) ||708 val < 0,709 5000, 50000);710 if (val < 0)711 ret = val;712 if (ret) {713 dev_err(&dac->spi->dev, "Error while resetting");714 return ret;715 }716 717 return ad3552r_update_reg_field(dac,718 addr_mask_map[AD3552R_ADDR_ASCENSION][0],719 addr_mask_map[AD3552R_ADDR_ASCENSION][1],720 val);721}722 723static void ad3552r_get_custom_range(struct ad3552r_desc *dac, s32 i, s32 *v_min,724 s32 *v_max)725{726 s64 vref, tmp, common, offset, gn, gp;727 /*728 * From datasheet formula (In Volts):729 * Vmin = 2.5 + [(GainN + Offset / 1024) * 2.5 * Rfb * 1.03]730 * Vmax = 2.5 - [(GainP + Offset / 1024) * 2.5 * Rfb * 1.03]731 * Calculus are converted to milivolts732 */733 vref = 2500;734 /* 2.5 * 1.03 * 1000 (To mV) */735 common = 2575 * dac->ch_data[i].rfb;736 offset = dac->ch_data[i].gain_offset;737 738 gn = gains_scaling_table[dac->ch_data[i].n];739 tmp = (1024 * gn + AD3552R_GAIN_SCALE * offset) * common;740 tmp = div_s64(tmp, 1024 * AD3552R_GAIN_SCALE);741 *v_max = vref + tmp;742 743 gp = gains_scaling_table[dac->ch_data[i].p];744 tmp = (1024 * gp - AD3552R_GAIN_SCALE * offset) * common;745 tmp = div_s64(tmp, 1024 * AD3552R_GAIN_SCALE);746 *v_min = vref - tmp;747}748 749static void ad3552r_calc_gain_and_offset(struct ad3552r_desc *dac, s32 ch)750{751 s32 idx, v_max, v_min, span, rem;752 s64 tmp;753 754 if (dac->ch_data[ch].range_override) {755 ad3552r_get_custom_range(dac, ch, &v_min, &v_max);756 } else {757 /* Normal range */758 idx = dac->ch_data[ch].range;759 v_min = dac->model_data->ranges_table[idx][0];760 v_max = dac->model_data->ranges_table[idx][1];761 }762 763 /*764 * From datasheet formula:765 * Vout = Span * (D / 65536) + Vmin766 * Converted to scale and offset:767 * Scale = Span / 65536768 * Offset = 65536 * Vmin / Span769 *770 * Reminders are in micros in order to be printed as771 * IIO_VAL_INT_PLUS_MICRO772 */773 span = v_max - v_min;774 dac->ch_data[ch].scale_int = div_s64_rem(span, 65536, &rem);775 /* Do operations in microvolts */776 dac->ch_data[ch].scale_dec = DIV_ROUND_CLOSEST((s64)rem * 1000000,777 65536);778 779 dac->ch_data[ch].offset_int = div_s64_rem(v_min * 65536, span, &rem);780 tmp = (s64)rem * 1000000;781 dac->ch_data[ch].offset_dec = div_s64(tmp, span);782}783 784static int ad3552r_find_range(const struct ad3552r_model_data *model_data,785 s32 *vals)786{787 int i;788 789 for (i = 0; i < model_data->num_ranges; i++)790 if (vals[0] == model_data->ranges_table[i][0] * 1000 &&791 vals[1] == model_data->ranges_table[i][1] * 1000)792 return i;793 794 return -EINVAL;795}796 797static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac,798 struct fwnode_handle *child,799 u32 ch)800{801 struct device *dev = &dac->spi->dev;802 u32 val;803 int err;804 u8 addr;805 u16 reg = 0, offset;806 807 struct fwnode_handle *gain_child __free(fwnode_handle)808 = fwnode_get_named_child_node(child,809 "custom-output-range-config");810 if (!gain_child)811 return dev_err_probe(dev, -EINVAL,812 "mandatory custom-output-range-config property missing\n");813 814 dac->ch_data[ch].range_override = 1;815 reg |= ad3552r_field_prep(1, AD3552R_MASK_CH_RANGE_OVERRIDE);816 817 err = fwnode_property_read_u32(gain_child, "adi,gain-scaling-p", &val);818 if (err)819 return dev_err_probe(dev, err,820 "mandatory adi,gain-scaling-p property missing\n");821 reg |= ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_P);822 dac->ch_data[ch].p = val;823 824 err = fwnode_property_read_u32(gain_child, "adi,gain-scaling-n", &val);825 if (err)826 return dev_err_probe(dev, err,827 "mandatory adi,gain-scaling-n property missing\n");828 reg |= ad3552r_field_prep(val, AD3552R_MASK_CH_GAIN_SCALING_N);829 dac->ch_data[ch].n = val;830 831 err = fwnode_property_read_u32(gain_child, "adi,rfb-ohms", &val);832 if (err)833 return dev_err_probe(dev, err,834 "mandatory adi,rfb-ohms property missing\n");835 dac->ch_data[ch].rfb = val;836 837 err = fwnode_property_read_u32(gain_child, "adi,gain-offset", &val);838 if (err)839 return dev_err_probe(dev, err,840 "mandatory adi,gain-offset property missing\n");841 dac->ch_data[ch].gain_offset = val;842 843 offset = abs((s32)val);844 reg |= ad3552r_field_prep((offset >> 8), AD3552R_MASK_CH_OFFSET_BIT_8);845 846 reg |= ad3552r_field_prep((s32)val < 0, AD3552R_MASK_CH_OFFSET_POLARITY);847 addr = AD3552R_REG_ADDR_CH_GAIN(ch);848 err = ad3552r_write_reg(dac, addr,849 offset & AD3552R_MASK_CH_OFFSET_BITS_0_7);850 if (err)851 return dev_err_probe(dev, err, "Error writing register\n");852 853 err = ad3552r_write_reg(dac, addr, reg);854 if (err)855 return dev_err_probe(dev, err, "Error writing register\n");856 857 return 0;858}859 860static int ad3552r_configure_device(struct ad3552r_desc *dac)861{862 struct device *dev = &dac->spi->dev;863 int err, cnt = 0, voltage, delta = 100000;864 u32 vals[2], val, ch;865 866 dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH);867 if (IS_ERR(dac->gpio_ldac))868 return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac),869 "Error getting gpio ldac");870 871 voltage = devm_regulator_get_enable_read_voltage(dev, "vref");872 if (voltage < 0 && voltage != -ENODEV)873 return dev_err_probe(dev, voltage, "Error getting vref voltage\n");874 875 if (voltage == -ENODEV) {876 if (device_property_read_bool(dev, "adi,vref-out-en"))877 val = AD3552R_INTERNAL_VREF_PIN_2P5V;878 else879 val = AD3552R_INTERNAL_VREF_PIN_FLOATING;880 } else {881 if (voltage > 2500000 + delta || voltage < 2500000 - delta) {882 dev_warn(dev, "vref-supply must be 2.5V");883 return -EINVAL;884 }885 val = AD3552R_EXTERNAL_VREF_PIN_INPUT;886 }887 888 err = ad3552r_update_reg_field(dac,889 addr_mask_map[AD3552R_VREF_SELECT][0],890 addr_mask_map[AD3552R_VREF_SELECT][1],891 val);892 if (err)893 return err;894 895 err = device_property_read_u32(dev, "adi,sdo-drive-strength", &val);896 if (!err) {897 if (val > 3) {898 dev_err(dev, "adi,sdo-drive-strength must be less than 4\n");899 return -EINVAL;900 }901 902 err = ad3552r_update_reg_field(dac,903 addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][0],904 addr_mask_map[AD3552R_SDO_DRIVE_STRENGTH][1],905 val);906 if (err)907 return err;908 }909 910 dac->num_ch = device_get_child_node_count(dev);911 if (!dac->num_ch) {912 dev_err(dev, "No channels defined\n");913 return -ENODEV;914 }915 916 device_for_each_child_node_scoped(dev, child) {917 err = fwnode_property_read_u32(child, "reg", &ch);918 if (err)919 return dev_err_probe(dev, err,920 "mandatory reg property missing\n");921 if (ch >= dac->model_data->num_hw_channels)922 return dev_err_probe(dev, -EINVAL,923 "reg must be less than %d\n",924 dac->model_data->num_hw_channels);925 926 if (fwnode_property_present(child, "adi,output-range-microvolt")) {927 err = fwnode_property_read_u32_array(child,928 "adi,output-range-microvolt",929 vals,930 2);931 if (err)932 return dev_err_probe(dev, err,933 "adi,output-range-microvolt property could not be parsed\n");934 935 err = ad3552r_find_range(dac->model_data, vals);936 if (err < 0)937 return dev_err_probe(dev, err,938 "Invalid adi,output-range-microvolt value\n");939 940 val = err;941 err = ad3552r_set_ch_value(dac,942 AD3552R_CH_OUTPUT_RANGE_SEL,943 ch, val);944 if (err)945 return err;946 947 dac->ch_data[ch].range = val;948 } else if (dac->model_data->requires_output_range) {949 return dev_err_probe(dev, -EINVAL,950 "adi,output-range-microvolt is required for %s\n",951 dac->model_data->model_name);952 } else {953 err = ad3552r_configure_custom_gain(dac, child, ch);954 if (err)955 return err;956 }957 958 ad3552r_calc_gain_and_offset(dac, ch);959 dac->enabled_ch |= BIT(ch);960 961 err = ad3552r_set_ch_value(dac, AD3552R_CH_SELECT, ch, 1);962 if (err < 0)963 return err;964 965 dac->channels[cnt] = AD3552R_CH_DAC(ch);966 ++cnt;967 968 }969 970 /* Disable unused channels */971 for_each_clear_bit(ch, &dac->enabled_ch,972 dac->model_data->num_hw_channels) {973 err = ad3552r_set_ch_value(dac, AD3552R_CH_AMPLIFIER_POWERDOWN,974 ch, 1);975 if (err)976 return err;977 }978 979 dac->num_ch = cnt;980 981 return 0;982}983 984static int ad3552r_init(struct ad3552r_desc *dac)985{986 int err;987 u16 val, id;988 989 err = ad3552r_reset(dac);990 if (err) {991 dev_err(&dac->spi->dev, "Reset failed\n");992 return err;993 }994 995 err = ad3552r_check_scratch_pad(dac);996 if (err) {997 dev_err(&dac->spi->dev, "Scratch pad test failed\n");998 return err;999 }1000 1001 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val);1002 if (err) {1003 dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_L\n");1004 return err;1005 }1006 1007 id = val;1008 err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val);1009 if (err) {1010 dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_H\n");1011 return err;1012 }1013 1014 id |= val << 8;1015 if (id != dac->model_data->chip_id) {1016 dev_err(&dac->spi->dev, "Product id not matching\n");1017 return -ENODEV;1018 }1019 1020 return ad3552r_configure_device(dac);1021}1022 1023static int ad3552r_probe(struct spi_device *spi)1024{1025 struct ad3552r_desc *dac;1026 struct iio_dev *indio_dev;1027 int err;1028 1029 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dac));1030 if (!indio_dev)1031 return -ENOMEM;1032 1033 dac = iio_priv(indio_dev);1034 dac->spi = spi;1035 dac->model_data = spi_get_device_match_data(spi);1036 if (!dac->model_data)1037 return -EINVAL;1038 1039 mutex_init(&dac->lock);1040 1041 err = ad3552r_init(dac);1042 if (err)1043 return err;1044 1045 /* Config triggered buffer device */1046 indio_dev->name = dac->model_data->model_name;1047 indio_dev->dev.parent = &spi->dev;1048 indio_dev->info = &ad3552r_iio_info;1049 indio_dev->num_channels = dac->num_ch;1050 indio_dev->channels = dac->channels;1051 indio_dev->modes = INDIO_DIRECT_MODE;1052 1053 err = devm_iio_triggered_buffer_setup_ext(&indio_dev->dev, indio_dev, NULL,1054 &ad3552r_trigger_handler,1055 IIO_BUFFER_DIRECTION_OUT,1056 NULL,1057 NULL);1058 if (err)1059 return err;1060 1061 return devm_iio_device_register(&spi->dev, indio_dev);1062}1063 1064static const struct ad3552r_model_data ad3541r_model_data = {1065 .model_name = "ad3541r",1066 .chip_id = AD3541R_ID,1067 .num_hw_channels = 1,1068 .ranges_table = ad3542r_ch_ranges,1069 .num_ranges = ARRAY_SIZE(ad3542r_ch_ranges),1070 .requires_output_range = true,1071};1072 1073static const struct ad3552r_model_data ad3542r_model_data = {1074 .model_name = "ad3542r",1075 .chip_id = AD3542R_ID,1076 .num_hw_channels = 2,1077 .ranges_table = ad3542r_ch_ranges,1078 .num_ranges = ARRAY_SIZE(ad3542r_ch_ranges),1079 .requires_output_range = true,1080};1081 1082static const struct ad3552r_model_data ad3551r_model_data = {1083 .model_name = "ad3551r",1084 .chip_id = AD3551R_ID,1085 .num_hw_channels = 1,1086 .ranges_table = ad3552r_ch_ranges,1087 .num_ranges = ARRAY_SIZE(ad3552r_ch_ranges),1088 .requires_output_range = false,1089};1090 1091static const struct ad3552r_model_data ad3552r_model_data = {1092 .model_name = "ad3552r",1093 .chip_id = AD3552R_ID,1094 .num_hw_channels = 2,1095 .ranges_table = ad3552r_ch_ranges,1096 .num_ranges = ARRAY_SIZE(ad3552r_ch_ranges),1097 .requires_output_range = false,1098};1099 1100static const struct spi_device_id ad3552r_id[] = {1101 {1102 .name = "ad3541r",1103 .driver_data = (kernel_ulong_t)&ad3541r_model_data1104 },1105 {1106 .name = "ad3542r",1107 .driver_data = (kernel_ulong_t)&ad3542r_model_data1108 },1109 {1110 .name = "ad3551r",1111 .driver_data = (kernel_ulong_t)&ad3551r_model_data1112 },1113 {1114 .name = "ad3552r",1115 .driver_data = (kernel_ulong_t)&ad3552r_model_data1116 },1117 { }1118};1119MODULE_DEVICE_TABLE(spi, ad3552r_id);1120 1121static const struct of_device_id ad3552r_of_match[] = {1122 { .compatible = "adi,ad3541r", .data = &ad3541r_model_data },1123 { .compatible = "adi,ad3542r", .data = &ad3542r_model_data },1124 { .compatible = "adi,ad3551r", .data = &ad3551r_model_data },1125 { .compatible = "adi,ad3552r", .data = &ad3552r_model_data },1126 { }1127};1128MODULE_DEVICE_TABLE(of, ad3552r_of_match);1129 1130static struct spi_driver ad3552r_driver = {1131 .driver = {1132 .name = "ad3552r",1133 .of_match_table = ad3552r_of_match,1134 },1135 .probe = ad3552r_probe,1136 .id_table = ad3552r_id1137};1138module_spi_driver(ad3552r_driver);1139 1140MODULE_AUTHOR("Mihail Chindris <mihail.chindris@analog.com>");1141MODULE_DESCRIPTION("Analog Device AD3552R DAC");1142MODULE_LICENSE("GPL v2");1143