1051 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * AD9523 SPI Low Jitter Clock Generator4 *5 * Copyright 2012 Analog Devices Inc.6 */7 8#include <linux/device.h>9#include <linux/kernel.h>10#include <linux/slab.h>11#include <linux/sysfs.h>12#include <linux/spi/spi.h>13#include <linux/regulator/consumer.h>14#include <linux/gpio/consumer.h>15#include <linux/err.h>16#include <linux/module.h>17#include <linux/delay.h>18 19#include <linux/iio/iio.h>20#include <linux/iio/sysfs.h>21#include <linux/iio/frequency/ad9523.h>22 23#define AD9523_READ (1 << 15)24#define AD9523_WRITE (0 << 15)25#define AD9523_CNT(x) (((x) - 1) << 13)26#define AD9523_ADDR(x) ((x) & 0xFFF)27 28#define AD9523_R1B (1 << 16)29#define AD9523_R2B (2 << 16)30#define AD9523_R3B (3 << 16)31#define AD9523_TRANSF_LEN(x) ((x) >> 16)32 33#define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0)34#define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2)35#define AD9523_PART_REGISTER (AD9523_R1B | 0x3)36#define AD9523_READBACK_CTRL (AD9523_R1B | 0x4)37 38#define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6)39 40#define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11)41#define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13)42#define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14)43#define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17)44#define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19)45#define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A)46#define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B)47#define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C)48#define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D)49 50#define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0)51#define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1)52#define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2)53#define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3)54#define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4)55#define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6)56#define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7)57 58#define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch))59 60#define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA)61#define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)62 63#define AD9523_READBACK_0 (AD9523_R1B | 0x22C)64#define AD9523_READBACK_1 (AD9523_R1B | 0x22D)65 66#define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232)67#define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233)68#define AD9523_IO_UPDATE (AD9523_R1B | 0x234)69 70#define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00)71#define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01)72#define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02)73#define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03)74 75/* AD9523_SERIAL_PORT_CONFIG */76 77#define AD9523_SER_CONF_SDO_ACTIVE (1 << 7)78#define AD9523_SER_CONF_SOFT_RESET (1 << 5)79 80/* AD9523_READBACK_CTRL */81#define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)82 83/* AD9523_PLL1_CHARGE_PUMP_CTRL */84#define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F)85#define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)86#define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)87#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)88#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)89#define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)90#define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10)91#define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10)92#define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10)93#define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10)94 95/* AD9523_PLL1_INPUT_RECEIVERS_CTRL */96#define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7)97#define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6)98#define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5)99#define AD9523_PLL1_REFB_RCV_EN (1 << 4)100#define AD9523_PLL1_REFA_RCV_EN (1 << 3)101#define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)102#define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)103#define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0)104 105/* AD9523_PLL1_REF_CTRL */106#define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7)107#define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6)108#define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5)109#define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5)110#define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4)111#define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3)112#define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2)113#define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1)114#define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0)115 116/* AD9523_PLL1_MISC_CTRL */117#define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7)118#define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6)119#define AD9523_PLL1_REF_MODE(x) ((x) << 2)120#define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1)121#define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)122 123/* AD9523_PLL1_LOOP_FILTER_CTRL */124#define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF)125 126/* AD9523_PLL2_CHARGE_PUMP */127#define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500)128 129/* AD9523_PLL2_FEEDBACK_DIVIDER_AB */130#define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6)131#define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0)132#define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a))133 134/* AD9523_PLL2_CTRL */135#define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)136#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)137#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)138#define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)139#define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2)140#define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2)141#define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)142#define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1)143#define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4)144#define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5)145#define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)146 147/* AD9523_PLL2_VCO_CTRL */148#define AD9523_PLL2_VCO_CALIBRATE (1 << 1)149#define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2)150#define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3)151#define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4)152 153/* AD9523_PLL2_VCO_DIVIDER */154#define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0)155#define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4)156#define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2)157#define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6)158 159/* AD9523_PLL2_LOOP_FILTER_CTRL */160#define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0)161#define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)162#define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6)163#define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)164 165/* AD9523_PLL2_R2_DIVIDER */166#define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0)167 168/* AD9523_CHANNEL_CLOCK_DIST */169#define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18)170#define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F)171#define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8)172#define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1)173#define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)174#define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6)175#define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5)176#define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4)177#define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0)178 179/* AD9523_PLL1_OUTPUT_CTRL */180#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7)181#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)182#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5)183#define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4)184#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0)185#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0)186#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0)187#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0)188#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0)189 190/* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */191#define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)192#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)193#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)194#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)195#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3)196#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2)197#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1)198#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0)199 200/* AD9523_READBACK_0 */201#define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)202#define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6)203#define AD9523_READBACK_0_STAT_VCXO (1 << 5)204#define AD9523_READBACK_0_STAT_REF_TEST (1 << 4)205#define AD9523_READBACK_0_STAT_REFB (1 << 3)206#define AD9523_READBACK_0_STAT_REFA (1 << 2)207#define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1)208#define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0)209 210/* AD9523_READBACK_1 */211#define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3)212#define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2)213#define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0)214 215/* AD9523_STATUS_SIGNALS */216#define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16)217#define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302)218/* AD9523_POWER_DOWN_CTRL */219#define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2)220#define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1)221#define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0)222 223/* AD9523_IO_UPDATE */224#define AD9523_IO_UPDATE_EN (1 << 0)225 226/* AD9523_EEPROM_DATA_XFER_STATUS */227#define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0)228 229/* AD9523_EEPROM_ERROR_READBACK */230#define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0)231 232/* AD9523_EEPROM_CTRL1 */233#define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1)234#define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0)235 236/* AD9523_EEPROM_CTRL2 */237#define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0)238 239#define AD9523_NUM_CHAN 14240#define AD9523_NUM_CHAN_ALT_CLK_SRC 10241 242/* Helpers to avoid excess line breaks */243#define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b)244#define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)245 246enum {247 AD9523_STAT_PLL1_LD,248 AD9523_STAT_PLL2_LD,249 AD9523_STAT_REFA,250 AD9523_STAT_REFB,251 AD9523_STAT_REF_TEST,252 AD9523_STAT_VCXO,253 AD9523_STAT_PLL2_FB_CLK,254 AD9523_STAT_PLL2_REF_CLK,255 AD9523_SYNC,256 AD9523_EEPROM,257};258 259enum {260 AD9523_VCO1,261 AD9523_VCO2,262 AD9523_VCXO,263 AD9523_NUM_CLK_SRC,264};265 266struct ad9523_state {267 struct spi_device *spi;268 struct ad9523_platform_data *pdata;269 struct iio_chan_spec ad9523_channels[AD9523_NUM_CHAN];270 struct gpio_desc *pwrdown_gpio;271 struct gpio_desc *reset_gpio;272 struct gpio_desc *sync_gpio;273 274 unsigned long vcxo_freq;275 unsigned long vco_freq;276 unsigned long vco_out_freq[AD9523_NUM_CLK_SRC];277 unsigned char vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC];278 279 /*280 * Lock for accessing device registers. Some operations require281 * multiple consecutive R/W operations, during which the device282 * shouldn't be interrupted. The buffers are also shared across283 * all operations so need to be protected on stand alone reads and284 * writes.285 */286 struct mutex lock;287 288 /*289 * DMA (thus cache coherency maintenance) may require that290 * transfer buffers live in their own cache lines.291 */292 union {293 __be32 d32;294 u8 d8[4];295 } data[2] __aligned(IIO_DMA_MINALIGN);296};297 298static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr)299{300 struct ad9523_state *st = iio_priv(indio_dev);301 int ret;302 303 /* We encode the register size 1..3 bytes into the register address.304 * On transfer we get the size from the register datum, and make sure305 * the result is properly aligned.306 */307 308 struct spi_transfer t[] = {309 {310 .tx_buf = &st->data[0].d8[2],311 .len = 2,312 }, {313 .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],314 .len = AD9523_TRANSF_LEN(addr),315 },316 };317 318 st->data[0].d32 = cpu_to_be32(AD9523_READ |319 AD9523_CNT(AD9523_TRANSF_LEN(addr)) |320 AD9523_ADDR(addr));321 322 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));323 if (ret < 0)324 dev_err(&indio_dev->dev, "read failed (%d)", ret);325 else326 ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >>327 (8 * (3 - AD9523_TRANSF_LEN(addr))));328 329 return ret;330};331 332static int ad9523_write(struct iio_dev *indio_dev,333 unsigned int addr, unsigned int val)334{335 struct ad9523_state *st = iio_priv(indio_dev);336 int ret;337 struct spi_transfer t[] = {338 {339 .tx_buf = &st->data[0].d8[2],340 .len = 2,341 }, {342 .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],343 .len = AD9523_TRANSF_LEN(addr),344 },345 };346 347 st->data[0].d32 = cpu_to_be32(AD9523_WRITE |348 AD9523_CNT(AD9523_TRANSF_LEN(addr)) |349 AD9523_ADDR(addr));350 st->data[1].d32 = cpu_to_be32(val);351 352 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));353 354 if (ret < 0)355 dev_err(&indio_dev->dev, "write failed (%d)", ret);356 357 return ret;358}359 360static int ad9523_io_update(struct iio_dev *indio_dev)361{362 return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN);363}364 365static int ad9523_vco_out_map(struct iio_dev *indio_dev,366 unsigned int ch, unsigned int out)367{368 struct ad9523_state *st = iio_priv(indio_dev);369 int ret;370 unsigned int mask;371 372 switch (ch) {373 case 0 ... 3:374 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);375 if (ret < 0)376 break;377 mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch;378 if (out) {379 ret |= mask;380 out = 2;381 } else {382 ret &= ~mask;383 }384 ret = ad9523_write(indio_dev,385 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);386 break;387 case 4 ... 6:388 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL);389 if (ret < 0)390 break;391 mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4);392 if (out)393 ret |= mask;394 else395 ret &= ~mask;396 ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret);397 break;398 case 7 ... 9:399 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);400 if (ret < 0)401 break;402 mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7);403 if (out)404 ret |= mask;405 else406 ret &= ~mask;407 ret = ad9523_write(indio_dev,408 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);409 break;410 default:411 return 0;412 }413 414 st->vco_out_map[ch] = out;415 416 return ret;417}418 419static int ad9523_set_clock_provider(struct iio_dev *indio_dev,420 unsigned int ch, unsigned long freq)421{422 struct ad9523_state *st = iio_priv(indio_dev);423 long tmp1, tmp2;424 bool use_alt_clk_src;425 426 switch (ch) {427 case 0 ... 3:428 use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]);429 break;430 case 4 ... 9:431 tmp1 = st->vco_out_freq[AD9523_VCO1] / freq;432 tmp2 = st->vco_out_freq[AD9523_VCO2] / freq;433 tmp1 *= freq;434 tmp2 *= freq;435 use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq));436 break;437 default:438 /* Ch 10..14: No action required, return success */439 return 0;440 }441 442 return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src);443}444 445static int ad9523_store_eeprom(struct iio_dev *indio_dev)446{447 int ret, tmp;448 449 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1,450 AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS);451 if (ret < 0)452 return ret;453 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2,454 AD9523_EEPROM_CTRL2_REG2EEPROM);455 if (ret < 0)456 return ret;457 458 tmp = 4;459 do {460 msleep(20);461 ret = ad9523_read(indio_dev,462 AD9523_EEPROM_DATA_XFER_STATUS);463 if (ret < 0)464 return ret;465 } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--);466 467 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0);468 if (ret < 0)469 return ret;470 471 ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK);472 if (ret < 0)473 return ret;474 475 if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) {476 dev_err(&indio_dev->dev, "Verify EEPROM failed");477 ret = -EIO;478 }479 480 return ret;481}482 483static int ad9523_sync(struct iio_dev *indio_dev)484{485 int ret, tmp;486 487 ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS);488 if (ret < 0)489 return ret;490 491 tmp = ret;492 tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;493 494 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);495 if (ret < 0)496 return ret;497 498 ad9523_io_update(indio_dev);499 tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;500 501 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);502 if (ret < 0)503 return ret;504 505 return ad9523_io_update(indio_dev);506}507 508static ssize_t ad9523_store(struct device *dev,509 struct device_attribute *attr,510 const char *buf, size_t len)511{512 struct iio_dev *indio_dev = dev_to_iio_dev(dev);513 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);514 struct ad9523_state *st = iio_priv(indio_dev);515 bool state;516 int ret;517 518 ret = kstrtobool(buf, &state);519 if (ret < 0)520 return ret;521 522 if (!state)523 return len;524 525 mutex_lock(&st->lock);526 switch ((u32)this_attr->address) {527 case AD9523_SYNC:528 ret = ad9523_sync(indio_dev);529 break;530 case AD9523_EEPROM:531 ret = ad9523_store_eeprom(indio_dev);532 break;533 default:534 ret = -ENODEV;535 }536 mutex_unlock(&st->lock);537 538 return ret ? ret : len;539}540 541static ssize_t ad9523_show(struct device *dev,542 struct device_attribute *attr,543 char *buf)544{545 struct iio_dev *indio_dev = dev_to_iio_dev(dev);546 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);547 struct ad9523_state *st = iio_priv(indio_dev);548 int ret;549 550 mutex_lock(&st->lock);551 ret = ad9523_read(indio_dev, AD9523_READBACK_0);552 if (ret >= 0) {553 ret = sysfs_emit(buf, "%d\n", !!(ret & (1 <<554 (u32)this_attr->address)));555 }556 mutex_unlock(&st->lock);557 558 return ret;559}560 561static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO,562 ad9523_show,563 NULL,564 AD9523_STAT_PLL1_LD);565 566static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO,567 ad9523_show,568 NULL,569 AD9523_STAT_PLL2_LD);570 571static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO,572 ad9523_show,573 NULL,574 AD9523_STAT_REFA);575 576static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO,577 ad9523_show,578 NULL,579 AD9523_STAT_REFB);580 581static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO,582 ad9523_show,583 NULL,584 AD9523_STAT_REF_TEST);585 586static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO,587 ad9523_show,588 NULL,589 AD9523_STAT_VCXO);590 591static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO,592 ad9523_show,593 NULL,594 AD9523_STAT_PLL2_FB_CLK);595 596static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO,597 ad9523_show,598 NULL,599 AD9523_STAT_PLL2_REF_CLK);600 601static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR,602 NULL,603 ad9523_store,604 AD9523_SYNC);605 606static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR,607 NULL,608 ad9523_store,609 AD9523_EEPROM);610 611static struct attribute *ad9523_attributes[] = {612 &iio_dev_attr_sync_dividers.dev_attr.attr,613 &iio_dev_attr_store_eeprom.dev_attr.attr,614 &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr,615 &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr,616 &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr,617 &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr,618 &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr,619 &iio_dev_attr_vcxo_clk_present.dev_attr.attr,620 &iio_dev_attr_pll1_locked.dev_attr.attr,621 &iio_dev_attr_pll2_locked.dev_attr.attr,622 NULL,623};624 625static const struct attribute_group ad9523_attribute_group = {626 .attrs = ad9523_attributes,627};628 629static int ad9523_read_raw(struct iio_dev *indio_dev,630 struct iio_chan_spec const *chan,631 int *val,632 int *val2,633 long m)634{635 struct ad9523_state *st = iio_priv(indio_dev);636 unsigned int code;637 int ret;638 639 mutex_lock(&st->lock);640 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));641 mutex_unlock(&st->lock);642 643 if (ret < 0)644 return ret;645 646 switch (m) {647 case IIO_CHAN_INFO_RAW:648 *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN);649 return IIO_VAL_INT;650 case IIO_CHAN_INFO_FREQUENCY:651 *val = st->vco_out_freq[st->vco_out_map[chan->channel]] /652 AD9523_CLK_DIST_DIV_REV(ret);653 return IIO_VAL_INT;654 case IIO_CHAN_INFO_PHASE:655 code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) /656 AD9523_CLK_DIST_DIV_REV(ret);657 *val = code / 1000000;658 *val2 = code % 1000000;659 return IIO_VAL_INT_PLUS_MICRO;660 default:661 return -EINVAL;662 }663};664 665static int ad9523_write_raw(struct iio_dev *indio_dev,666 struct iio_chan_spec const *chan,667 int val,668 int val2,669 long mask)670{671 struct ad9523_state *st = iio_priv(indio_dev);672 unsigned int reg;673 int ret, tmp, code;674 675 mutex_lock(&st->lock);676 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));677 if (ret < 0)678 goto out;679 680 reg = ret;681 682 switch (mask) {683 case IIO_CHAN_INFO_RAW:684 if (val)685 reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN;686 else687 reg |= AD9523_CLK_DIST_PWR_DOWN_EN;688 break;689 case IIO_CHAN_INFO_FREQUENCY:690 if (val <= 0) {691 ret = -EINVAL;692 goto out;693 }694 ret = ad9523_set_clock_provider(indio_dev, chan->channel, val);695 if (ret < 0)696 goto out;697 tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val;698 tmp = clamp(tmp, 1, 1024);699 reg &= ~(0x3FF << 8);700 reg |= AD9523_CLK_DIST_DIV(tmp);701 break;702 case IIO_CHAN_INFO_PHASE:703 code = val * 1000000 + val2 % 1000000;704 tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592;705 tmp = clamp(tmp, 0, 63);706 reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0);707 reg |= AD9523_CLK_DIST_DIV_PHASE(tmp);708 break;709 default:710 ret = -EINVAL;711 goto out;712 }713 714 ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel),715 reg);716 if (ret < 0)717 goto out;718 719 ad9523_io_update(indio_dev);720out:721 mutex_unlock(&st->lock);722 return ret;723}724 725static int ad9523_reg_access(struct iio_dev *indio_dev,726 unsigned int reg, unsigned int writeval,727 unsigned int *readval)728{729 struct ad9523_state *st = iio_priv(indio_dev);730 int ret;731 732 mutex_lock(&st->lock);733 if (readval == NULL) {734 ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);735 ad9523_io_update(indio_dev);736 } else {737 ret = ad9523_read(indio_dev, reg | AD9523_R1B);738 if (ret < 0)739 goto out_unlock;740 *readval = ret;741 ret = 0;742 }743 744out_unlock:745 mutex_unlock(&st->lock);746 747 return ret;748}749 750static const struct iio_info ad9523_info = {751 .read_raw = &ad9523_read_raw,752 .write_raw = &ad9523_write_raw,753 .debugfs_reg_access = &ad9523_reg_access,754 .attrs = &ad9523_attribute_group,755};756 757static int ad9523_setup(struct iio_dev *indio_dev)758{759 struct ad9523_state *st = iio_priv(indio_dev);760 struct ad9523_platform_data *pdata = st->pdata;761 struct ad9523_channel_spec *chan;762 unsigned long active_mask = 0;763 int ret, i;764 765 ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG,766 AD9523_SER_CONF_SOFT_RESET |767 (st->spi->mode & SPI_3WIRE ? 0 :768 AD9523_SER_CONF_SDO_ACTIVE));769 if (ret < 0)770 return ret;771 772 ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL,773 AD9523_READBACK_CTRL_READ_BUFFERED);774 if (ret < 0)775 return ret;776 777 ret = ad9523_io_update(indio_dev);778 if (ret < 0)779 return ret;780 781 /*782 * PLL1 Setup783 */784 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER,785 pdata->refa_r_div);786 if (ret < 0)787 return ret;788 789 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER,790 pdata->refb_r_div);791 if (ret < 0)792 return ret;793 794 ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER,795 pdata->pll1_feedback_div);796 if (ret < 0)797 return ret;798 799 ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL,800 AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata->801 pll1_charge_pump_current_nA) |802 AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL |803 AD9523_PLL1_BACKLASH_PW_MIN);804 if (ret < 0)805 return ret;806 807 ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,808 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) |809 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) |810 AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) |811 AD_IF(osc_in_cmos_neg_inp_en,812 AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) |813 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) |814 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN));815 if (ret < 0)816 return ret;817 818 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL,819 AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) |820 AD_IF(zd_in_cmos_neg_inp_en,821 AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) |822 AD_IF(zero_delay_mode_internal_en,823 AD9523_PLL1_ZERO_DELAY_MODE_INT) |824 AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) |825 AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) |826 AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN));827 if (ret < 0)828 return ret;829 830 ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL,831 AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN |832 AD9523_PLL1_REF_MODE(pdata->ref_mode));833 if (ret < 0)834 return ret;835 836 ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL,837 AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero));838 if (ret < 0)839 return ret;840 /*841 * PLL2 Setup842 */843 844 ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP,845 AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata->846 pll2_charge_pump_current_nA));847 if (ret < 0)848 return ret;849 850 ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,851 AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) |852 AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt));853 if (ret < 0)854 return ret;855 856 ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL,857 AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL |858 AD9523_PLL2_BACKLASH_CTRL_EN |859 AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN));860 if (ret < 0)861 return ret;862 863 st->vco_freq = div_u64((unsigned long long)pdata->vcxo_freq *864 (pdata->pll2_freq_doubler_en ? 2 : 1) *865 AD9523_PLL2_FB_NDIV(pdata->pll2_ndiv_a_cnt,866 pdata->pll2_ndiv_b_cnt),867 pdata->pll2_r2_div);868 869 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL,870 AD9523_PLL2_VCO_CALIBRATE);871 if (ret < 0)872 return ret;873 874 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,875 AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_div_m1) |876 AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_div_m2) |877 AD_IFE(pll2_vco_div_m1, 0,878 AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) |879 AD_IFE(pll2_vco_div_m2, 0,880 AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN));881 if (ret < 0)882 return ret;883 884 if (pdata->pll2_vco_div_m1)885 st->vco_out_freq[AD9523_VCO1] =886 st->vco_freq / pdata->pll2_vco_div_m1;887 888 if (pdata->pll2_vco_div_m2)889 st->vco_out_freq[AD9523_VCO2] =890 st->vco_freq / pdata->pll2_vco_div_m2;891 892 st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq;893 894 ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER,895 AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div));896 if (ret < 0)897 return ret;898 899 ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL,900 AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) |901 AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) |902 AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) |903 AD_IF(rzero_bypass_en,904 AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN));905 if (ret < 0)906 return ret;907 908 for (i = 0; i < pdata->num_channels; i++) {909 chan = &pdata->channels[i];910 if (chan->channel_num < AD9523_NUM_CHAN) {911 __set_bit(chan->channel_num, &active_mask);912 ret = ad9523_write(indio_dev,913 AD9523_CHANNEL_CLOCK_DIST(chan->channel_num),914 AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) |915 AD9523_CLK_DIST_DIV(chan->channel_divider) |916 AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) |917 (chan->sync_ignore_en ?918 AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) |919 (chan->divider_output_invert_en ?920 AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) |921 (chan->low_power_mode_en ?922 AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) |923 (chan->output_dis ?924 AD9523_CLK_DIST_PWR_DOWN_EN : 0));925 if (ret < 0)926 return ret;927 928 ret = ad9523_vco_out_map(indio_dev, chan->channel_num,929 chan->use_alt_clock_src);930 if (ret < 0)931 return ret;932 933 st->ad9523_channels[i].type = IIO_ALTVOLTAGE;934 st->ad9523_channels[i].output = 1;935 st->ad9523_channels[i].indexed = 1;936 st->ad9523_channels[i].channel = chan->channel_num;937 st->ad9523_channels[i].extend_name =938 chan->extended_name;939 st->ad9523_channels[i].info_mask_separate =940 BIT(IIO_CHAN_INFO_RAW) |941 BIT(IIO_CHAN_INFO_PHASE) |942 BIT(IIO_CHAN_INFO_FREQUENCY);943 }944 }945 946 for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN) {947 ret = ad9523_write(indio_dev,948 AD9523_CHANNEL_CLOCK_DIST(i),949 AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) |950 AD9523_CLK_DIST_PWR_DOWN_EN);951 if (ret < 0)952 return ret;953 }954 955 ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0);956 if (ret < 0)957 return ret;958 959 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS,960 AD9523_STATUS_MONITOR_01_PLL12_LOCKED);961 if (ret < 0)962 return ret;963 964 ret = ad9523_io_update(indio_dev);965 if (ret < 0)966 return ret;967 968 return 0;969}970 971static int ad9523_probe(struct spi_device *spi)972{973 struct ad9523_platform_data *pdata = spi->dev.platform_data;974 struct iio_dev *indio_dev;975 struct ad9523_state *st;976 int ret;977 978 if (!pdata) {979 dev_err(&spi->dev, "no platform data?\n");980 return -EINVAL;981 }982 983 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));984 if (indio_dev == NULL)985 return -ENOMEM;986 987 st = iio_priv(indio_dev);988 989 mutex_init(&st->lock);990 991 ret = devm_regulator_get_enable(&spi->dev, "vcc");992 if (ret)993 return ret;994 995 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",996 GPIOD_OUT_HIGH);997 if (IS_ERR(st->pwrdown_gpio))998 return PTR_ERR(st->pwrdown_gpio);999 1000 st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",1001 GPIOD_OUT_LOW);1002 if (IS_ERR(st->reset_gpio))1003 return PTR_ERR(st->reset_gpio);1004 1005 if (st->reset_gpio) {1006 udelay(1);1007 gpiod_direction_output(st->reset_gpio, 1);1008 }1009 1010 st->sync_gpio = devm_gpiod_get_optional(&spi->dev, "sync",1011 GPIOD_OUT_HIGH);1012 if (IS_ERR(st->sync_gpio))1013 return PTR_ERR(st->sync_gpio);1014 1015 spi_set_drvdata(spi, indio_dev);1016 st->spi = spi;1017 st->pdata = pdata;1018 1019 indio_dev->name = (pdata->name[0] != 0) ? pdata->name :1020 spi_get_device_id(spi)->name;1021 indio_dev->info = &ad9523_info;1022 indio_dev->modes = INDIO_DIRECT_MODE;1023 indio_dev->channels = st->ad9523_channels;1024 indio_dev->num_channels = pdata->num_channels;1025 1026 ret = ad9523_setup(indio_dev);1027 if (ret < 0)1028 return ret;1029 1030 return devm_iio_device_register(&spi->dev, indio_dev);1031}1032 1033static const struct spi_device_id ad9523_id[] = {1034 {"ad9523-1", 9523},1035 {}1036};1037MODULE_DEVICE_TABLE(spi, ad9523_id);1038 1039static struct spi_driver ad9523_driver = {1040 .driver = {1041 .name = "ad9523",1042 },1043 .probe = ad9523_probe,1044 .id_table = ad9523_id,1045};1046module_spi_driver(ad9523_driver);1047 1048MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");1049MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL");1050MODULE_LICENSE("GPL v2");1051