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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * ADMV1013 driver4 *5 * Copyright 2021 Analog Devices Inc.6 */7 8#include <linux/bitfield.h>9#include <linux/bits.h>10#include <linux/clk.h>11#include <linux/device.h>12#include <linux/iio/iio.h>13#include <linux/module.h>14#include <linux/mod_devicetable.h>15#include <linux/notifier.h>16#include <linux/property.h>17#include <linux/regulator/consumer.h>18#include <linux/spi/spi.h>19#include <linux/units.h>20 21#include <linux/unaligned.h>22 23/* ADMV1013 Register Map */24#define ADMV1013_REG_SPI_CONTROL 0x0025#define ADMV1013_REG_ALARM 0x0126#define ADMV1013_REG_ALARM_MASKS 0x0227#define ADMV1013_REG_ENABLE 0x0328#define ADMV1013_REG_LO_AMP_I 0x0529#define ADMV1013_REG_LO_AMP_Q 0x0630#define ADMV1013_REG_OFFSET_ADJUST_I 0x0731#define ADMV1013_REG_OFFSET_ADJUST_Q 0x0832#define ADMV1013_REG_QUAD 0x0933#define ADMV1013_REG_VVA_TEMP_COMP 0x0A34 35/* ADMV1013_REG_SPI_CONTROL Map */36#define ADMV1013_PARITY_EN_MSK BIT(15)37#define ADMV1013_SPI_SOFT_RESET_MSK BIT(14)38#define ADMV1013_CHIP_ID_MSK GENMASK(11, 4)39#define ADMV1013_CHIP_ID 0xA40#define ADMV1013_REVISION_ID_MSK GENMASK(3, 0)41 42/* ADMV1013_REG_ALARM Map */43#define ADMV1013_PARITY_ERROR_MSK BIT(15)44#define ADMV1013_TOO_FEW_ERRORS_MSK BIT(14)45#define ADMV1013_TOO_MANY_ERRORS_MSK BIT(13)46#define ADMV1013_ADDRESS_RANGE_ERROR_MSK BIT(12)47 48/* ADMV1013_REG_ENABLE Map */49#define ADMV1013_VGA_PD_MSK BIT(15)50#define ADMV1013_MIXER_PD_MSK BIT(14)51#define ADMV1013_QUAD_PD_MSK GENMASK(13, 11)52#define ADMV1013_BG_PD_MSK BIT(10)53#define ADMV1013_MIXER_IF_EN_MSK BIT(7)54#define ADMV1013_DET_EN_MSK BIT(5)55 56/* ADMV1013_REG_LO_AMP Map */57#define ADMV1013_LOAMP_PH_ADJ_FINE_MSK GENMASK(13, 7)58#define ADMV1013_MIXER_VGATE_MSK GENMASK(6, 0)59 60/* ADMV1013_REG_OFFSET_ADJUST Map */61#define ADMV1013_MIXER_OFF_ADJ_P_MSK GENMASK(15, 9)62#define ADMV1013_MIXER_OFF_ADJ_N_MSK GENMASK(8, 2)63 64/* ADMV1013_REG_QUAD Map */65#define ADMV1013_QUAD_SE_MODE_MSK GENMASK(9, 6)66#define ADMV1013_QUAD_FILTERS_MSK GENMASK(3, 0)67 68/* ADMV1013_REG_VVA_TEMP_COMP Map */69#define ADMV1013_VVA_TEMP_COMP_MSK GENMASK(15, 0)70 71/* ADMV1013 Miscellaneous Defines */72#define ADMV1013_READ BIT(7)73#define ADMV1013_REG_ADDR_READ_MSK GENMASK(6, 1)74#define ADMV1013_REG_ADDR_WRITE_MSK GENMASK(22, 17)75#define ADMV1013_REG_DATA_MSK GENMASK(16, 1)76 77enum {78 ADMV1013_IQ_MODE,79 ADMV1013_IF_MODE80};81 82enum {83 ADMV1013_RFMOD_I_CALIBPHASE,84 ADMV1013_RFMOD_Q_CALIBPHASE,85};86 87enum {88 ADMV1013_SE_MODE_POS = 6,89 ADMV1013_SE_MODE_NEG = 9,90 ADMV1013_SE_MODE_DIFF = 1291};92 93struct admv1013_state {94 struct spi_device *spi;95 struct clk *clkin;96 /* Protect against concurrent accesses to the device and to data */97 struct mutex lock;98 struct notifier_block nb;99 unsigned int input_mode;100 unsigned int quad_se_mode;101 bool det_en;102 u8 data[3] __aligned(IIO_DMA_MINALIGN);103};104 105static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg,106 unsigned int *val)107{108 int ret;109 struct spi_transfer t = {0};110 111 st->data[0] = ADMV1013_READ | FIELD_PREP(ADMV1013_REG_ADDR_READ_MSK, reg);112 st->data[1] = 0x0;113 st->data[2] = 0x0;114 115 t.rx_buf = &st->data[0];116 t.tx_buf = &st->data[0];117 t.len = 3;118 119 ret = spi_sync_transfer(st->spi, &t, 1);120 if (ret)121 return ret;122 123 *val = FIELD_GET(ADMV1013_REG_DATA_MSK, get_unaligned_be24(&st->data[0]));124 125 return ret;126}127 128static int admv1013_spi_read(struct admv1013_state *st, unsigned int reg,129 unsigned int *val)130{131 int ret;132 133 mutex_lock(&st->lock);134 ret = __admv1013_spi_read(st, reg, val);135 mutex_unlock(&st->lock);136 137 return ret;138}139 140static int __admv1013_spi_write(struct admv1013_state *st,141 unsigned int reg,142 unsigned int val)143{144 put_unaligned_be24(FIELD_PREP(ADMV1013_REG_DATA_MSK, val) |145 FIELD_PREP(ADMV1013_REG_ADDR_WRITE_MSK, reg), &st->data[0]);146 147 return spi_write(st->spi, &st->data[0], 3);148}149 150static int admv1013_spi_write(struct admv1013_state *st, unsigned int reg,151 unsigned int val)152{153 int ret;154 155 mutex_lock(&st->lock);156 ret = __admv1013_spi_write(st, reg, val);157 mutex_unlock(&st->lock);158 159 return ret;160}161 162static int __admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,163 unsigned int mask, unsigned int val)164{165 int ret;166 unsigned int data, temp;167 168 ret = __admv1013_spi_read(st, reg, &data);169 if (ret)170 return ret;171 172 temp = (data & ~mask) | (val & mask);173 174 return __admv1013_spi_write(st, reg, temp);175}176 177static int admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,178 unsigned int mask, unsigned int val)179{180 int ret;181 182 mutex_lock(&st->lock);183 ret = __admv1013_spi_update_bits(st, reg, mask, val);184 mutex_unlock(&st->lock);185 186 return ret;187}188 189static int admv1013_read_raw(struct iio_dev *indio_dev,190 struct iio_chan_spec const *chan,191 int *val, int *val2, long info)192{193 struct admv1013_state *st = iio_priv(indio_dev);194 unsigned int data, addr;195 int ret;196 197 switch (info) {198 case IIO_CHAN_INFO_CALIBBIAS:199 switch (chan->channel) {200 case IIO_MOD_I:201 addr = ADMV1013_REG_OFFSET_ADJUST_I;202 break;203 case IIO_MOD_Q:204 addr = ADMV1013_REG_OFFSET_ADJUST_Q;205 break;206 default:207 return -EINVAL;208 }209 210 ret = admv1013_spi_read(st, addr, &data);211 if (ret)212 return ret;213 214 if (!chan->channel)215 *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_P_MSK, data);216 else217 *val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_N_MSK, data);218 219 return IIO_VAL_INT;220 default:221 return -EINVAL;222 }223}224 225static int admv1013_write_raw(struct iio_dev *indio_dev,226 struct iio_chan_spec const *chan,227 int val, int val2, long info)228{229 struct admv1013_state *st = iio_priv(indio_dev);230 unsigned int addr, data, msk;231 232 switch (info) {233 case IIO_CHAN_INFO_CALIBBIAS:234 switch (chan->channel2) {235 case IIO_MOD_I:236 addr = ADMV1013_REG_OFFSET_ADJUST_I;237 break;238 case IIO_MOD_Q:239 addr = ADMV1013_REG_OFFSET_ADJUST_Q;240 break;241 default:242 return -EINVAL;243 }244 245 if (!chan->channel) {246 msk = ADMV1013_MIXER_OFF_ADJ_P_MSK;247 data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_P_MSK, val);248 } else {249 msk = ADMV1013_MIXER_OFF_ADJ_N_MSK;250 data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_N_MSK, val);251 }252 253 return admv1013_spi_update_bits(st, addr, msk, data);254 default:255 return -EINVAL;256 }257}258 259static ssize_t admv1013_read(struct iio_dev *indio_dev,260 uintptr_t private,261 const struct iio_chan_spec *chan,262 char *buf)263{264 struct admv1013_state *st = iio_priv(indio_dev);265 unsigned int data, addr;266 int ret;267 268 switch ((u32)private) {269 case ADMV1013_RFMOD_I_CALIBPHASE:270 addr = ADMV1013_REG_LO_AMP_I;271 break;272 case ADMV1013_RFMOD_Q_CALIBPHASE:273 addr = ADMV1013_REG_LO_AMP_Q;274 break;275 default:276 return -EINVAL;277 }278 279 ret = admv1013_spi_read(st, addr, &data);280 if (ret)281 return ret;282 283 data = FIELD_GET(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);284 285 return sysfs_emit(buf, "%u\n", data);286}287 288static ssize_t admv1013_write(struct iio_dev *indio_dev,289 uintptr_t private,290 const struct iio_chan_spec *chan,291 const char *buf, size_t len)292{293 struct admv1013_state *st = iio_priv(indio_dev);294 unsigned int data;295 int ret;296 297 ret = kstrtou32(buf, 10, &data);298 if (ret)299 return ret;300 301 data = FIELD_PREP(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);302 303 switch ((u32)private) {304 case ADMV1013_RFMOD_I_CALIBPHASE:305 ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,306 ADMV1013_LOAMP_PH_ADJ_FINE_MSK,307 data);308 if (ret)309 return ret;310 break;311 case ADMV1013_RFMOD_Q_CALIBPHASE:312 ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_Q,313 ADMV1013_LOAMP_PH_ADJ_FINE_MSK,314 data);315 if (ret)316 return ret;317 break;318 default:319 return -EINVAL;320 }321 322 return ret ? ret : len;323}324 325static int admv1013_update_quad_filters(struct admv1013_state *st)326{327 unsigned int filt_raw;328 u64 rate = clk_get_rate(st->clkin);329 330 if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ))331 filt_raw = 15;332 else if (rate >= (5400 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ))333 filt_raw = 10;334 else if (rate >= (6600 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ))335 filt_raw = 5;336 else337 filt_raw = 0;338 339 return __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,340 ADMV1013_QUAD_FILTERS_MSK,341 FIELD_PREP(ADMV1013_QUAD_FILTERS_MSK, filt_raw));342}343 344static int admv1013_update_mixer_vgate(struct admv1013_state *st, int vcm)345{346 unsigned int mixer_vgate;347 348 if (vcm <= 1800000)349 mixer_vgate = (2389 * vcm / 1000000 + 8100) / 100;350 else if (vcm > 1800000 && vcm <= 2600000)351 mixer_vgate = (2375 * vcm / 1000000 + 125) / 100;352 else353 return -EINVAL;354 355 return __admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,356 ADMV1013_MIXER_VGATE_MSK,357 FIELD_PREP(ADMV1013_MIXER_VGATE_MSK, mixer_vgate));358}359 360static int admv1013_reg_access(struct iio_dev *indio_dev,361 unsigned int reg,362 unsigned int write_val,363 unsigned int *read_val)364{365 struct admv1013_state *st = iio_priv(indio_dev);366 367 if (read_val)368 return admv1013_spi_read(st, reg, read_val);369 else370 return admv1013_spi_write(st, reg, write_val);371}372 373static const struct iio_info admv1013_info = {374 .read_raw = admv1013_read_raw,375 .write_raw = admv1013_write_raw,376 .debugfs_reg_access = &admv1013_reg_access,377};378 379static const char * const admv1013_vcc_regs[] = {380 "vcc-drv", "vcc2-drv", "vcc-vva", "vcc-amp1", "vcc-amp2",381 "vcc-env", "vcc-bg", "vcc-bg2", "vcc-mixer", "vcc-quad"382};383 384static int admv1013_freq_change(struct notifier_block *nb, unsigned long action, void *data)385{386 struct admv1013_state *st = container_of(nb, struct admv1013_state, nb);387 int ret;388 389 if (action == POST_RATE_CHANGE) {390 mutex_lock(&st->lock);391 ret = notifier_from_errno(admv1013_update_quad_filters(st));392 mutex_unlock(&st->lock);393 return ret;394 }395 396 return NOTIFY_OK;397}398 399#define _ADMV1013_EXT_INFO(_name, _shared, _ident) { \400 .name = _name, \401 .read = admv1013_read, \402 .write = admv1013_write, \403 .private = _ident, \404 .shared = _shared, \405}406 407static const struct iio_chan_spec_ext_info admv1013_ext_info[] = {408 _ADMV1013_EXT_INFO("i_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_I_CALIBPHASE),409 _ADMV1013_EXT_INFO("q_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_Q_CALIBPHASE),410 { },411};412 413#define ADMV1013_CHAN_PHASE(_channel, _channel2, _admv1013_ext_info) { \414 .type = IIO_ALTVOLTAGE, \415 .output = 0, \416 .indexed = 1, \417 .channel2 = _channel2, \418 .channel = _channel, \419 .differential = 1, \420 .ext_info = _admv1013_ext_info, \421 }422 423#define ADMV1013_CHAN_CALIB(_channel, rf_comp) { \424 .type = IIO_ALTVOLTAGE, \425 .output = 0, \426 .indexed = 1, \427 .channel = _channel, \428 .channel2 = IIO_MOD_##rf_comp, \429 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBBIAS), \430 }431 432static const struct iio_chan_spec admv1013_channels[] = {433 ADMV1013_CHAN_PHASE(0, 1, admv1013_ext_info),434 ADMV1013_CHAN_CALIB(0, I),435 ADMV1013_CHAN_CALIB(0, Q),436 ADMV1013_CHAN_CALIB(1, I),437 ADMV1013_CHAN_CALIB(1, Q),438};439 440static int admv1013_init(struct admv1013_state *st, int vcm_uv)441{442 int ret;443 unsigned int data;444 struct spi_device *spi = st->spi;445 446 /* Perform a software reset */447 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,448 ADMV1013_SPI_SOFT_RESET_MSK,449 FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 1));450 if (ret)451 return ret;452 453 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,454 ADMV1013_SPI_SOFT_RESET_MSK,455 FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 0));456 if (ret)457 return ret;458 459 ret = __admv1013_spi_read(st, ADMV1013_REG_SPI_CONTROL, &data);460 if (ret)461 return ret;462 463 data = FIELD_GET(ADMV1013_CHIP_ID_MSK, data);464 if (data != ADMV1013_CHIP_ID) {465 dev_err(&spi->dev, "Invalid Chip ID.\n");466 return -EINVAL;467 }468 469 ret = __admv1013_spi_write(st, ADMV1013_REG_VVA_TEMP_COMP, 0xE700);470 if (ret)471 return ret;472 473 data = FIELD_PREP(ADMV1013_QUAD_SE_MODE_MSK, st->quad_se_mode);474 475 ret = __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,476 ADMV1013_QUAD_SE_MODE_MSK, data);477 if (ret)478 return ret;479 480 ret = admv1013_update_mixer_vgate(st, vcm_uv);481 if (ret)482 return ret;483 484 ret = admv1013_update_quad_filters(st);485 if (ret)486 return ret;487 488 return __admv1013_spi_update_bits(st, ADMV1013_REG_ENABLE,489 ADMV1013_DET_EN_MSK |490 ADMV1013_MIXER_IF_EN_MSK,491 st->det_en |492 st->input_mode);493}494 495static void admv1013_powerdown(void *data)496{497 unsigned int enable_reg, enable_reg_msk;498 499 /* Disable all components in the Enable Register */500 enable_reg_msk = ADMV1013_VGA_PD_MSK |501 ADMV1013_MIXER_PD_MSK |502 ADMV1013_QUAD_PD_MSK |503 ADMV1013_BG_PD_MSK |504 ADMV1013_MIXER_IF_EN_MSK |505 ADMV1013_DET_EN_MSK;506 507 enable_reg = FIELD_PREP(ADMV1013_VGA_PD_MSK, 1) |508 FIELD_PREP(ADMV1013_MIXER_PD_MSK, 1) |509 FIELD_PREP(ADMV1013_QUAD_PD_MSK, 7) |510 FIELD_PREP(ADMV1013_BG_PD_MSK, 1) |511 FIELD_PREP(ADMV1013_MIXER_IF_EN_MSK, 0) |512 FIELD_PREP(ADMV1013_DET_EN_MSK, 0);513 514 admv1013_spi_update_bits(data, ADMV1013_REG_ENABLE, enable_reg_msk, enable_reg);515}516 517static int admv1013_properties_parse(struct admv1013_state *st)518{519 int ret;520 const char *str;521 struct spi_device *spi = st->spi;522 523 st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable");524 525 ret = device_property_read_string(&spi->dev, "adi,input-mode", &str);526 if (ret)527 st->input_mode = ADMV1013_IQ_MODE;528 529 if (!strcmp(str, "iq"))530 st->input_mode = ADMV1013_IQ_MODE;531 else if (!strcmp(str, "if"))532 st->input_mode = ADMV1013_IF_MODE;533 else534 return -EINVAL;535 536 ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str);537 if (ret)538 st->quad_se_mode = ADMV1013_SE_MODE_DIFF;539 540 if (!strcmp(str, "diff"))541 st->quad_se_mode = ADMV1013_SE_MODE_DIFF;542 else if (!strcmp(str, "se-pos"))543 st->quad_se_mode = ADMV1013_SE_MODE_POS;544 else if (!strcmp(str, "se-neg"))545 st->quad_se_mode = ADMV1013_SE_MODE_NEG;546 else547 return -EINVAL;548 549 ret = devm_regulator_bulk_get_enable(&st->spi->dev,550 ARRAY_SIZE(admv1013_vcc_regs),551 admv1013_vcc_regs);552 if (ret) {553 dev_err_probe(&spi->dev, ret,554 "Failed to request VCC regulators\n");555 return ret;556 }557 558 return 0;559}560 561static int admv1013_probe(struct spi_device *spi)562{563 struct iio_dev *indio_dev;564 struct admv1013_state *st;565 int ret, vcm_uv;566 567 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));568 if (!indio_dev)569 return -ENOMEM;570 571 st = iio_priv(indio_dev);572 573 indio_dev->info = &admv1013_info;574 indio_dev->name = "admv1013";575 indio_dev->channels = admv1013_channels;576 indio_dev->num_channels = ARRAY_SIZE(admv1013_channels);577 578 st->spi = spi;579 580 ret = admv1013_properties_parse(st);581 if (ret)582 return ret;583 584 ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vcm");585 if (ret < 0)586 return dev_err_probe(&spi->dev, ret,587 "failed to get the common-mode voltage\n");588 589 vcm_uv = ret;590 591 st->clkin = devm_clk_get_enabled(&spi->dev, "lo_in");592 if (IS_ERR(st->clkin))593 return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),594 "failed to get the LO input clock\n");595 596 st->nb.notifier_call = admv1013_freq_change;597 ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb);598 if (ret)599 return ret;600 601 mutex_init(&st->lock);602 603 ret = admv1013_init(st, vcm_uv);604 if (ret) {605 dev_err(&spi->dev, "admv1013 init failed\n");606 return ret;607 }608 609 ret = devm_add_action_or_reset(&spi->dev, admv1013_powerdown, st);610 if (ret)611 return ret;612 613 return devm_iio_device_register(&spi->dev, indio_dev);614}615 616static const struct spi_device_id admv1013_id[] = {617 { "admv1013", 0 },618 {}619};620MODULE_DEVICE_TABLE(spi, admv1013_id);621 622static const struct of_device_id admv1013_of_match[] = {623 { .compatible = "adi,admv1013" },624 {},625};626MODULE_DEVICE_TABLE(of, admv1013_of_match);627 628static struct spi_driver admv1013_driver = {629 .driver = {630 .name = "admv1013",631 .of_match_table = admv1013_of_match,632 },633 .probe = admv1013_probe,634 .id_table = admv1013_id,635};636module_spi_driver(admv1013_driver);637 638MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");639MODULE_DESCRIPTION("Analog Devices ADMV1013");640MODULE_LICENSE("GPL v2");641