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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * ADRF6780 driver4 *5 * Copyright 2021 Analog Devices Inc.6 */7 8#include <linux/bitfield.h>9#include <linux/bits.h>10#include <linux/clk.h>11#include <linux/clkdev.h>12#include <linux/delay.h>13#include <linux/device.h>14#include <linux/iio/iio.h>15#include <linux/module.h>16#include <linux/mod_devicetable.h>17#include <linux/spi/spi.h>18 19#include <linux/unaligned.h>20 21/* ADRF6780 Register Map */22#define ADRF6780_REG_CONTROL 0x0023#define ADRF6780_REG_ALARM_READBACK 0x0124#define ADRF6780_REG_ALARM_MASKS 0x0225#define ADRF6780_REG_ENABLE 0x0326#define ADRF6780_REG_LINEARIZE 0x0427#define ADRF6780_REG_LO_PATH 0x0528#define ADRF6780_REG_ADC_CONTROL 0x0629#define ADRF6780_REG_ADC_OUTPUT 0x0C30 31/* ADRF6780_REG_CONTROL Map */32#define ADRF6780_PARITY_EN_MSK BIT(15)33#define ADRF6780_SOFT_RESET_MSK BIT(14)34#define ADRF6780_CHIP_ID_MSK GENMASK(11, 4)35#define ADRF6780_CHIP_ID 0xA36#define ADRF6780_CHIP_REVISION_MSK GENMASK(3, 0)37 38/* ADRF6780_REG_ALARM_READBACK Map */39#define ADRF6780_PARITY_ERROR_MSK BIT(15)40#define ADRF6780_TOO_FEW_ERRORS_MSK BIT(14)41#define ADRF6780_TOO_MANY_ERRORS_MSK BIT(13)42#define ADRF6780_ADDRESS_RANGE_ERROR_MSK BIT(12)43 44/* ADRF6780_REG_ENABLE Map */45#define ADRF6780_VGA_BUFFER_EN_MSK BIT(8)46#define ADRF6780_DETECTOR_EN_MSK BIT(7)47#define ADRF6780_LO_BUFFER_EN_MSK BIT(6)48#define ADRF6780_IF_MODE_EN_MSK BIT(5)49#define ADRF6780_IQ_MODE_EN_MSK BIT(4)50#define ADRF6780_LO_X2_EN_MSK BIT(3)51#define ADRF6780_LO_PPF_EN_MSK BIT(2)52#define ADRF6780_LO_EN_MSK BIT(1)53#define ADRF6780_UC_BIAS_EN_MSK BIT(0)54 55/* ADRF6780_REG_LINEARIZE Map */56#define ADRF6780_RDAC_LINEARIZE_MSK GENMASK(7, 0)57 58/* ADRF6780_REG_LO_PATH Map */59#define ADRF6780_LO_SIDEBAND_MSK BIT(10)60#define ADRF6780_Q_PATH_PHASE_ACCURACY_MSK GENMASK(7, 4)61#define ADRF6780_I_PATH_PHASE_ACCURACY_MSK GENMASK(3, 0)62 63/* ADRF6780_REG_ADC_CONTROL Map */64#define ADRF6780_VDET_OUTPUT_SELECT_MSK BIT(3)65#define ADRF6780_ADC_START_MSK BIT(2)66#define ADRF6780_ADC_EN_MSK BIT(1)67#define ADRF6780_ADC_CLOCK_EN_MSK BIT(0)68 69/* ADRF6780_REG_ADC_OUTPUT Map */70#define ADRF6780_ADC_STATUS_MSK BIT(8)71#define ADRF6780_ADC_VALUE_MSK GENMASK(7, 0)72 73struct adrf6780_state {74 struct spi_device *spi;75 struct clk *clkin;76 /* Protect against concurrent accesses to the device */77 struct mutex lock;78 bool vga_buff_en;79 bool lo_buff_en;80 bool if_mode_en;81 bool iq_mode_en;82 bool lo_x2_en;83 bool lo_ppf_en;84 bool lo_en;85 bool uc_bias_en;86 bool lo_sideband;87 bool vdet_out_en;88 u8 data[3] __aligned(IIO_DMA_MINALIGN);89};90 91static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,92 unsigned int *val)93{94 int ret;95 struct spi_transfer t = {0};96 97 st->data[0] = 0x80 | (reg << 1);98 st->data[1] = 0x0;99 st->data[2] = 0x0;100 101 t.rx_buf = &st->data[0];102 t.tx_buf = &st->data[0];103 t.len = 3;104 105 ret = spi_sync_transfer(st->spi, &t, 1);106 if (ret)107 return ret;108 109 *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0);110 111 return ret;112}113 114static int adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,115 unsigned int *val)116{117 int ret;118 119 mutex_lock(&st->lock);120 ret = __adrf6780_spi_read(st, reg, val);121 mutex_unlock(&st->lock);122 123 return ret;124}125 126static int __adrf6780_spi_write(struct adrf6780_state *st,127 unsigned int reg,128 unsigned int val)129{130 put_unaligned_be24((val << 1) | (reg << 17), &st->data[0]);131 132 return spi_write(st->spi, &st->data[0], 3);133}134 135static int adrf6780_spi_write(struct adrf6780_state *st, unsigned int reg,136 unsigned int val)137{138 int ret;139 140 mutex_lock(&st->lock);141 ret = __adrf6780_spi_write(st, reg, val);142 mutex_unlock(&st->lock);143 144 return ret;145}146 147static int __adrf6780_spi_update_bits(struct adrf6780_state *st,148 unsigned int reg, unsigned int mask,149 unsigned int val)150{151 int ret;152 unsigned int data, temp;153 154 ret = __adrf6780_spi_read(st, reg, &data);155 if (ret)156 return ret;157 158 temp = (data & ~mask) | (val & mask);159 160 return __adrf6780_spi_write(st, reg, temp);161}162 163static int adrf6780_spi_update_bits(struct adrf6780_state *st, unsigned int reg,164 unsigned int mask, unsigned int val)165{166 int ret;167 168 mutex_lock(&st->lock);169 ret = __adrf6780_spi_update_bits(st, reg, mask, val);170 mutex_unlock(&st->lock);171 172 return ret;173}174 175static int adrf6780_read_adc_raw(struct adrf6780_state *st, unsigned int *read_val)176{177 int ret;178 179 mutex_lock(&st->lock);180 181 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,182 ADRF6780_ADC_EN_MSK |183 ADRF6780_ADC_CLOCK_EN_MSK |184 ADRF6780_ADC_START_MSK,185 FIELD_PREP(ADRF6780_ADC_EN_MSK, 1) |186 FIELD_PREP(ADRF6780_ADC_CLOCK_EN_MSK, 1) |187 FIELD_PREP(ADRF6780_ADC_START_MSK, 1));188 if (ret)189 goto exit;190 191 /* Recommended delay for the ADC to be ready*/192 usleep_range(200, 250);193 194 ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val);195 if (ret)196 goto exit;197 198 if (!(*read_val & ADRF6780_ADC_STATUS_MSK)) {199 ret = -EINVAL;200 goto exit;201 }202 203 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,204 ADRF6780_ADC_START_MSK,205 FIELD_PREP(ADRF6780_ADC_START_MSK, 0));206 if (ret)207 goto exit;208 209 ret = __adrf6780_spi_read(st, ADRF6780_REG_ADC_OUTPUT, read_val);210 211exit:212 mutex_unlock(&st->lock);213 return ret;214}215 216static int adrf6780_read_raw(struct iio_dev *indio_dev,217 struct iio_chan_spec const *chan,218 int *val, int *val2, long info)219{220 struct adrf6780_state *dev = iio_priv(indio_dev);221 unsigned int data;222 int ret;223 224 switch (info) {225 case IIO_CHAN_INFO_RAW:226 ret = adrf6780_read_adc_raw(dev, &data);227 if (ret)228 return ret;229 230 *val = data & ADRF6780_ADC_VALUE_MSK;231 232 return IIO_VAL_INT;233 234 case IIO_CHAN_INFO_SCALE:235 ret = adrf6780_spi_read(dev, ADRF6780_REG_LINEARIZE, &data);236 if (ret)237 return ret;238 239 *val = data & ADRF6780_RDAC_LINEARIZE_MSK;240 241 return IIO_VAL_INT;242 case IIO_CHAN_INFO_PHASE:243 ret = adrf6780_spi_read(dev, ADRF6780_REG_LO_PATH, &data);244 if (ret)245 return ret;246 247 switch (chan->channel2) {248 case IIO_MOD_I:249 *val = data & ADRF6780_I_PATH_PHASE_ACCURACY_MSK;250 251 return IIO_VAL_INT;252 case IIO_MOD_Q:253 *val = FIELD_GET(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK,254 data);255 256 return IIO_VAL_INT;257 default:258 return -EINVAL;259 }260 default:261 return -EINVAL;262 }263}264 265static int adrf6780_write_raw(struct iio_dev *indio_dev,266 struct iio_chan_spec const *chan,267 int val, int val2, long info)268{269 struct adrf6780_state *st = iio_priv(indio_dev);270 271 switch (info) {272 case IIO_CHAN_INFO_SCALE:273 return adrf6780_spi_write(st, ADRF6780_REG_LINEARIZE, val);274 case IIO_CHAN_INFO_PHASE:275 switch (chan->channel2) {276 case IIO_MOD_I:277 return adrf6780_spi_update_bits(st,278 ADRF6780_REG_LO_PATH,279 ADRF6780_I_PATH_PHASE_ACCURACY_MSK,280 FIELD_PREP(ADRF6780_I_PATH_PHASE_ACCURACY_MSK, val));281 case IIO_MOD_Q:282 return adrf6780_spi_update_bits(st,283 ADRF6780_REG_LO_PATH,284 ADRF6780_Q_PATH_PHASE_ACCURACY_MSK,285 FIELD_PREP(ADRF6780_Q_PATH_PHASE_ACCURACY_MSK, val));286 default:287 return -EINVAL;288 }289 default:290 return -EINVAL;291 }292}293 294static int adrf6780_reg_access(struct iio_dev *indio_dev,295 unsigned int reg,296 unsigned int write_val,297 unsigned int *read_val)298{299 struct adrf6780_state *st = iio_priv(indio_dev);300 301 if (read_val)302 return adrf6780_spi_read(st, reg, read_val);303 else304 return adrf6780_spi_write(st, reg, write_val);305}306 307static const struct iio_info adrf6780_info = {308 .read_raw = adrf6780_read_raw,309 .write_raw = adrf6780_write_raw,310 .debugfs_reg_access = &adrf6780_reg_access,311};312 313#define ADRF6780_CHAN_ADC(_channel) { \314 .type = IIO_ALTVOLTAGE, \315 .output = 0, \316 .indexed = 1, \317 .channel = _channel, \318 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \319}320 321#define ADRF6780_CHAN_RDAC(_channel) { \322 .type = IIO_ALTVOLTAGE, \323 .output = 1, \324 .indexed = 1, \325 .channel = _channel, \326 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) \327}328 329#define ADRF6780_CHAN_IQ_PHASE(_channel, rf_comp) { \330 .type = IIO_ALTVOLTAGE, \331 .modified = 1, \332 .output = 1, \333 .indexed = 1, \334 .channel2 = IIO_MOD_##rf_comp, \335 .channel = _channel, \336 .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) \337}338 339static const struct iio_chan_spec adrf6780_channels[] = {340 ADRF6780_CHAN_ADC(0),341 ADRF6780_CHAN_RDAC(0),342 ADRF6780_CHAN_IQ_PHASE(0, I),343 ADRF6780_CHAN_IQ_PHASE(0, Q),344};345 346static int adrf6780_reset(struct adrf6780_state *st)347{348 int ret;349 struct spi_device *spi = st->spi;350 351 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL,352 ADRF6780_SOFT_RESET_MSK,353 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 1));354 if (ret) {355 dev_err(&spi->dev, "ADRF6780 SPI software reset failed.\n");356 return ret;357 }358 359 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_CONTROL,360 ADRF6780_SOFT_RESET_MSK,361 FIELD_PREP(ADRF6780_SOFT_RESET_MSK, 0));362 if (ret) {363 dev_err(&spi->dev, "ADRF6780 SPI software reset disable failed.\n");364 return ret;365 }366 367 return 0;368}369 370static int adrf6780_init(struct adrf6780_state *st)371{372 int ret;373 unsigned int chip_id, enable_reg, enable_reg_msk;374 struct spi_device *spi = st->spi;375 376 /* Perform a software reset */377 ret = adrf6780_reset(st);378 if (ret)379 return ret;380 381 ret = __adrf6780_spi_read(st, ADRF6780_REG_CONTROL, &chip_id);382 if (ret)383 return ret;384 385 chip_id = FIELD_GET(ADRF6780_CHIP_ID_MSK, chip_id);386 if (chip_id != ADRF6780_CHIP_ID) {387 dev_err(&spi->dev, "ADRF6780 Invalid Chip ID.\n");388 return -EINVAL;389 }390 391 enable_reg_msk = ADRF6780_VGA_BUFFER_EN_MSK |392 ADRF6780_DETECTOR_EN_MSK |393 ADRF6780_LO_BUFFER_EN_MSK |394 ADRF6780_IF_MODE_EN_MSK |395 ADRF6780_IQ_MODE_EN_MSK |396 ADRF6780_LO_X2_EN_MSK |397 ADRF6780_LO_PPF_EN_MSK |398 ADRF6780_LO_EN_MSK |399 ADRF6780_UC_BIAS_EN_MSK;400 401 enable_reg = FIELD_PREP(ADRF6780_VGA_BUFFER_EN_MSK, st->vga_buff_en) |402 FIELD_PREP(ADRF6780_DETECTOR_EN_MSK, 1) |403 FIELD_PREP(ADRF6780_LO_BUFFER_EN_MSK, st->lo_buff_en) |404 FIELD_PREP(ADRF6780_IF_MODE_EN_MSK, st->if_mode_en) |405 FIELD_PREP(ADRF6780_IQ_MODE_EN_MSK, st->iq_mode_en) |406 FIELD_PREP(ADRF6780_LO_X2_EN_MSK, st->lo_x2_en) |407 FIELD_PREP(ADRF6780_LO_PPF_EN_MSK, st->lo_ppf_en) |408 FIELD_PREP(ADRF6780_LO_EN_MSK, st->lo_en) |409 FIELD_PREP(ADRF6780_UC_BIAS_EN_MSK, st->uc_bias_en);410 411 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_ENABLE,412 enable_reg_msk, enable_reg);413 if (ret)414 return ret;415 416 ret = __adrf6780_spi_update_bits(st, ADRF6780_REG_LO_PATH,417 ADRF6780_LO_SIDEBAND_MSK,418 FIELD_PREP(ADRF6780_LO_SIDEBAND_MSK, st->lo_sideband));419 if (ret)420 return ret;421 422 return __adrf6780_spi_update_bits(st, ADRF6780_REG_ADC_CONTROL,423 ADRF6780_VDET_OUTPUT_SELECT_MSK,424 FIELD_PREP(ADRF6780_VDET_OUTPUT_SELECT_MSK, st->vdet_out_en));425}426 427static void adrf6780_properties_parse(struct adrf6780_state *st)428{429 struct spi_device *spi = st->spi;430 431 st->vga_buff_en = device_property_read_bool(&spi->dev, "adi,vga-buff-en");432 st->lo_buff_en = device_property_read_bool(&spi->dev, "adi,lo-buff-en");433 st->if_mode_en = device_property_read_bool(&spi->dev, "adi,if-mode-en");434 st->iq_mode_en = device_property_read_bool(&spi->dev, "adi,iq-mode-en");435 st->lo_x2_en = device_property_read_bool(&spi->dev, "adi,lo-x2-en");436 st->lo_ppf_en = device_property_read_bool(&spi->dev, "adi,lo-ppf-en");437 st->lo_en = device_property_read_bool(&spi->dev, "adi,lo-en");438 st->uc_bias_en = device_property_read_bool(&spi->dev, "adi,uc-bias-en");439 st->lo_sideband = device_property_read_bool(&spi->dev, "adi,lo-sideband");440 st->vdet_out_en = device_property_read_bool(&spi->dev, "adi,vdet-out-en");441}442 443static void adrf6780_powerdown(void *data)444{445 /* Disable all components in the Enable Register */446 adrf6780_spi_write(data, ADRF6780_REG_ENABLE, 0x0);447}448 449static int adrf6780_probe(struct spi_device *spi)450{451 struct iio_dev *indio_dev;452 struct adrf6780_state *st;453 int ret;454 455 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));456 if (!indio_dev)457 return -ENOMEM;458 459 st = iio_priv(indio_dev);460 461 indio_dev->info = &adrf6780_info;462 indio_dev->name = "adrf6780";463 indio_dev->channels = adrf6780_channels;464 indio_dev->num_channels = ARRAY_SIZE(adrf6780_channels);465 466 st->spi = spi;467 468 adrf6780_properties_parse(st);469 470 st->clkin = devm_clk_get_enabled(&spi->dev, "lo_in");471 if (IS_ERR(st->clkin))472 return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),473 "failed to get the LO input clock\n");474 475 mutex_init(&st->lock);476 477 ret = adrf6780_init(st);478 if (ret)479 return ret;480 481 ret = devm_add_action_or_reset(&spi->dev, adrf6780_powerdown, st);482 if (ret)483 return ret;484 485 return devm_iio_device_register(&spi->dev, indio_dev);486}487 488static const struct spi_device_id adrf6780_id[] = {489 { "adrf6780", 0 },490 {}491};492MODULE_DEVICE_TABLE(spi, adrf6780_id);493 494static const struct of_device_id adrf6780_of_match[] = {495 { .compatible = "adi,adrf6780" },496 {}497};498MODULE_DEVICE_TABLE(of, adrf6780_of_match);499 500static struct spi_driver adrf6780_driver = {501 .driver = {502 .name = "adrf6780",503 .of_match_table = adrf6780_of_match,504 },505 .probe = adrf6780_probe,506 .id_table = adrf6780_id,507};508module_spi_driver(adrf6780_driver);509 510MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");511MODULE_DESCRIPTION("Analog Devices ADRF6780");512MODULE_LICENSE("GPL v2");513