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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (C) 2020 Invensense, Inc.4 */5 6#ifndef INV_ICM42600_H_7#define INV_ICM42600_H_8 9#include <linux/bits.h>10#include <linux/bitfield.h>11#include <linux/regmap.h>12#include <linux/mutex.h>13#include <linux/regulator/consumer.h>14#include <linux/pm.h>15#include <linux/iio/iio.h>16#include <linux/iio/common/inv_sensors_timestamp.h>17 18#include "inv_icm42600_buffer.h"19 20enum inv_icm42600_chip {21 INV_CHIP_INVALID,22 INV_CHIP_ICM42600,23 INV_CHIP_ICM42602,24 INV_CHIP_ICM42605,25 INV_CHIP_ICM42686,26 INV_CHIP_ICM42622,27 INV_CHIP_ICM42688,28 INV_CHIP_ICM42631,29 INV_CHIP_NB,30};31 32/* serial bus slew rates */33enum inv_icm42600_slew_rate {34 INV_ICM42600_SLEW_RATE_20_60NS,35 INV_ICM42600_SLEW_RATE_12_36NS,36 INV_ICM42600_SLEW_RATE_6_18NS,37 INV_ICM42600_SLEW_RATE_4_12NS,38 INV_ICM42600_SLEW_RATE_2_6NS,39 INV_ICM42600_SLEW_RATE_INF_2NS,40};41 42enum inv_icm42600_sensor_mode {43 INV_ICM42600_SENSOR_MODE_OFF,44 INV_ICM42600_SENSOR_MODE_STANDBY,45 INV_ICM42600_SENSOR_MODE_LOW_POWER,46 INV_ICM42600_SENSOR_MODE_LOW_NOISE,47 INV_ICM42600_SENSOR_MODE_NB,48};49 50/* gyroscope fullscale values */51enum inv_icm42600_gyro_fs {52 INV_ICM42600_GYRO_FS_2000DPS,53 INV_ICM42600_GYRO_FS_1000DPS,54 INV_ICM42600_GYRO_FS_500DPS,55 INV_ICM42600_GYRO_FS_250DPS,56 INV_ICM42600_GYRO_FS_125DPS,57 INV_ICM42600_GYRO_FS_62_5DPS,58 INV_ICM42600_GYRO_FS_31_25DPS,59 INV_ICM42600_GYRO_FS_15_625DPS,60 INV_ICM42600_GYRO_FS_NB,61};62enum inv_icm42686_gyro_fs {63 INV_ICM42686_GYRO_FS_4000DPS,64 INV_ICM42686_GYRO_FS_2000DPS,65 INV_ICM42686_GYRO_FS_1000DPS,66 INV_ICM42686_GYRO_FS_500DPS,67 INV_ICM42686_GYRO_FS_250DPS,68 INV_ICM42686_GYRO_FS_125DPS,69 INV_ICM42686_GYRO_FS_62_5DPS,70 INV_ICM42686_GYRO_FS_31_25DPS,71 INV_ICM42686_GYRO_FS_NB,72};73 74/* accelerometer fullscale values */75enum inv_icm42600_accel_fs {76 INV_ICM42600_ACCEL_FS_16G,77 INV_ICM42600_ACCEL_FS_8G,78 INV_ICM42600_ACCEL_FS_4G,79 INV_ICM42600_ACCEL_FS_2G,80 INV_ICM42600_ACCEL_FS_NB,81};82enum inv_icm42686_accel_fs {83 INV_ICM42686_ACCEL_FS_32G,84 INV_ICM42686_ACCEL_FS_16G,85 INV_ICM42686_ACCEL_FS_8G,86 INV_ICM42686_ACCEL_FS_4G,87 INV_ICM42686_ACCEL_FS_2G,88 INV_ICM42686_ACCEL_FS_NB,89};90 91/* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */92enum inv_icm42600_odr {93 INV_ICM42600_ODR_8KHZ_LN = 3,94 INV_ICM42600_ODR_4KHZ_LN,95 INV_ICM42600_ODR_2KHZ_LN,96 INV_ICM42600_ODR_1KHZ_LN,97 INV_ICM42600_ODR_200HZ,98 INV_ICM42600_ODR_100HZ,99 INV_ICM42600_ODR_50HZ,100 INV_ICM42600_ODR_25HZ,101 INV_ICM42600_ODR_12_5HZ,102 INV_ICM42600_ODR_6_25HZ_LP,103 INV_ICM42600_ODR_3_125HZ_LP,104 INV_ICM42600_ODR_1_5625HZ_LP,105 INV_ICM42600_ODR_500HZ,106 INV_ICM42600_ODR_NB,107};108 109enum inv_icm42600_filter {110 /* Low-Noise mode sensor data filter (3rd order filter by default) */111 INV_ICM42600_FILTER_BW_ODR_DIV_2,112 113 /* Low-Power mode sensor data filter (averaging) */114 INV_ICM42600_FILTER_AVG_1X = 1,115 INV_ICM42600_FILTER_AVG_16X = 6,116};117 118struct inv_icm42600_sensor_conf {119 int mode;120 int fs;121 int odr;122 int filter;123};124#define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1}125 126struct inv_icm42600_conf {127 struct inv_icm42600_sensor_conf gyro;128 struct inv_icm42600_sensor_conf accel;129 bool temp_en;130};131 132struct inv_icm42600_suspended {133 enum inv_icm42600_sensor_mode gyro;134 enum inv_icm42600_sensor_mode accel;135 bool temp;136};137 138/**139 * struct inv_icm42600_state - driver state variables140 * @lock: lock for serializing multiple registers access.141 * @chip: chip identifier.142 * @name: chip name.143 * @map: regmap pointer.144 * @vdd_supply: VDD voltage regulator for the chip.145 * @vddio_supply: I/O voltage regulator for the chip.146 * @orientation: sensor chip orientation relative to main hardware.147 * @conf: chip sensors configurations.148 * @suspended: suspended sensors configuration.149 * @indio_gyro: gyroscope IIO device.150 * @indio_accel: accelerometer IIO device.151 * @buffer: data transfer buffer aligned for DMA.152 * @fifo: FIFO management structure.153 * @timestamp: interrupt timestamps.154 */155struct inv_icm42600_state {156 struct mutex lock;157 enum inv_icm42600_chip chip;158 const char *name;159 struct regmap *map;160 struct regulator *vdd_supply;161 struct regulator *vddio_supply;162 struct iio_mount_matrix orientation;163 struct inv_icm42600_conf conf;164 struct inv_icm42600_suspended suspended;165 struct iio_dev *indio_gyro;166 struct iio_dev *indio_accel;167 uint8_t buffer[2] __aligned(IIO_DMA_MINALIGN);168 struct inv_icm42600_fifo fifo;169 struct {170 int64_t gyro;171 int64_t accel;172 } timestamp;173};174 175 176/**177 * struct inv_icm42600_sensor_state - sensor state variables178 * @scales: table of scales.179 * @scales_len: length (nb of items) of the scales table.180 * @power_mode: sensor requested power mode (for common frequencies)181 * @filter: sensor filter.182 * @ts: timestamp module states.183 */184struct inv_icm42600_sensor_state {185 const int *scales;186 size_t scales_len;187 enum inv_icm42600_sensor_mode power_mode;188 enum inv_icm42600_filter filter;189 struct inv_sensors_timestamp ts;190};191 192/* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */193 194/* Bank selection register, available in all banks */195#define INV_ICM42600_REG_BANK_SEL 0x76196#define INV_ICM42600_BANK_SEL_MASK GENMASK(2, 0)197 198/* User bank 0 (MSB 0x00) */199#define INV_ICM42600_REG_DEVICE_CONFIG 0x0011200#define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET BIT(0)201 202#define INV_ICM42600_REG_DRIVE_CONFIG 0x0013203#define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3)204#define INV_ICM42600_DRIVE_CONFIG_I2C(_rate) \205 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_I2C_MASK, (_rate))206#define INV_ICM42600_DRIVE_CONFIG_SPI_MASK GENMASK(2, 0)207#define INV_ICM42600_DRIVE_CONFIG_SPI(_rate) \208 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_SPI_MASK, (_rate))209 210#define INV_ICM42600_REG_INT_CONFIG 0x0014211#define INV_ICM42600_INT_CONFIG_INT2_LATCHED BIT(5)212#define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL BIT(4)213#define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3)214#define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_LOW 0x00215#define INV_ICM42600_INT_CONFIG_INT1_LATCHED BIT(2)216#define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL BIT(1)217#define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0)218#define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_LOW 0x00219 220#define INV_ICM42600_REG_FIFO_CONFIG 0x0016221#define INV_ICM42600_FIFO_CONFIG_MASK GENMASK(7, 6)222#define INV_ICM42600_FIFO_CONFIG_BYPASS \223 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 0)224#define INV_ICM42600_FIFO_CONFIG_STREAM \225 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 1)226#define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL \227 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 2)228 229/* all sensor data are 16 bits (2 registers wide) in big-endian */230#define INV_ICM42600_REG_TEMP_DATA 0x001D231#define INV_ICM42600_REG_ACCEL_DATA_X 0x001F232#define INV_ICM42600_REG_ACCEL_DATA_Y 0x0021233#define INV_ICM42600_REG_ACCEL_DATA_Z 0x0023234#define INV_ICM42600_REG_GYRO_DATA_X 0x0025235#define INV_ICM42600_REG_GYRO_DATA_Y 0x0027236#define INV_ICM42600_REG_GYRO_DATA_Z 0x0029237#define INV_ICM42600_DATA_INVALID -32768238 239#define INV_ICM42600_REG_INT_STATUS 0x002D240#define INV_ICM42600_INT_STATUS_UI_FSYNC BIT(6)241#define INV_ICM42600_INT_STATUS_PLL_RDY BIT(5)242#define INV_ICM42600_INT_STATUS_RESET_DONE BIT(4)243#define INV_ICM42600_INT_STATUS_DATA_RDY BIT(3)244#define INV_ICM42600_INT_STATUS_FIFO_THS BIT(2)245#define INV_ICM42600_INT_STATUS_FIFO_FULL BIT(1)246#define INV_ICM42600_INT_STATUS_AGC_RDY BIT(0)247 248/*249 * FIFO access registers250 * FIFO count is 16 bits (2 registers) big-endian251 * FIFO data is a continuous read register to read FIFO content252 */253#define INV_ICM42600_REG_FIFO_COUNT 0x002E254#define INV_ICM42600_REG_FIFO_DATA 0x0030255 256#define INV_ICM42600_REG_SIGNAL_PATH_RESET 0x004B257#define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6)258#define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5)259#define INV_ICM42600_SIGNAL_PATH_RESET_RESET BIT(3)260#define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE BIT(2)261#define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(1)262 263/* default configuration: all data big-endian and fifo count in bytes */264#define INV_ICM42600_REG_INTF_CONFIG0 0x004C265#define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA BIT(7)266#define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC BIT(6)267#define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5)268#define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4)269#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0)270#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS \271 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 2)272#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS \273 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 3)274 275#define INV_ICM42600_REG_INTF_CONFIG1 0x004D276#define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC BIT(3)277 278#define INV_ICM42600_REG_PWR_MGMT0 0x004E279#define INV_ICM42600_PWR_MGMT0_TEMP_DIS BIT(5)280#define INV_ICM42600_PWR_MGMT0_IDLE BIT(4)281#define INV_ICM42600_PWR_MGMT0_GYRO(_mode) \282 FIELD_PREP(GENMASK(3, 2), (_mode))283#define INV_ICM42600_PWR_MGMT0_ACCEL(_mode) \284 FIELD_PREP(GENMASK(1, 0), (_mode))285 286#define INV_ICM42600_REG_GYRO_CONFIG0 0x004F287#define INV_ICM42600_GYRO_CONFIG0_FS(_fs) \288 FIELD_PREP(GENMASK(7, 5), (_fs))289#define INV_ICM42600_GYRO_CONFIG0_ODR(_odr) \290 FIELD_PREP(GENMASK(3, 0), (_odr))291 292#define INV_ICM42600_REG_ACCEL_CONFIG0 0x0050293#define INV_ICM42600_ACCEL_CONFIG0_FS(_fs) \294 FIELD_PREP(GENMASK(7, 5), (_fs))295#define INV_ICM42600_ACCEL_CONFIG0_ODR(_odr) \296 FIELD_PREP(GENMASK(3, 0), (_odr))297 298#define INV_ICM42600_REG_GYRO_ACCEL_CONFIG0 0x0052299#define INV_ICM42600_GYRO_ACCEL_CONFIG0_ACCEL_FILT(_f) \300 FIELD_PREP(GENMASK(7, 4), (_f))301#define INV_ICM42600_GYRO_ACCEL_CONFIG0_GYRO_FILT(_f) \302 FIELD_PREP(GENMASK(3, 0), (_f))303 304#define INV_ICM42600_REG_TMST_CONFIG 0x0054305#define INV_ICM42600_TMST_CONFIG_MASK GENMASK(4, 0)306#define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN BIT(4)307#define INV_ICM42600_TMST_CONFIG_TMST_RES_16US BIT(3)308#define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN BIT(2)309#define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1)310#define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0)311 312#define INV_ICM42600_REG_FIFO_CONFIG1 0x005F313#define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6)314#define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5)315#define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN BIT(3)316#define INV_ICM42600_FIFO_CONFIG1_TEMP_EN BIT(2)317#define INV_ICM42600_FIFO_CONFIG1_GYRO_EN BIT(1)318#define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN BIT(0)319 320/* FIFO watermark is 16 bits (2 registers wide) in little-endian */321#define INV_ICM42600_REG_FIFO_WATERMARK 0x0060322#define INV_ICM42600_FIFO_WATERMARK_VAL(_wm) \323 cpu_to_le16((_wm) & GENMASK(11, 0))324/* FIFO is 2048 bytes, let 12 samples for reading latency */325#define INV_ICM42600_FIFO_WATERMARK_MAX (2048 - 12 * 16)326 327#define INV_ICM42600_REG_INT_CONFIG1 0x0064328#define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION BIT(6)329#define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE BIT(5)330#define INV_ICM42600_INT_CONFIG1_ASYNC_RESET BIT(4)331 332#define INV_ICM42600_REG_INT_SOURCE0 0x0065333#define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN BIT(6)334#define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5)335#define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4)336#define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN BIT(3)337#define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2)338#define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1)339#define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0)340 341#define INV_ICM42600_REG_WHOAMI 0x0075342#define INV_ICM42600_WHOAMI_ICM42600 0x40343#define INV_ICM42600_WHOAMI_ICM42602 0x41344#define INV_ICM42600_WHOAMI_ICM42605 0x42345#define INV_ICM42600_WHOAMI_ICM42686 0x44346#define INV_ICM42600_WHOAMI_ICM42622 0x46347#define INV_ICM42600_WHOAMI_ICM42688 0x47348#define INV_ICM42600_WHOAMI_ICM42631 0x5C349 350/* User bank 1 (MSB 0x10) */351#define INV_ICM42600_REG_SENSOR_CONFIG0 0x1003352#define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE BIT(5)353#define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE BIT(4)354#define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE BIT(3)355#define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE BIT(2)356#define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE BIT(1)357#define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE BIT(0)358 359/* Timestamp value is 20 bits (3 registers) in little-endian */360#define INV_ICM42600_REG_TMSTVAL 0x1062361#define INV_ICM42600_TMSTVAL_MASK GENMASK(19, 0)362 363#define INV_ICM42600_REG_INTF_CONFIG4 0x107A364#define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY BIT(6)365#define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE BIT(1)366 367#define INV_ICM42600_REG_INTF_CONFIG6 0x107C368#define INV_ICM42600_INTF_CONFIG6_MASK GENMASK(4, 0)369#define INV_ICM42600_INTF_CONFIG6_I3C_EN BIT(4)370#define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN BIT(3)371#define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN BIT(2)372#define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN BIT(1)373#define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0)374 375/* User bank 4 (MSB 0x40) */376#define INV_ICM42600_REG_INT_SOURCE8 0x404F377#define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5)378#define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4)379#define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN BIT(3)380#define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN BIT(2)381#define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN BIT(1)382#define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN BIT(0)383 384#define INV_ICM42600_REG_OFFSET_USER0 0x4077385#define INV_ICM42600_REG_OFFSET_USER1 0x4078386#define INV_ICM42600_REG_OFFSET_USER2 0x4079387#define INV_ICM42600_REG_OFFSET_USER3 0x407A388#define INV_ICM42600_REG_OFFSET_USER4 0x407B389#define INV_ICM42600_REG_OFFSET_USER5 0x407C390#define INV_ICM42600_REG_OFFSET_USER6 0x407D391#define INV_ICM42600_REG_OFFSET_USER7 0x407E392#define INV_ICM42600_REG_OFFSET_USER8 0x407F393 394/* Sleep times required by the driver */395#define INV_ICM42600_POWER_UP_TIME_MS 100396#define INV_ICM42600_RESET_TIME_MS 1397#define INV_ICM42600_ACCEL_STARTUP_TIME_MS 20398#define INV_ICM42600_GYRO_STARTUP_TIME_MS 60399#define INV_ICM42600_GYRO_STOP_TIME_MS 150400#define INV_ICM42600_TEMP_STARTUP_TIME_MS 14401#define INV_ICM42600_SUSPEND_DELAY_MS 2000402 403typedef int (*inv_icm42600_bus_setup)(struct inv_icm42600_state *);404 405extern const struct regmap_config inv_icm42600_regmap_config;406extern const struct dev_pm_ops inv_icm42600_pm_ops;407 408const struct iio_mount_matrix *409inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev,410 const struct iio_chan_spec *chan);411 412uint32_t inv_icm42600_odr_to_period(enum inv_icm42600_odr odr);413 414int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st,415 struct inv_icm42600_sensor_conf *conf,416 unsigned int *sleep_ms);417 418int inv_icm42600_set_gyro_conf(struct inv_icm42600_state *st,419 struct inv_icm42600_sensor_conf *conf,420 unsigned int *sleep_ms);421 422int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable,423 unsigned int *sleep_ms);424 425int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg,426 unsigned int writeval, unsigned int *readval);427 428int inv_icm42600_core_probe(struct regmap *regmap, int chip, int irq,429 inv_icm42600_bus_setup bus_setup);430 431struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st);432 433int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev);434 435struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st);436 437int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev);438 439#endif440