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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3* Copyright (C) 2012 Invensense, Inc.4*/5 6#ifndef INV_MPU_IIO_H_7#define INV_MPU_IIO_H_8 9#include <linux/i2c.h>10#include <linux/i2c-mux.h>11#include <linux/mutex.h>12#include <linux/platform_data/invensense_mpu6050.h>13#include <linux/regmap.h>14 15#include <linux/iio/buffer.h>16#include <linux/iio/common/inv_sensors_timestamp.h>17#include <linux/iio/iio.h>18#include <linux/iio/kfifo_buf.h>19#include <linux/iio/trigger.h>20#include <linux/iio/triggered_buffer.h>21#include <linux/iio/trigger_consumer.h>22#include <linux/iio/sysfs.h>23 24/**25 * struct inv_mpu6050_reg_map - Notable registers.26 * @sample_rate_div: Divider applied to gyro output rate.27 * @lpf: Configures internal low pass filter.28 * @accel_lpf: Configures accelerometer low pass filter.29 * @user_ctrl: Enables/resets the FIFO.30 * @fifo_en: Determines which data will appear in FIFO.31 * @gyro_config: gyro config register.32 * @accl_config: accel config register33 * @fifo_count_h: Upper byte of FIFO count.34 * @fifo_r_w: FIFO register.35 * @raw_gyro: Address of first gyro register.36 * @raw_accl: Address of first accel register.37 * @temperature: temperature register38 * @int_enable: Interrupt enable register.39 * @int_status: Interrupt status register.40 * @pwr_mgmt_1: Controls chip's power state and clock source.41 * @pwr_mgmt_2: Controls power state of individual sensors.42 * @int_pin_cfg; Controls interrupt pin configuration.43 * @accl_offset: Controls the accelerometer calibration offset.44 * @gyro_offset: Controls the gyroscope calibration offset.45 * @i2c_if: Controls the i2c interface46 */47struct inv_mpu6050_reg_map {48 u8 sample_rate_div;49 u8 lpf;50 u8 accel_lpf;51 u8 user_ctrl;52 u8 fifo_en;53 u8 gyro_config;54 u8 accl_config;55 u8 fifo_count_h;56 u8 fifo_r_w;57 u8 raw_gyro;58 u8 raw_accl;59 u8 temperature;60 u8 int_enable;61 u8 int_status;62 u8 pwr_mgmt_1;63 u8 pwr_mgmt_2;64 u8 int_pin_cfg;65 u8 accl_offset;66 u8 gyro_offset;67 u8 i2c_if;68};69 70/*device enum */71enum inv_devices {72 INV_MPU6050,73 INV_MPU6500,74 INV_MPU6515,75 INV_MPU6880,76 INV_MPU6000,77 INV_MPU9150,78 INV_MPU9250,79 INV_MPU9255,80 INV_ICM20608,81 INV_ICM20608D,82 INV_ICM20609,83 INV_ICM20689,84 INV_ICM20600,85 INV_ICM20602,86 INV_ICM20690,87 INV_IAM20680,88 INV_NUM_PARTS89};90 91/* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer, WoM */92#define INV_MPU6050_SENSOR_ACCL BIT(0)93#define INV_MPU6050_SENSOR_GYRO BIT(1)94#define INV_MPU6050_SENSOR_TEMP BIT(2)95#define INV_MPU6050_SENSOR_MAGN BIT(3)96#define INV_MPU6050_SENSOR_WOM BIT(4)97 98/**99 * struct inv_mpu6050_chip_config - Cached chip configuration data.100 * @clk: selected chip clock101 * @fsr: Full scale range.102 * @lpf: Digital low pass filter frequency.103 * @accl_fs: accel full scale range.104 * @accl_en: accel engine enabled105 * @gyro_en: gyro engine enabled106 * @temp_en: temperature sensor enabled107 * @magn_en: magn engine (i2c master) enabled108 * @wom_en: Wake-on-Motion enabled109 * @accl_fifo_enable: enable accel data output110 * @gyro_fifo_enable: enable gyro data output111 * @temp_fifo_enable: enable temp data output112 * @magn_fifo_enable: enable magn data output113 * @divider: chip sample rate divider (sample rate divider - 1)114 * @roc_threshold: save ROC threshold (WoM) set value115 */116struct inv_mpu6050_chip_config {117 unsigned int clk:3;118 unsigned int fsr:2;119 unsigned int lpf:3;120 unsigned int accl_fs:2;121 unsigned int accl_en:1;122 unsigned int gyro_en:1;123 unsigned int temp_en:1;124 unsigned int magn_en:1;125 unsigned int wom_en:1;126 unsigned int accl_fifo_enable:1;127 unsigned int gyro_fifo_enable:1;128 unsigned int temp_fifo_enable:1;129 unsigned int magn_fifo_enable:1;130 u8 divider;131 u8 user_ctrl;132 u64 roc_threshold;133};134 135/*136 * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8.137 * May be less if fewer channels are enabled, as long as the timestamp138 * remains 8 byte aligned139 */140#define INV_MPU6050_OUTPUT_DATA_SIZE 32141 142/**143 * struct inv_mpu6050_hw - Other important hardware information.144 * @whoami: Self identification byte from WHO_AM_I register145 * @name: name of the chip.146 * @reg: register map of the chip.147 * @config: configuration of the chip.148 * @fifo_size: size of the FIFO in bytes.149 * @temp: offset and scale to apply to raw temperature.150 */151struct inv_mpu6050_hw {152 u8 whoami;153 u8 *name;154 const struct inv_mpu6050_reg_map *reg;155 const struct inv_mpu6050_chip_config *config;156 size_t fifo_size;157 struct {158 int offset;159 int scale;160 } temp;161 struct {162 unsigned int accel;163 unsigned int gyro;164 } startup_time;165};166 167/*168 * struct inv_mpu6050_state - Driver state variables.169 * @lock: Chip access lock.170 * @trig: IIO trigger.171 * @chip_config: Cached attribute information.172 * @reg: Map of important registers.173 * @hw: Other hardware-specific information.174 * @chip_type: chip type.175 * @plat_data: platform data (deprecated in favor of @orientation).176 * @orientation: sensor chip orientation relative to main hardware.177 * @map regmap pointer.178 * @irq interrupt number.179 * @irq_mask the int_pin_cfg mask to configure interrupt type.180 * @timestamp: timestamping module181 * @vdd_supply: VDD voltage regulator for the chip.182 * @vddio_supply I/O voltage regulator for the chip.183 * @magn_disabled: magnetometer disabled for backward compatibility reason.184 * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss.185 * @magn_orient: magnetometer sensor chip orientation if available.186 * @suspended_sensors: sensors mask of sensors turned off for suspend187 * @data: read buffer used for bulk reads.188 * @it_timestamp: interrupt timestamp.189 */190struct inv_mpu6050_state {191 struct mutex lock;192 struct iio_trigger *trig;193 struct inv_mpu6050_chip_config chip_config;194 const struct inv_mpu6050_reg_map *reg;195 const struct inv_mpu6050_hw *hw;196 enum inv_devices chip_type;197 struct i2c_mux_core *muxc;198 struct i2c_client *mux_client;199 struct inv_mpu6050_platform_data plat_data;200 struct iio_mount_matrix orientation;201 struct regmap *map;202 int irq;203 u8 irq_mask;204 unsigned skip_samples;205 struct inv_sensors_timestamp timestamp;206 struct regulator *vdd_supply;207 struct regulator *vddio_supply;208 bool magn_disabled;209 s32 magn_raw_to_gauss[3];210 struct iio_mount_matrix magn_orient;211 unsigned int suspended_sensors;212 bool level_shifter;213 u8 *data;214 s64 it_timestamp;215};216 217/*register and associated bit definition*/218#define INV_MPU6050_REG_ACCEL_OFFSET 0x06219#define INV_MPU6050_REG_GYRO_OFFSET 0x13220 221#define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19222#define INV_MPU6050_REG_CONFIG 0x1A223#define INV_MPU6050_REG_GYRO_CONFIG 0x1B224#define INV_MPU6050_REG_ACCEL_CONFIG 0x1C225 226#define INV_MPU6050_REG_FIFO_EN 0x23227#define INV_MPU6050_BIT_SLAVE_0 0x01228#define INV_MPU6050_BIT_SLAVE_1 0x02229#define INV_MPU6050_BIT_SLAVE_2 0x04230#define INV_MPU6050_BIT_ACCEL_OUT 0x08231#define INV_MPU6050_BITS_GYRO_OUT 0x70232#define INV_MPU6050_BIT_TEMP_OUT 0x80233 234#define INV_MPU6050_REG_I2C_MST_CTRL 0x24235#define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D236#define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10237#define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20238#define INV_MPU6050_BIT_WAIT_FOR_ES 0x40239#define INV_MPU6050_BIT_MULT_MST_EN 0x80240 241/* control I2C slaves from 0 to 3 */242#define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x))243#define INV_MPU6050_BIT_I2C_SLV_RNW 0x80244 245#define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x))246 247#define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x))248#define INV_MPU6050_BIT_SLV_GRP 0x10249#define INV_MPU6050_BIT_SLV_REG_DIS 0x20250#define INV_MPU6050_BIT_SLV_BYTE_SW 0x40251#define INV_MPU6050_BIT_SLV_EN 0x80252 253/* I2C master delay register */254#define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34255#define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F)256 257#define INV_MPU6050_REG_I2C_MST_STATUS 0x36258#define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01259#define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02260#define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04261#define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08262 263#define INV_MPU6050_REG_INT_ENABLE 0x38264#define INV_MPU6050_BIT_DATA_RDY_EN 0x01265#define INV_MPU6050_BIT_DMP_INT_EN 0x02266#define INV_MPU6500_BIT_WOM_INT_EN BIT(6)267#define INV_ICM20608_BIT_WOM_INT_EN GENMASK(7, 5)268 269#define INV_MPU6050_REG_RAW_ACCEL 0x3B270#define INV_MPU6050_REG_TEMPERATURE 0x41271#define INV_MPU6050_REG_RAW_GYRO 0x43272 273#define INV_MPU6050_REG_INT_STATUS 0x3A274#define INV_MPU6500_BIT_WOM_INT BIT(6)275#define INV_ICM20608_BIT_WOM_INT GENMASK(7, 5)276#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10277#define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01278 279#define INV_MPU6050_REG_EXT_SENS_DATA 0x49280 281/* I2C slaves data output from 0 to 3 */282#define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x))283 284#define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67285#define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01286#define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02287#define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04288#define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08289#define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80290 291#define INV_MPU6050_REG_SIGNAL_PATH_RESET 0x68292#define INV_MPU6050_BIT_TEMP_RST BIT(0)293#define INV_MPU6050_BIT_ACCEL_RST BIT(1)294#define INV_MPU6050_BIT_GYRO_RST BIT(2)295 296#define INV_MPU6050_REG_USER_CTRL 0x6A297#define INV_MPU6050_BIT_SIG_COND_RST 0x01298#define INV_MPU6050_BIT_FIFO_RST 0x04299#define INV_MPU6050_BIT_DMP_RST 0x08300#define INV_MPU6050_BIT_I2C_MST_EN 0x20301#define INV_MPU6050_BIT_FIFO_EN 0x40302#define INV_MPU6050_BIT_DMP_EN 0x80303#define INV_MPU6050_BIT_I2C_IF_DIS 0x10304 305#define INV_MPU6050_REG_PWR_MGMT_1 0x6B306#define INV_MPU6050_BIT_H_RESET 0x80307#define INV_MPU6050_BIT_SLEEP 0x40308#define INV_MPU6050_BIT_CYCLE 0x20309#define INV_MPU6050_BIT_TEMP_DIS 0x08310#define INV_MPU6050_BIT_CLK_MASK 0x7311 312#define INV_MPU6050_REG_PWR_MGMT_2 0x6C313#define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38314#define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07315 316/* ICM20609 registers */317#define INV_ICM20609_REG_ACCEL_WOM_X_THR 0x20318#define INV_ICM20609_REG_ACCEL_WOM_Y_THR 0x21319#define INV_ICM20609_REG_ACCEL_WOM_Z_THR 0x22320 321/* ICM20602 register */322#define INV_ICM20602_REG_I2C_IF 0x70323#define INV_ICM20602_BIT_I2C_IF_DIS 0x40324 325#define INV_MPU6050_REG_FIFO_COUNT_H 0x72326#define INV_MPU6050_REG_FIFO_R_W 0x74327 328#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6329#define INV_MPU6050_FIFO_COUNT_BYTE 2330 331/* MPU9X50 9-axis magnetometer */332#define INV_MPU9X50_BYTES_MAGN 7333 334/* FIFO temperature sample size */335#define INV_MPU6050_BYTES_PER_TEMP_SENSOR 2336 337/* mpu6500 registers */338#define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D339#define INV_ICM20689_BITS_FIFO_SIZE_MAX 0xC0340#define INV_MPU6500_REG_LP_ODR 0x1E341#define INV_MPU6500_REG_WOM_THRESHOLD 0x1F342#define INV_MPU6500_REG_ACCEL_INTEL_CTRL 0x69343#define INV_MPU6500_BIT_ACCEL_INTEL_EN BIT(7)344#define INV_MPU6500_BIT_ACCEL_INTEL_MODE BIT(6)345#define INV_MPU6500_REG_ACCEL_OFFSET 0x77346 347/* delay time in milliseconds */348#define INV_MPU6050_POWER_UP_TIME 100349#define INV_MPU6050_TEMP_UP_TIME 100350#define INV_MPU6050_ACCEL_STARTUP_TIME 20351#define INV_MPU6050_GYRO_STARTUP_TIME 60352#define INV_MPU6050_GYRO_DOWN_TIME 150353#define INV_MPU6050_SUSPEND_DELAY_MS 2000354 355#define INV_MPU6500_GYRO_STARTUP_TIME 70356#define INV_MPU6500_ACCEL_STARTUP_TIME 30357 358#define INV_ICM20602_GYRO_STARTUP_TIME 100359#define INV_ICM20602_ACCEL_STARTUP_TIME 20360 361#define INV_ICM20690_GYRO_STARTUP_TIME 80362#define INV_ICM20690_ACCEL_STARTUP_TIME 10363 364 365/* delay time in microseconds */366#define INV_MPU6050_REG_UP_TIME_MIN 5000367#define INV_MPU6050_REG_UP_TIME_MAX 10000368 369#define INV_MPU6050_TEMP_OFFSET 12420370#define INV_MPU6050_TEMP_SCALE 2941176371#define INV_MPU6050_MAX_GYRO_FS_PARAM 3372#define INV_MPU6050_MAX_ACCL_FS_PARAM 3373#define INV_MPU6050_THREE_AXIS 3374#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3375#define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT 2376#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3377 378#define INV_MPU6500_TEMP_OFFSET 7011379#define INV_MPU6500_TEMP_SCALE 2995178380 381#define INV_ICM20608_TEMP_OFFSET 8170382#define INV_ICM20608_TEMP_SCALE 3059976383 384#define INV_MPU6050_REG_INT_PIN_CFG 0x37385#define INV_MPU6050_ACTIVE_HIGH 0x00386#define INV_MPU6050_ACTIVE_LOW 0x80387/* enable level triggering */388#define INV_MPU6050_LATCH_INT_EN 0x20389#define INV_MPU6050_BIT_BYPASS_EN 0x2390 391/* Allowed timestamp period jitter in percent */392#define INV_MPU6050_TS_PERIOD_JITTER 4393 394/* init parameters */395#define INV_MPU6050_MAX_FIFO_RATE 1000396#define INV_MPU6050_MIN_FIFO_RATE 4397 398/* chip internal frequency: 1KHz */399#define INV_MPU6050_INTERNAL_FREQ_HZ 1000400/* return the frequency divider (chip sample rate divider + 1) */401#define INV_MPU6050_FREQ_DIVIDER(st) \402 ((st)->chip_config.divider + 1)403/* chip sample rate divider to fifo rate */404#define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \405 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)406#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \407 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))408 409#define INV_MPU6050_REG_WHOAMI 117410 411#define INV_MPU6000_WHOAMI_VALUE 0x68412#define INV_MPU6050_WHOAMI_VALUE 0x68413#define INV_MPU6500_WHOAMI_VALUE 0x70414#define INV_MPU6880_WHOAMI_VALUE 0x78415#define INV_MPU9150_WHOAMI_VALUE 0x68416#define INV_MPU9250_WHOAMI_VALUE 0x71417#define INV_MPU9255_WHOAMI_VALUE 0x73418#define INV_MPU6515_WHOAMI_VALUE 0x74419#define INV_ICM20608_WHOAMI_VALUE 0xAF420#define INV_ICM20608D_WHOAMI_VALUE 0xAE421#define INV_ICM20609_WHOAMI_VALUE 0xA6422#define INV_ICM20689_WHOAMI_VALUE 0x98423#define INV_ICM20600_WHOAMI_VALUE 0x11424#define INV_ICM20602_WHOAMI_VALUE 0x12425#define INV_ICM20690_WHOAMI_VALUE 0x20426#define INV_IAM20680_WHOAMI_VALUE 0xA9427 428/* scan element definition for generic MPU6xxx devices */429enum inv_mpu6050_scan {430 INV_MPU6050_SCAN_ACCL_X,431 INV_MPU6050_SCAN_ACCL_Y,432 INV_MPU6050_SCAN_ACCL_Z,433 INV_MPU6050_SCAN_TEMP,434 INV_MPU6050_SCAN_GYRO_X,435 INV_MPU6050_SCAN_GYRO_Y,436 INV_MPU6050_SCAN_GYRO_Z,437 INV_MPU6050_SCAN_TIMESTAMP,438 439 INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1,440 INV_MPU9X50_SCAN_MAGN_Y,441 INV_MPU9X50_SCAN_MAGN_Z,442 INV_MPU9X50_SCAN_TIMESTAMP,443};444 445enum inv_mpu6050_filter_e {446 INV_MPU6050_FILTER_NOLPF2 = 0,447 INV_MPU6050_FILTER_200HZ,448 INV_MPU6050_FILTER_100HZ,449 INV_MPU6050_FILTER_45HZ,450 INV_MPU6050_FILTER_20HZ,451 INV_MPU6050_FILTER_10HZ,452 INV_MPU6050_FILTER_5HZ,453 INV_MPU6050_FILTER_NOLPF,454 NUM_MPU6050_FILTER455};456 457enum inv_mpu6050_lposc_e {458 INV_MPU6050_LPOSC_4HZ = 4,459 INV_MPU6050_LPOSC_8HZ,460 INV_MPU6050_LPOSC_16HZ,461 INV_MPU6050_LPOSC_31HZ,462 INV_MPU6050_LPOSC_62HZ,463 INV_MPU6050_LPOSC_125HZ,464 INV_MPU6050_LPOSC_250HZ,465 INV_MPU6050_LPOSC_500HZ,466 NUM_MPU6050_LPOSC,467};468 469/* IIO attribute address */470enum INV_MPU6050_IIO_ATTR_ADDR {471 ATTR_GYRO_MATRIX,472 ATTR_ACCL_MATRIX,473};474 475enum inv_mpu6050_accl_fs_e {476 INV_MPU6050_FS_02G = 0,477 INV_MPU6050_FS_04G,478 INV_MPU6050_FS_08G,479 INV_MPU6050_FS_16G,480 NUM_ACCL_FSR481};482 483enum inv_mpu6050_fsr_e {484 INV_MPU6050_FSR_250DPS = 0,485 INV_MPU6050_FSR_500DPS,486 INV_MPU6050_FSR_1000DPS,487 INV_MPU6050_FSR_2000DPS,488 NUM_MPU6050_FSR489};490 491enum inv_mpu6050_clock_sel_e {492 INV_CLK_INTERNAL = 0,493 INV_CLK_PLL,494 NUM_CLK495};496 497irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);498int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);499int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable);500int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,501 unsigned int mask);502int inv_mpu_acpi_create_mux_client(struct i2c_client *client);503void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);504int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,505 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);506extern const struct dev_pm_ops inv_mpu_pmops;507 508#endif509