243 lines · c
1/*2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.3 *4 * This software is available to you under a choice of one of two5 * licenses. You may choose to be licensed under the terms of the GNU6 * General Public License (GPL) Version 2, available from the file7 * COPYING in the main directory of this source tree, or the8 * OpenIB.org BSD license below:9 *10 * Redistribution and use in source and binary forms, with or11 * without modification, are permitted provided that the following12 * conditions are met:13 *14 * - Redistributions of source code must retain the above15 * copyright notice, this list of conditions and the following16 * disclaimer.17 *18 * - Redistributions in binary form must reproduce the above19 * copyright notice, this list of conditions and the following20 * disclaimer in the documentation and/or other materials21 * provided with the distribution.22 *23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE30 * SOFTWARE.31 */32#include <linux/slab.h>33#include <linux/mman.h>34#include <net/sock.h>35 36#include "iw_cxgb4.h"37 38static void print_tpte(struct c4iw_dev *dev, u32 stag)39{40 int ret;41 struct fw_ri_tpte tpte;42 43 ret = cxgb4_read_tpte(dev->rdev.lldi.ports[0], stag,44 (__be32 *)&tpte);45 if (ret) {46 dev_err(&dev->rdev.lldi.pdev->dev,47 "%s cxgb4_read_tpte err %d\n", __func__, ret);48 return;49 }50 pr_debug("stag idx 0x%x valid %d key 0x%x state %d pdid %d perm 0x%x ps %d len 0x%llx va 0x%llx\n",51 stag & 0xffffff00,52 FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),53 FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),54 FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),55 FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),56 FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),57 FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),58 ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),59 ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));60}61 62static void dump_err_cqe(struct c4iw_dev *dev, struct t4_cqe *err_cqe)63{64 __be64 *p = (void *)err_cqe;65 66 dev_err(&dev->rdev.lldi.pdev->dev,67 "AE qpid %d opcode %d status 0x%x "68 "type %d len 0x%x wrid.hi 0x%x wrid.lo 0x%x\n",69 CQE_QPID(err_cqe), CQE_OPCODE(err_cqe),70 CQE_STATUS(err_cqe), CQE_TYPE(err_cqe), ntohl(err_cqe->len),71 CQE_WRID_HI(err_cqe), CQE_WRID_LOW(err_cqe));72 73 pr_debug("%016llx %016llx %016llx %016llx - %016llx %016llx %016llx %016llx\n",74 be64_to_cpu(p[0]), be64_to_cpu(p[1]), be64_to_cpu(p[2]),75 be64_to_cpu(p[3]), be64_to_cpu(p[4]), be64_to_cpu(p[5]),76 be64_to_cpu(p[6]), be64_to_cpu(p[7]));77 78 /*79 * Ingress WRITE and READ_RESP errors provide80 * the offending stag, so parse and log it.81 */82 if (RQ_TYPE(err_cqe) && (CQE_OPCODE(err_cqe) == FW_RI_RDMA_WRITE ||83 CQE_OPCODE(err_cqe) == FW_RI_READ_RESP))84 print_tpte(dev, CQE_WRID_STAG(err_cqe));85}86 87static void post_qp_event(struct c4iw_dev *dev, struct c4iw_cq *chp,88 struct c4iw_qp *qhp,89 struct t4_cqe *err_cqe,90 enum ib_event_type ib_event)91{92 struct ib_event event;93 struct c4iw_qp_attributes attrs;94 unsigned long flag;95 96 dump_err_cqe(dev, err_cqe);97 98 if (qhp->attr.state == C4IW_QP_STATE_RTS) {99 attrs.next_state = C4IW_QP_STATE_TERMINATE;100 c4iw_modify_qp(qhp->rhp, qhp, C4IW_QP_ATTR_NEXT_STATE,101 &attrs, 0);102 }103 104 event.event = ib_event;105 event.device = chp->ibcq.device;106 if (ib_event == IB_EVENT_CQ_ERR)107 event.element.cq = &chp->ibcq;108 else109 event.element.qp = &qhp->ibqp;110 if (qhp->ibqp.event_handler)111 (*qhp->ibqp.event_handler)(&event, qhp->ibqp.qp_context);112 113 if (t4_clear_cq_armed(&chp->cq)) {114 spin_lock_irqsave(&chp->comp_handler_lock, flag);115 (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);116 spin_unlock_irqrestore(&chp->comp_handler_lock, flag);117 }118}119 120void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe)121{122 struct c4iw_cq *chp;123 struct c4iw_qp *qhp;124 u32 cqid;125 126 xa_lock_irq(&dev->qps);127 qhp = xa_load(&dev->qps, CQE_QPID(err_cqe));128 if (!qhp) {129 pr_err("BAD AE qpid 0x%x opcode %d status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n",130 CQE_QPID(err_cqe),131 CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe),132 CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe),133 CQE_WRID_LOW(err_cqe));134 xa_unlock_irq(&dev->qps);135 goto out;136 }137 138 if (SQ_TYPE(err_cqe))139 cqid = qhp->attr.scq;140 else141 cqid = qhp->attr.rcq;142 chp = get_chp(dev, cqid);143 if (!chp) {144 pr_err("BAD AE cqid 0x%x qpid 0x%x opcode %d status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n",145 cqid, CQE_QPID(err_cqe),146 CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe),147 CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe),148 CQE_WRID_LOW(err_cqe));149 xa_unlock_irq(&dev->qps);150 goto out;151 }152 153 c4iw_qp_add_ref(&qhp->ibqp);154 refcount_inc(&chp->refcnt);155 xa_unlock_irq(&dev->qps);156 157 /* Bad incoming write */158 if (RQ_TYPE(err_cqe) &&159 (CQE_OPCODE(err_cqe) == FW_RI_RDMA_WRITE)) {160 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_REQ_ERR);161 goto done;162 }163 164 switch (CQE_STATUS(err_cqe)) {165 166 /* Completion Events */167 case T4_ERR_SUCCESS:168 pr_err("AE with status 0!\n");169 break;170 171 case T4_ERR_STAG:172 case T4_ERR_PDID:173 case T4_ERR_QPID:174 case T4_ERR_ACCESS:175 case T4_ERR_WRAP:176 case T4_ERR_BOUND:177 case T4_ERR_INVALIDATE_SHARED_MR:178 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:179 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_ACCESS_ERR);180 break;181 182 /* Device Fatal Errors */183 case T4_ERR_ECC:184 case T4_ERR_ECC_PSTAG:185 case T4_ERR_INTERNAL_ERR:186 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_DEVICE_FATAL);187 break;188 189 /* QP Fatal Errors */190 case T4_ERR_OUT_OF_RQE:191 case T4_ERR_PBL_ADDR_BOUND:192 case T4_ERR_CRC:193 case T4_ERR_MARKER:194 case T4_ERR_PDU_LEN_ERR:195 case T4_ERR_DDP_VERSION:196 case T4_ERR_RDMA_VERSION:197 case T4_ERR_OPCODE:198 case T4_ERR_DDP_QUEUE_NUM:199 case T4_ERR_MSN:200 case T4_ERR_TBIT:201 case T4_ERR_MO:202 case T4_ERR_MSN_GAP:203 case T4_ERR_MSN_RANGE:204 case T4_ERR_RQE_ADDR_BOUND:205 case T4_ERR_IRD_OVERFLOW:206 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL);207 break;208 209 default:210 pr_err("Unknown T4 status 0x%x QPID 0x%x\n",211 CQE_STATUS(err_cqe), qhp->wq.sq.qid);212 post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL);213 break;214 }215done:216 c4iw_cq_rem_ref(chp);217 c4iw_qp_rem_ref(&qhp->ibqp);218out:219 return;220}221 222int c4iw_ev_handler(struct c4iw_dev *dev, u32 qid)223{224 struct c4iw_cq *chp;225 unsigned long flag;226 227 xa_lock_irqsave(&dev->cqs, flag);228 chp = xa_load(&dev->cqs, qid);229 if (chp) {230 refcount_inc(&chp->refcnt);231 xa_unlock_irqrestore(&dev->cqs, flag);232 t4_clear_cq_armed(&chp->cq);233 spin_lock_irqsave(&chp->comp_handler_lock, flag);234 (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);235 spin_unlock_irqrestore(&chp->comp_handler_lock, flag);236 c4iw_cq_rem_ref(chp);237 } else {238 pr_debug("unknown cqid 0x%x\n", qid);239 xa_unlock_irqrestore(&dev->cqs, flag);240 }241 return 0;242}243