102 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */2/*3 * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.4 */5 6#ifndef _EFA_REGS_H_7#define _EFA_REGS_H_8 9enum efa_regs_reset_reason_types {10 EFA_REGS_RESET_NORMAL = 0,11 /* Keep alive timeout */12 EFA_REGS_RESET_KEEP_ALIVE_TO = 1,13 EFA_REGS_RESET_ADMIN_TO = 2,14 EFA_REGS_RESET_INIT_ERR = 3,15 EFA_REGS_RESET_DRIVER_INVALID_STATE = 4,16 EFA_REGS_RESET_OS_TRIGGER = 5,17 EFA_REGS_RESET_SHUTDOWN = 6,18 EFA_REGS_RESET_USER_TRIGGER = 7,19 EFA_REGS_RESET_GENERIC = 8,20};21 22/* efa_registers offsets */23 24/* 0 base */25#define EFA_REGS_VERSION_OFF 0x026#define EFA_REGS_CONTROLLER_VERSION_OFF 0x427#define EFA_REGS_CAPS_OFF 0x828#define EFA_REGS_AQ_BASE_LO_OFF 0x1029#define EFA_REGS_AQ_BASE_HI_OFF 0x1430#define EFA_REGS_AQ_CAPS_OFF 0x1831#define EFA_REGS_ACQ_BASE_LO_OFF 0x2032#define EFA_REGS_ACQ_BASE_HI_OFF 0x2433#define EFA_REGS_ACQ_CAPS_OFF 0x2834#define EFA_REGS_AQ_PROD_DB_OFF 0x2c35#define EFA_REGS_AENQ_CAPS_OFF 0x3436#define EFA_REGS_AENQ_BASE_LO_OFF 0x3837#define EFA_REGS_AENQ_BASE_HI_OFF 0x3c38#define EFA_REGS_AENQ_CONS_DB_OFF 0x4039#define EFA_REGS_INTR_MASK_OFF 0x4c40#define EFA_REGS_DEV_CTL_OFF 0x5441#define EFA_REGS_DEV_STS_OFF 0x5842#define EFA_REGS_MMIO_REG_READ_OFF 0x5c43#define EFA_REGS_MMIO_RESP_LO_OFF 0x6044#define EFA_REGS_MMIO_RESP_HI_OFF 0x6445#define EFA_REGS_EQ_DB_OFF 0x6846 47/* version register */48#define EFA_REGS_VERSION_MINOR_VERSION_MASK 0xff49#define EFA_REGS_VERSION_MAJOR_VERSION_MASK 0xff0050 51/* controller_version register */52#define EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff53#define EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff0054#define EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff000055#define EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff00000056 57/* caps register */58#define EFA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x159#define EFA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e60#define EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff0061#define EFA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf000062 63/* aq_caps register */64#define EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff65#define EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff000066 67/* acq_caps register */68#define EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff69#define EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xff000070#define EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK 0xff00000071 72/* aenq_caps register */73#define EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff74#define EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xff000075#define EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK 0xff00000076 77/* intr_mask register */78#define EFA_REGS_INTR_MASK_EN_MASK 0x179 80/* dev_ctl register */81#define EFA_REGS_DEV_CTL_DEV_RESET_MASK 0x182#define EFA_REGS_DEV_CTL_AQ_RESTART_MASK 0x283#define EFA_REGS_DEV_CTL_RESET_REASON_MASK 0xf000000084 85/* dev_sts register */86#define EFA_REGS_DEV_STS_READY_MASK 0x187#define EFA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x288#define EFA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x489#define EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x890#define EFA_REGS_DEV_STS_RESET_FINISHED_MASK 0x1091#define EFA_REGS_DEV_STS_FATAL_ERROR_MASK 0x2092 93/* mmio_reg_read register */94#define EFA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff95#define EFA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff000096 97/* eq_db register */98#define EFA_REGS_EQ_DB_EQN_MASK 0xffff99#define EFA_REGS_EQ_DB_ARM_MASK 0x80000000100 101#endif /* _EFA_REGS_H_ */102